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stm32l431xx.h
[詳解]
1
33#ifndef __STM32L431xx_H
34#define __STM32L431xx_H
35
36#ifdef __cplusplus
37 extern "C" {
38#endif /* __cplusplus */
39
47#define __CM4_REV 0x0001U
48#define __MPU_PRESENT 1U
49#define __NVIC_PRIO_BITS 4U
50#define __Vendor_SysTickConfig 0U
51#define __FPU_PRESENT 1U
65typedef enum
66{
67/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
68 NonMaskableInt_IRQn = -14,
69 HardFault_IRQn = -13,
70 MemoryManagement_IRQn = -12,
71 BusFault_IRQn = -11,
72 UsageFault_IRQn = -10,
73 SVCall_IRQn = -5,
74 DebugMonitor_IRQn = -4,
75 PendSV_IRQn = -2,
76 SysTick_IRQn = -1,
77/****** STM32 specific Interrupt Numbers **********************************************************************/
78 WWDG_IRQn = 0,
79 PVD_PVM_IRQn = 1,
80 TAMP_STAMP_IRQn = 2,
81 RTC_WKUP_IRQn = 3,
82 FLASH_IRQn = 4,
83 RCC_IRQn = 5,
84 EXTI0_IRQn = 6,
85 EXTI1_IRQn = 7,
86 EXTI2_IRQn = 8,
87 EXTI3_IRQn = 9,
88 EXTI4_IRQn = 10,
89 DMA1_Channel1_IRQn = 11,
90 DMA1_Channel2_IRQn = 12,
91 DMA1_Channel3_IRQn = 13,
92 DMA1_Channel4_IRQn = 14,
93 DMA1_Channel5_IRQn = 15,
94 DMA1_Channel6_IRQn = 16,
95 DMA1_Channel7_IRQn = 17,
96 ADC1_IRQn = 18,
97 CAN1_TX_IRQn = 19,
98 CAN1_RX0_IRQn = 20,
99 CAN1_RX1_IRQn = 21,
100 CAN1_SCE_IRQn = 22,
101 EXTI9_5_IRQn = 23,
102 TIM1_BRK_TIM15_IRQn = 24,
103 TIM1_UP_TIM16_IRQn = 25,
104 TIM1_TRG_COM_IRQn = 26,
105 TIM1_CC_IRQn = 27,
106 TIM2_IRQn = 28,
107 I2C1_EV_IRQn = 31,
108 I2C1_ER_IRQn = 32,
109 I2C2_EV_IRQn = 33,
110 I2C2_ER_IRQn = 34,
111 SPI1_IRQn = 35,
112 SPI2_IRQn = 36,
113 USART1_IRQn = 37,
114 USART2_IRQn = 38,
115 USART3_IRQn = 39,
116 EXTI15_10_IRQn = 40,
117 RTC_Alarm_IRQn = 41,
118 SDMMC1_IRQn = 49,
119 SPI3_IRQn = 51,
120 TIM6_DAC_IRQn = 54,
121 TIM7_IRQn = 55,
122 DMA2_Channel1_IRQn = 56,
123 DMA2_Channel2_IRQn = 57,
124 DMA2_Channel3_IRQn = 58,
125 DMA2_Channel4_IRQn = 59,
126 DMA2_Channel5_IRQn = 60,
127 COMP_IRQn = 64,
128 LPTIM1_IRQn = 65,
129 LPTIM2_IRQn = 66,
130 DMA2_Channel6_IRQn = 68,
131 DMA2_Channel7_IRQn = 69,
132 LPUART1_IRQn = 70,
133 QUADSPI_IRQn = 71,
134 I2C3_EV_IRQn = 72,
135 I2C3_ER_IRQn = 73,
136 SAI1_IRQn = 74,
137 SWPMI1_IRQn = 76,
138 TSC_IRQn = 77,
139 RNG_IRQn = 80,
140 FPU_IRQn = 81,
141 CRS_IRQn = 82
142} IRQn_Type;
143
148#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
149#include "system_stm32l4xx.h"
150#include <stdint.h>
151
160typedef struct
161{
162 __IO uint32_t ISR;
163 __IO uint32_t IER;
164 __IO uint32_t CR;
165 __IO uint32_t CFGR;
166 __IO uint32_t CFGR2;
167 __IO uint32_t SMPR1;
168 __IO uint32_t SMPR2;
169 uint32_t RESERVED1;
170 __IO uint32_t TR1;
171 __IO uint32_t TR2;
172 __IO uint32_t TR3;
173 uint32_t RESERVED2;
174 __IO uint32_t SQR1;
175 __IO uint32_t SQR2;
176 __IO uint32_t SQR3;
177 __IO uint32_t SQR4;
178 __IO uint32_t DR;
179 uint32_t RESERVED3;
180 uint32_t RESERVED4;
181 __IO uint32_t JSQR;
182 uint32_t RESERVED5[4];
183 __IO uint32_t OFR1;
184 __IO uint32_t OFR2;
185 __IO uint32_t OFR3;
186 __IO uint32_t OFR4;
187 uint32_t RESERVED6[4];
188 __IO uint32_t JDR1;
189 __IO uint32_t JDR2;
190 __IO uint32_t JDR3;
191 __IO uint32_t JDR4;
192 uint32_t RESERVED7[4];
193 __IO uint32_t AWD2CR;
194 __IO uint32_t AWD3CR;
195 uint32_t RESERVED8;
196 uint32_t RESERVED9;
197 __IO uint32_t DIFSEL;
198 __IO uint32_t CALFACT;
200} ADC_TypeDef;
201
202typedef struct
203{
204 uint32_t RESERVED1;
205 uint32_t RESERVED2;
206 __IO uint32_t CCR;
207 uint32_t RESERVED3;
208} ADC_Common_TypeDef;
209
210
215typedef struct
216{
217 __IO uint32_t TIR;
218 __IO uint32_t TDTR;
219 __IO uint32_t TDLR;
220 __IO uint32_t TDHR;
221} CAN_TxMailBox_TypeDef;
222
227typedef struct
228{
229 __IO uint32_t RIR;
230 __IO uint32_t RDTR;
231 __IO uint32_t RDLR;
232 __IO uint32_t RDHR;
233} CAN_FIFOMailBox_TypeDef;
234
239typedef struct
240{
241 __IO uint32_t FR1;
242 __IO uint32_t FR2;
243} CAN_FilterRegister_TypeDef;
244
249typedef struct
250{
251 __IO uint32_t MCR;
252 __IO uint32_t MSR;
253 __IO uint32_t TSR;
254 __IO uint32_t RF0R;
255 __IO uint32_t RF1R;
256 __IO uint32_t IER;
257 __IO uint32_t ESR;
258 __IO uint32_t BTR;
259 uint32_t RESERVED0[88];
260 CAN_TxMailBox_TypeDef sTxMailBox[3];
261 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
262 uint32_t RESERVED1[12];
263 __IO uint32_t FMR;
264 __IO uint32_t FM1R;
265 uint32_t RESERVED2;
266 __IO uint32_t FS1R;
267 uint32_t RESERVED3;
268 __IO uint32_t FFA1R;
269 uint32_t RESERVED4;
270 __IO uint32_t FA1R;
271 uint32_t RESERVED5[8];
272 CAN_FilterRegister_TypeDef sFilterRegister[28];
273} CAN_TypeDef;
274
275
280typedef struct
281{
282 __IO uint32_t CSR;
283} COMP_TypeDef;
284
285typedef struct
286{
287 __IO uint32_t CSR;
288} COMP_Common_TypeDef;
289
294typedef struct
295{
296 __IO uint32_t DR;
297 __IO uint8_t IDR;
298 uint8_t RESERVED0;
299 uint16_t RESERVED1;
300 __IO uint32_t CR;
301 uint32_t RESERVED2;
302 __IO uint32_t INIT;
303 __IO uint32_t POL;
304} CRC_TypeDef;
305
309typedef struct
310{
311__IO uint32_t CR;
312__IO uint32_t CFGR;
313__IO uint32_t ISR;
314__IO uint32_t ICR;
315} CRS_TypeDef;
316
321typedef struct
322{
323 __IO uint32_t CR;
324 __IO uint32_t SWTRIGR;
325 __IO uint32_t DHR12R1;
326 __IO uint32_t DHR12L1;
327 __IO uint32_t DHR8R1;
328 __IO uint32_t DHR12R2;
329 __IO uint32_t DHR12L2;
330 __IO uint32_t DHR8R2;
331 __IO uint32_t DHR12RD;
332 __IO uint32_t DHR12LD;
333 __IO uint32_t DHR8RD;
334 __IO uint32_t DOR1;
335 __IO uint32_t DOR2;
336 __IO uint32_t SR;
337 __IO uint32_t CCR;
338 __IO uint32_t MCR;
339 __IO uint32_t SHSR1;
340 __IO uint32_t SHSR2;
341 __IO uint32_t SHHR;
342 __IO uint32_t SHRR;
343} DAC_TypeDef;
344
345
350typedef struct
351{
352 __IO uint32_t IDCODE;
353 __IO uint32_t CR;
354 __IO uint32_t APB1FZR1;
355 __IO uint32_t APB1FZR2;
356 __IO uint32_t APB2FZ;
357} DBGMCU_TypeDef;
358
359
364typedef struct
365{
366 __IO uint32_t CCR;
367 __IO uint32_t CNDTR;
368 __IO uint32_t CPAR;
369 __IO uint32_t CMAR;
370} DMA_Channel_TypeDef;
371
372typedef struct
373{
374 __IO uint32_t ISR;
375 __IO uint32_t IFCR;
376} DMA_TypeDef;
377
378typedef struct
379{
380 __IO uint32_t CSELR;
381} DMA_Request_TypeDef;
382
383/* Legacy define */
384#define DMA_request_TypeDef DMA_Request_TypeDef
385
386
391typedef struct
392{
393 __IO uint32_t IMR1;
394 __IO uint32_t EMR1;
395 __IO uint32_t RTSR1;
396 __IO uint32_t FTSR1;
397 __IO uint32_t SWIER1;
398 __IO uint32_t PR1;
399 uint32_t RESERVED1;
400 uint32_t RESERVED2;
401 __IO uint32_t IMR2;
402 __IO uint32_t EMR2;
403 __IO uint32_t RTSR2;
404 __IO uint32_t FTSR2;
405 __IO uint32_t SWIER2;
406 __IO uint32_t PR2;
407} EXTI_TypeDef;
408
409
414typedef struct
415{
416 __IO uint32_t CSSA;
417 __IO uint32_t CSL;
418 __IO uint32_t NVDSSA;
419 __IO uint32_t NVDSL;
420 __IO uint32_t VDSSA ;
421 __IO uint32_t VDSL ;
422 uint32_t RESERVED1;
423 uint32_t RESERVED2;
424 __IO uint32_t CR ;
425} FIREWALL_TypeDef;
426
427
432typedef struct
433{
434 __IO uint32_t ACR;
435 __IO uint32_t PDKEYR;
436 __IO uint32_t KEYR;
437 __IO uint32_t OPTKEYR;
438 __IO uint32_t SR;
439 __IO uint32_t CR;
440 __IO uint32_t ECCR;
441 __IO uint32_t RESERVED1;
442 __IO uint32_t OPTR;
443 __IO uint32_t PCROP1SR;
444 __IO uint32_t PCROP1ER;
445 __IO uint32_t WRP1AR;
446 __IO uint32_t WRP1BR;
447} FLASH_TypeDef;
448
449
450
455typedef struct
456{
457 __IO uint32_t MODER;
458 __IO uint32_t OTYPER;
459 __IO uint32_t OSPEEDR;
460 __IO uint32_t PUPDR;
461 __IO uint32_t IDR;
462 __IO uint32_t ODR;
463 __IO uint32_t BSRR;
464 __IO uint32_t LCKR;
465 __IO uint32_t AFR[2];
466 __IO uint32_t BRR;
468} GPIO_TypeDef;
469
470
475typedef struct
476{
477 __IO uint32_t CR1;
478 __IO uint32_t CR2;
479 __IO uint32_t OAR1;
480 __IO uint32_t OAR2;
481 __IO uint32_t TIMINGR;
482 __IO uint32_t TIMEOUTR;
483 __IO uint32_t ISR;
484 __IO uint32_t ICR;
485 __IO uint32_t PECR;
486 __IO uint32_t RXDR;
487 __IO uint32_t TXDR;
488} I2C_TypeDef;
489
494typedef struct
495{
496 __IO uint32_t KR;
497 __IO uint32_t PR;
498 __IO uint32_t RLR;
499 __IO uint32_t SR;
500 __IO uint32_t WINR;
501} IWDG_TypeDef;
502
506typedef struct
507{
508 __IO uint32_t ISR;
509 __IO uint32_t ICR;
510 __IO uint32_t IER;
511 __IO uint32_t CFGR;
512 __IO uint32_t CR;
513 __IO uint32_t CMP;
514 __IO uint32_t ARR;
515 __IO uint32_t CNT;
516 __IO uint32_t OR;
517} LPTIM_TypeDef;
518
523typedef struct
524{
525 __IO uint32_t CSR;
526 __IO uint32_t OTR;
527 __IO uint32_t LPOTR;
528} OPAMP_TypeDef;
529
530typedef struct
531{
532 __IO uint32_t CSR;
533} OPAMP_Common_TypeDef;
534
539typedef struct
540{
541 __IO uint32_t CR1;
542 __IO uint32_t CR2;
543 __IO uint32_t CR3;
544 __IO uint32_t CR4;
545 __IO uint32_t SR1;
546 __IO uint32_t SR2;
547 __IO uint32_t SCR;
548 uint32_t RESERVED;
549 __IO uint32_t PUCRA;
550 __IO uint32_t PDCRA;
551 __IO uint32_t PUCRB;
552 __IO uint32_t PDCRB;
553 __IO uint32_t PUCRC;
554 __IO uint32_t PDCRC;
555 __IO uint32_t PUCRD;
556 __IO uint32_t PDCRD;
557 __IO uint32_t PUCRE;
558 __IO uint32_t PDCRE;
559 uint32_t RESERVED1;
560 uint32_t RESERVED2;
561 uint32_t RESERVED3;
562 uint32_t RESERVED4;
563 __IO uint32_t PUCRH;
564 __IO uint32_t PDCRH;
565} PWR_TypeDef;
566
567
572typedef struct
573{
574 __IO uint32_t CR;
575 __IO uint32_t DCR;
576 __IO uint32_t SR;
577 __IO uint32_t FCR;
578 __IO uint32_t DLR;
579 __IO uint32_t CCR;
580 __IO uint32_t AR;
581 __IO uint32_t ABR;
582 __IO uint32_t DR;
583 __IO uint32_t PSMKR;
584 __IO uint32_t PSMAR;
585 __IO uint32_t PIR;
586 __IO uint32_t LPTR;
587} QUADSPI_TypeDef;
588
589
594typedef struct
595{
596 __IO uint32_t CR;
597 __IO uint32_t ICSCR;
598 __IO uint32_t CFGR;
599 __IO uint32_t PLLCFGR;
600 __IO uint32_t PLLSAI1CFGR;
601 uint32_t RESERVED;
602 __IO uint32_t CIER;
603 __IO uint32_t CIFR;
604 __IO uint32_t CICR;
605 uint32_t RESERVED0;
606 __IO uint32_t AHB1RSTR;
607 __IO uint32_t AHB2RSTR;
608 __IO uint32_t AHB3RSTR;
609 uint32_t RESERVED1;
610 __IO uint32_t APB1RSTR1;
611 __IO uint32_t APB1RSTR2;
612 __IO uint32_t APB2RSTR;
613 uint32_t RESERVED2;
614 __IO uint32_t AHB1ENR;
615 __IO uint32_t AHB2ENR;
616 __IO uint32_t AHB3ENR;
617 uint32_t RESERVED3;
618 __IO uint32_t APB1ENR1;
619 __IO uint32_t APB1ENR2;
620 __IO uint32_t APB2ENR;
621 uint32_t RESERVED4;
622 __IO uint32_t AHB1SMENR;
623 __IO uint32_t AHB2SMENR;
624 __IO uint32_t AHB3SMENR;
625 uint32_t RESERVED5;
626 __IO uint32_t APB1SMENR1;
627 __IO uint32_t APB1SMENR2;
628 __IO uint32_t APB2SMENR;
629 uint32_t RESERVED6;
630 __IO uint32_t CCIPR;
631 uint32_t RESERVED7;
632 __IO uint32_t BDCR;
633 __IO uint32_t CSR;
634 __IO uint32_t CRRCR;
635} RCC_TypeDef;
636
641typedef struct
642{
643 __IO uint32_t TR;
644 __IO uint32_t DR;
645 __IO uint32_t CR;
646 __IO uint32_t ISR;
647 __IO uint32_t PRER;
648 __IO uint32_t WUTR;
649 uint32_t reserved;
650 __IO uint32_t ALRMAR;
651 __IO uint32_t ALRMBR;
652 __IO uint32_t WPR;
653 __IO uint32_t SSR;
654 __IO uint32_t SHIFTR;
655 __IO uint32_t TSTR;
656 __IO uint32_t TSDR;
657 __IO uint32_t TSSSR;
658 __IO uint32_t CALR;
659 __IO uint32_t TAMPCR;
660 __IO uint32_t ALRMASSR;
661 __IO uint32_t ALRMBSSR;
662 __IO uint32_t OR;
663 __IO uint32_t BKP0R;
664 __IO uint32_t BKP1R;
665 __IO uint32_t BKP2R;
666 __IO uint32_t BKP3R;
667 __IO uint32_t BKP4R;
668 __IO uint32_t BKP5R;
669 __IO uint32_t BKP6R;
670 __IO uint32_t BKP7R;
671 __IO uint32_t BKP8R;
672 __IO uint32_t BKP9R;
673 __IO uint32_t BKP10R;
674 __IO uint32_t BKP11R;
675 __IO uint32_t BKP12R;
676 __IO uint32_t BKP13R;
677 __IO uint32_t BKP14R;
678 __IO uint32_t BKP15R;
679 __IO uint32_t BKP16R;
680 __IO uint32_t BKP17R;
681 __IO uint32_t BKP18R;
682 __IO uint32_t BKP19R;
683 __IO uint32_t BKP20R;
684 __IO uint32_t BKP21R;
685 __IO uint32_t BKP22R;
686 __IO uint32_t BKP23R;
687 __IO uint32_t BKP24R;
688 __IO uint32_t BKP25R;
689 __IO uint32_t BKP26R;
690 __IO uint32_t BKP27R;
691 __IO uint32_t BKP28R;
692 __IO uint32_t BKP29R;
693 __IO uint32_t BKP30R;
694 __IO uint32_t BKP31R;
695} RTC_TypeDef;
696
701typedef struct
702{
703 __IO uint32_t GCR;
704} SAI_TypeDef;
705
706typedef struct
707{
708 __IO uint32_t CR1;
709 __IO uint32_t CR2;
710 __IO uint32_t FRCR;
711 __IO uint32_t SLOTR;
712 __IO uint32_t IMR;
713 __IO uint32_t SR;
714 __IO uint32_t CLRFR;
715 __IO uint32_t DR;
716} SAI_Block_TypeDef;
717
718
723typedef struct
724{
725 __IO uint32_t POWER;
726 __IO uint32_t CLKCR;
727 __IO uint32_t ARG;
728 __IO uint32_t CMD;
729 __I uint32_t RESPCMD;
730 __I uint32_t RESP1;
731 __I uint32_t RESP2;
732 __I uint32_t RESP3;
733 __I uint32_t RESP4;
734 __IO uint32_t DTIMER;
735 __IO uint32_t DLEN;
736 __IO uint32_t DCTRL;
737 __I uint32_t DCOUNT;
738 __I uint32_t STA;
739 __IO uint32_t ICR;
740 __IO uint32_t MASK;
741 uint32_t RESERVED0[2];
742 __I uint32_t FIFOCNT;
743 uint32_t RESERVED1[13];
744 __IO uint32_t FIFO;
745} SDMMC_TypeDef;
746
747
752typedef struct
753{
754 __IO uint32_t CR1;
755 __IO uint32_t CR2;
756 __IO uint32_t SR;
757 __IO uint32_t DR;
758 __IO uint32_t CRCPR;
759 __IO uint32_t RXCRCR;
760 __IO uint32_t TXCRCR;
761} SPI_TypeDef;
762
763
768typedef struct
769{
770 __IO uint32_t CR;
771 __IO uint32_t BRR;
772 uint32_t RESERVED1;
773 __IO uint32_t ISR;
774 __IO uint32_t ICR;
775 __IO uint32_t IER;
776 __IO uint32_t RFL;
777 __IO uint32_t TDR;
778 __IO uint32_t RDR;
779 __IO uint32_t OR;
780} SWPMI_TypeDef;
781
782
787typedef struct
788{
789 __IO uint32_t MEMRMP;
790 __IO uint32_t CFGR1;
791 __IO uint32_t EXTICR[4];
792 __IO uint32_t SCSR;
793 __IO uint32_t CFGR2;
794 __IO uint32_t SWPR;
795 __IO uint32_t SKR;
796} SYSCFG_TypeDef;
797
798
803typedef struct
804{
805 __IO uint32_t CR1;
806 __IO uint32_t CR2;
807 __IO uint32_t SMCR;
808 __IO uint32_t DIER;
809 __IO uint32_t SR;
810 __IO uint32_t EGR;
811 __IO uint32_t CCMR1;
812 __IO uint32_t CCMR2;
813 __IO uint32_t CCER;
814 __IO uint32_t CNT;
815 __IO uint32_t PSC;
816 __IO uint32_t ARR;
817 __IO uint32_t RCR;
818 __IO uint32_t CCR1;
819 __IO uint32_t CCR2;
820 __IO uint32_t CCR3;
821 __IO uint32_t CCR4;
822 __IO uint32_t BDTR;
823 __IO uint32_t DCR;
824 __IO uint32_t DMAR;
825 __IO uint32_t OR1;
826 __IO uint32_t CCMR3;
827 __IO uint32_t CCR5;
828 __IO uint32_t CCR6;
829 __IO uint32_t OR2;
830 __IO uint32_t OR3;
831} TIM_TypeDef;
832
833
838typedef struct
839{
840 __IO uint32_t CR;
841 __IO uint32_t IER;
842 __IO uint32_t ICR;
843 __IO uint32_t ISR;
844 __IO uint32_t IOHCR;
845 uint32_t RESERVED1;
846 __IO uint32_t IOASCR;
847 uint32_t RESERVED2;
848 __IO uint32_t IOSCR;
849 uint32_t RESERVED3;
850 __IO uint32_t IOCCR;
851 uint32_t RESERVED4;
852 __IO uint32_t IOGCSR;
853 __IO uint32_t IOGXCR[7];
854} TSC_TypeDef;
855
860typedef struct
861{
862 __IO uint32_t CR1;
863 __IO uint32_t CR2;
864 __IO uint32_t CR3;
865 __IO uint32_t BRR;
866 __IO uint16_t GTPR;
867 uint16_t RESERVED2;
868 __IO uint32_t RTOR;
869 __IO uint16_t RQR;
870 uint16_t RESERVED3;
871 __IO uint32_t ISR;
872 __IO uint32_t ICR;
873 __IO uint16_t RDR;
874 uint16_t RESERVED4;
875 __IO uint16_t TDR;
876 uint16_t RESERVED5;
877} USART_TypeDef;
878
883typedef struct
884{
885 __IO uint32_t CSR;
886 __IO uint32_t CCR;
887} VREFBUF_TypeDef;
888
893typedef struct
894{
895 __IO uint32_t CR;
896 __IO uint32_t CFR;
897 __IO uint32_t SR;
898} WWDG_TypeDef;
899
904typedef struct
905{
906 __IO uint32_t CR;
907 __IO uint32_t SR;
908 __IO uint32_t DR;
909} RNG_TypeDef;
910
918#define FLASH_BASE (0x08000000UL)
919#define FLASH_END (0x0803FFFFUL)
920#define FLASH_BANK1_END (0x0803FFFFUL)
921#define SRAM1_BASE (0x20000000UL)
922#define SRAM2_BASE (0x10000000UL)
923#define PERIPH_BASE (0x40000000UL)
924#define QSPI_BASE (0x90000000UL)
926#define QSPI_R_BASE (0xA0001000UL)
927#define SRAM1_BB_BASE (0x22000000UL)
928#define PERIPH_BB_BASE (0x42000000UL)
930/* Legacy defines */
931#define SRAM_BASE SRAM1_BASE
932#define SRAM_BB_BASE SRAM1_BB_BASE
933
934#define SRAM1_SIZE_MAX (0x0000C000UL)
935#define SRAM2_SIZE (0x00004000UL)
937#define FLASH_SIZE_DATA_REGISTER ((uint32_t)0x1FFF75E0)
938
939#define FLASH_SIZE (((((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) == 0x0000FFFFU)) ? (0x100U << 10U) : \
940 (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) << 10U))
941
943#define APB1PERIPH_BASE PERIPH_BASE
944#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
945#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)
946#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL)
947
948
950#define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL)
951#define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL)
952#define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL)
953#define RTC_BASE (APB1PERIPH_BASE + 0x2800UL)
954#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL)
955#define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL)
956#define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL)
957#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL)
958#define USART2_BASE (APB1PERIPH_BASE + 0x4400UL)
959#define USART3_BASE (APB1PERIPH_BASE + 0x4800UL)
960#define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL)
961#define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL)
962#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00UL)
963#define CRS_BASE (APB1PERIPH_BASE + 0x6000UL)
964#define CAN1_BASE (APB1PERIPH_BASE + 0x6400UL)
965#define PWR_BASE (APB1PERIPH_BASE + 0x7000UL)
966#define DAC_BASE (APB1PERIPH_BASE + 0x7400UL)
967#define DAC1_BASE (APB1PERIPH_BASE + 0x7400UL)
968#define OPAMP_BASE (APB1PERIPH_BASE + 0x7800UL)
969#define OPAMP1_BASE (APB1PERIPH_BASE + 0x7800UL)
970#define LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00UL)
971#define LPUART1_BASE (APB1PERIPH_BASE + 0x8000UL)
972#define SWPMI1_BASE (APB1PERIPH_BASE + 0x8800UL)
973#define LPTIM2_BASE (APB1PERIPH_BASE + 0x9400UL)
974
975
977#define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000UL)
978#define VREFBUF_BASE (APB2PERIPH_BASE + 0x0030UL)
979#define COMP1_BASE (APB2PERIPH_BASE + 0x0200UL)
980#define COMP2_BASE (APB2PERIPH_BASE + 0x0204UL)
981#define EXTI_BASE (APB2PERIPH_BASE + 0x0400UL)
982#define FIREWALL_BASE (APB2PERIPH_BASE + 0x1C00UL)
983#define SDMMC1_BASE (APB2PERIPH_BASE + 0x2800UL)
984#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00UL)
985#define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL)
986#define USART1_BASE (APB2PERIPH_BASE + 0x3800UL)
987#define TIM15_BASE (APB2PERIPH_BASE + 0x4000UL)
988#define TIM16_BASE (APB2PERIPH_BASE + 0x4400UL)
989#define SAI1_BASE (APB2PERIPH_BASE + 0x5400UL)
990#define SAI1_Block_A_BASE (SAI1_BASE + 0x0004UL)
991#define SAI1_Block_B_BASE (SAI1_BASE + 0x0024UL)
992
994#define DMA1_BASE (AHB1PERIPH_BASE)
995#define DMA2_BASE (AHB1PERIPH_BASE + 0x0400UL)
996#define RCC_BASE (AHB1PERIPH_BASE + 0x1000UL)
997#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000UL)
998#define CRC_BASE (AHB1PERIPH_BASE + 0x3000UL)
999#define TSC_BASE (AHB1PERIPH_BASE + 0x4000UL)
1000
1001
1002#define DMA1_Channel1_BASE (DMA1_BASE + 0x0008UL)
1003#define DMA1_Channel2_BASE (DMA1_BASE + 0x001CUL)
1004#define DMA1_Channel3_BASE (DMA1_BASE + 0x0030UL)
1005#define DMA1_Channel4_BASE (DMA1_BASE + 0x0044UL)
1006#define DMA1_Channel5_BASE (DMA1_BASE + 0x0058UL)
1007#define DMA1_Channel6_BASE (DMA1_BASE + 0x006CUL)
1008#define DMA1_Channel7_BASE (DMA1_BASE + 0x0080UL)
1009#define DMA1_CSELR_BASE (DMA1_BASE + 0x00A8UL)
1010
1011
1012#define DMA2_Channel1_BASE (DMA2_BASE + 0x0008UL)
1013#define DMA2_Channel2_BASE (DMA2_BASE + 0x001CUL)
1014#define DMA2_Channel3_BASE (DMA2_BASE + 0x0030UL)
1015#define DMA2_Channel4_BASE (DMA2_BASE + 0x0044UL)
1016#define DMA2_Channel5_BASE (DMA2_BASE + 0x0058UL)
1017#define DMA2_Channel6_BASE (DMA2_BASE + 0x006CUL)
1018#define DMA2_Channel7_BASE (DMA2_BASE + 0x0080UL)
1019#define DMA2_CSELR_BASE (DMA2_BASE + 0x00A8UL)
1020
1021
1023#define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000UL)
1024#define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400UL)
1025#define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800UL)
1026#define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00UL)
1027#define GPIOE_BASE (AHB2PERIPH_BASE + 0x1000UL)
1028#define GPIOH_BASE (AHB2PERIPH_BASE + 0x1C00UL)
1029
1030
1031#define ADC1_BASE (AHB2PERIPH_BASE + 0x08040000UL)
1032#define ADC1_COMMON_BASE (AHB2PERIPH_BASE + 0x08040300UL)
1033
1034
1035#define RNG_BASE (AHB2PERIPH_BASE + 0x08060800UL)
1036
1037
1038
1039/* Debug MCU registers base address */
1040#define DBGMCU_BASE (0xE0042000UL)
1041
1042
1043#define PACKAGE_BASE (0x1FFF7500UL)
1044#define UID_BASE (0x1FFF7590UL)
1045#define FLASHSIZE_BASE (0x1FFF75E0UL)
1053#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
1054#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
1055#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
1056#define RTC ((RTC_TypeDef *) RTC_BASE)
1057#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
1058#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
1059#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
1060#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
1061#define USART2 ((USART_TypeDef *) USART2_BASE)
1062#define USART3 ((USART_TypeDef *) USART3_BASE)
1063#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
1064#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
1065#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
1066#define CRS ((CRS_TypeDef *) CRS_BASE)
1067#define CAN ((CAN_TypeDef *) CAN1_BASE)
1068#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
1069#define PWR ((PWR_TypeDef *) PWR_BASE)
1070#define DAC ((DAC_TypeDef *) DAC1_BASE)
1071#define DAC1 ((DAC_TypeDef *) DAC1_BASE)
1072#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
1073#define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)
1074#define OPAMP1_COMMON ((OPAMP_Common_TypeDef *) OPAMP1_BASE)
1075#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
1076#define LPUART1 ((USART_TypeDef *) LPUART1_BASE)
1077#define SWPMI1 ((SWPMI_TypeDef *) SWPMI1_BASE)
1078#define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE)
1079
1080#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
1081#define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE)
1082#define COMP1 ((COMP_TypeDef *) COMP1_BASE)
1083#define COMP2 ((COMP_TypeDef *) COMP2_BASE)
1084#define COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE)
1085#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
1086#define FIREWALL ((FIREWALL_TypeDef *) FIREWALL_BASE)
1087#define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)
1088#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
1089#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
1090#define USART1 ((USART_TypeDef *) USART1_BASE)
1091#define TIM15 ((TIM_TypeDef *) TIM15_BASE)
1092#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
1093#define SAI1 ((SAI_TypeDef *) SAI1_BASE)
1094#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
1095#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
1096#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
1097#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
1098#define RCC ((RCC_TypeDef *) RCC_BASE)
1099#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
1100#define CRC ((CRC_TypeDef *) CRC_BASE)
1101#define TSC ((TSC_TypeDef *) TSC_BASE)
1102
1103#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
1104#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
1105#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
1106#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
1107#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
1108#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
1109#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
1110#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_COMMON_BASE)
1111#define RNG ((RNG_TypeDef *) RNG_BASE)
1112
1113
1114#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
1115#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
1116#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
1117#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
1118#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
1119#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
1120#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
1121#define DMA1_CSELR ((DMA_Request_TypeDef *) DMA1_CSELR_BASE)
1122
1123
1124#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
1125#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
1126#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
1127#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
1128#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
1129#define DMA2_Channel6 ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE)
1130#define DMA2_Channel7 ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE)
1131#define DMA2_CSELR ((DMA_Request_TypeDef *) DMA2_CSELR_BASE)
1132
1133
1134
1135#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
1136
1137#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
1138
1150#define LSI_STARTUP_TIME 130U
1160/******************************************************************************/
1161/* Peripheral Registers_Bits_Definition */
1162/******************************************************************************/
1163
1164/******************************************************************************/
1165/* */
1166/* Analog to Digital Converter */
1167/* */
1168/******************************************************************************/
1169
1170/*
1171 * @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)
1172 */
1173/* Note: No specific macro feature on this device */
1174
1175/******************** Bit definition for ADC_ISR register *******************/
1176#define ADC_ISR_ADRDY_Pos (0U)
1177#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos)
1178#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk
1179#define ADC_ISR_EOSMP_Pos (1U)
1180#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos)
1181#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk
1182#define ADC_ISR_EOC_Pos (2U)
1183#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos)
1184#define ADC_ISR_EOC ADC_ISR_EOC_Msk
1185#define ADC_ISR_EOS_Pos (3U)
1186#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos)
1187#define ADC_ISR_EOS ADC_ISR_EOS_Msk
1188#define ADC_ISR_OVR_Pos (4U)
1189#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos)
1190#define ADC_ISR_OVR ADC_ISR_OVR_Msk
1191#define ADC_ISR_JEOC_Pos (5U)
1192#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos)
1193#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk
1194#define ADC_ISR_JEOS_Pos (6U)
1195#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos)
1196#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk
1197#define ADC_ISR_AWD1_Pos (7U)
1198#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos)
1199#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk
1200#define ADC_ISR_AWD2_Pos (8U)
1201#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos)
1202#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk
1203#define ADC_ISR_AWD3_Pos (9U)
1204#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos)
1205#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk
1206#define ADC_ISR_JQOVF_Pos (10U)
1207#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos)
1208#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk
1210/******************** Bit definition for ADC_IER register *******************/
1211#define ADC_IER_ADRDYIE_Pos (0U)
1212#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos)
1213#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk
1214#define ADC_IER_EOSMPIE_Pos (1U)
1215#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos)
1216#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk
1217#define ADC_IER_EOCIE_Pos (2U)
1218#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos)
1219#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk
1220#define ADC_IER_EOSIE_Pos (3U)
1221#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos)
1222#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk
1223#define ADC_IER_OVRIE_Pos (4U)
1224#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos)
1225#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk
1226#define ADC_IER_JEOCIE_Pos (5U)
1227#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos)
1228#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk
1229#define ADC_IER_JEOSIE_Pos (6U)
1230#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos)
1231#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk
1232#define ADC_IER_AWD1IE_Pos (7U)
1233#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos)
1234#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk
1235#define ADC_IER_AWD2IE_Pos (8U)
1236#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos)
1237#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk
1238#define ADC_IER_AWD3IE_Pos (9U)
1239#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos)
1240#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk
1241#define ADC_IER_JQOVFIE_Pos (10U)
1242#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos)
1243#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk
1245/* Legacy defines */
1246#define ADC_IER_ADRDY (ADC_IER_ADRDYIE)
1247#define ADC_IER_EOSMP (ADC_IER_EOSMPIE)
1248#define ADC_IER_EOC (ADC_IER_EOCIE)
1249#define ADC_IER_EOS (ADC_IER_EOSIE)
1250#define ADC_IER_OVR (ADC_IER_OVRIE)
1251#define ADC_IER_JEOC (ADC_IER_JEOCIE)
1252#define ADC_IER_JEOS (ADC_IER_JEOSIE)
1253#define ADC_IER_AWD1 (ADC_IER_AWD1IE)
1254#define ADC_IER_AWD2 (ADC_IER_AWD2IE)
1255#define ADC_IER_AWD3 (ADC_IER_AWD3IE)
1256#define ADC_IER_JQOVF (ADC_IER_JQOVFIE)
1257
1258/******************** Bit definition for ADC_CR register ********************/
1259#define ADC_CR_ADEN_Pos (0U)
1260#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos)
1261#define ADC_CR_ADEN ADC_CR_ADEN_Msk
1262#define ADC_CR_ADDIS_Pos (1U)
1263#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos)
1264#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk
1265#define ADC_CR_ADSTART_Pos (2U)
1266#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos)
1267#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk
1268#define ADC_CR_JADSTART_Pos (3U)
1269#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos)
1270#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk
1271#define ADC_CR_ADSTP_Pos (4U)
1272#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos)
1273#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk
1274#define ADC_CR_JADSTP_Pos (5U)
1275#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos)
1276#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk
1277#define ADC_CR_ADVREGEN_Pos (28U)
1278#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos)
1279#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk
1280#define ADC_CR_DEEPPWD_Pos (29U)
1281#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos)
1282#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk
1283#define ADC_CR_ADCALDIF_Pos (30U)
1284#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos)
1285#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk
1286#define ADC_CR_ADCAL_Pos (31U)
1287#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos)
1288#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk
1290/******************** Bit definition for ADC_CFGR register ******************/
1291#define ADC_CFGR_DMAEN_Pos (0U)
1292#define ADC_CFGR_DMAEN_Msk (0x1UL << ADC_CFGR_DMAEN_Pos)
1293#define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk
1294#define ADC_CFGR_DMACFG_Pos (1U)
1295#define ADC_CFGR_DMACFG_Msk (0x1UL << ADC_CFGR_DMACFG_Pos)
1296#define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk
1298#define ADC_CFGR_RES_Pos (3U)
1299#define ADC_CFGR_RES_Msk (0x3UL << ADC_CFGR_RES_Pos)
1300#define ADC_CFGR_RES ADC_CFGR_RES_Msk
1301#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos)
1302#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos)
1304#define ADC_CFGR_ALIGN_Pos (5U)
1305#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos)
1306#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk
1308#define ADC_CFGR_EXTSEL_Pos (6U)
1309#define ADC_CFGR_EXTSEL_Msk (0xFUL << ADC_CFGR_EXTSEL_Pos)
1310#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk
1311#define ADC_CFGR_EXTSEL_0 (0x1UL << ADC_CFGR_EXTSEL_Pos)
1312#define ADC_CFGR_EXTSEL_1 (0x2UL << ADC_CFGR_EXTSEL_Pos)
1313#define ADC_CFGR_EXTSEL_2 (0x4UL << ADC_CFGR_EXTSEL_Pos)
1314#define ADC_CFGR_EXTSEL_3 (0x8UL << ADC_CFGR_EXTSEL_Pos)
1316#define ADC_CFGR_EXTEN_Pos (10U)
1317#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos)
1318#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk
1319#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos)
1320#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos)
1322#define ADC_CFGR_OVRMOD_Pos (12U)
1323#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos)
1324#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk
1325#define ADC_CFGR_CONT_Pos (13U)
1326#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos)
1327#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk
1328#define ADC_CFGR_AUTDLY_Pos (14U)
1329#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos)
1330#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk
1332#define ADC_CFGR_DISCEN_Pos (16U)
1333#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos)
1334#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk
1336#define ADC_CFGR_DISCNUM_Pos (17U)
1337#define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos)
1338#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk
1339#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos)
1340#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos)
1341#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos)
1343#define ADC_CFGR_JDISCEN_Pos (20U)
1344#define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos)
1345#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk
1346#define ADC_CFGR_JQM_Pos (21U)
1347#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos)
1348#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk
1349#define ADC_CFGR_AWD1SGL_Pos (22U)
1350#define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos)
1351#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk
1352#define ADC_CFGR_AWD1EN_Pos (23U)
1353#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos)
1354#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk
1355#define ADC_CFGR_JAWD1EN_Pos (24U)
1356#define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos)
1357#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk
1358#define ADC_CFGR_JAUTO_Pos (25U)
1359#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos)
1360#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk
1362#define ADC_CFGR_AWD1CH_Pos (26U)
1363#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos)
1364#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk
1365#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos)
1366#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos)
1367#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos)
1368#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos)
1369#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos)
1371#define ADC_CFGR_JQDIS_Pos (31U)
1372#define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos)
1373#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk
1375/******************** Bit definition for ADC_CFGR2 register *****************/
1376#define ADC_CFGR2_ROVSE_Pos (0U)
1377#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos)
1378#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk
1379#define ADC_CFGR2_JOVSE_Pos (1U)
1380#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos)
1381#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk
1383#define ADC_CFGR2_OVSR_Pos (2U)
1384#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos)
1385#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk
1386#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos)
1387#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos)
1388#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos)
1390#define ADC_CFGR2_OVSS_Pos (5U)
1391#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos)
1392#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk
1393#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos)
1394#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos)
1395#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos)
1396#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos)
1398#define ADC_CFGR2_TROVS_Pos (9U)
1399#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos)
1400#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk
1401#define ADC_CFGR2_ROVSM_Pos (10U)
1402#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos)
1403#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk
1405/******************** Bit definition for ADC_SMPR1 register *****************/
1406#define ADC_SMPR1_SMP0_Pos (0U)
1407#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos)
1408#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk
1409#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos)
1410#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos)
1411#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos)
1413#define ADC_SMPR1_SMP1_Pos (3U)
1414#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos)
1415#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk
1416#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos)
1417#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos)
1418#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos)
1420#define ADC_SMPR1_SMP2_Pos (6U)
1421#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos)
1422#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk
1423#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos)
1424#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos)
1425#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos)
1427#define ADC_SMPR1_SMP3_Pos (9U)
1428#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos)
1429#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk
1430#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos)
1431#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos)
1432#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos)
1434#define ADC_SMPR1_SMP4_Pos (12U)
1435#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos)
1436#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk
1437#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos)
1438#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos)
1439#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos)
1441#define ADC_SMPR1_SMP5_Pos (15U)
1442#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos)
1443#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk
1444#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos)
1445#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos)
1446#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos)
1448#define ADC_SMPR1_SMP6_Pos (18U)
1449#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos)
1450#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk
1451#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos)
1452#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos)
1453#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos)
1455#define ADC_SMPR1_SMP7_Pos (21U)
1456#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos)
1457#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk
1458#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos)
1459#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos)
1460#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos)
1462#define ADC_SMPR1_SMP8_Pos (24U)
1463#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos)
1464#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk
1465#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos)
1466#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos)
1467#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos)
1469#define ADC_SMPR1_SMP9_Pos (27U)
1470#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos)
1471#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk
1472#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos)
1473#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos)
1474#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos)
1476/******************** Bit definition for ADC_SMPR2 register *****************/
1477#define ADC_SMPR2_SMP10_Pos (0U)
1478#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos)
1479#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk
1480#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos)
1481#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos)
1482#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos)
1484#define ADC_SMPR2_SMP11_Pos (3U)
1485#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos)
1486#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk
1487#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos)
1488#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos)
1489#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos)
1491#define ADC_SMPR2_SMP12_Pos (6U)
1492#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos)
1493#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk
1494#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos)
1495#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos)
1496#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos)
1498#define ADC_SMPR2_SMP13_Pos (9U)
1499#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos)
1500#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk
1501#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos)
1502#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos)
1503#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos)
1505#define ADC_SMPR2_SMP14_Pos (12U)
1506#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos)
1507#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk
1508#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos)
1509#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos)
1510#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos)
1512#define ADC_SMPR2_SMP15_Pos (15U)
1513#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos)
1514#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk
1515#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos)
1516#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos)
1517#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos)
1519#define ADC_SMPR2_SMP16_Pos (18U)
1520#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos)
1521#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk
1522#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos)
1523#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos)
1524#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos)
1526#define ADC_SMPR2_SMP17_Pos (21U)
1527#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos)
1528#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk
1529#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos)
1530#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos)
1531#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos)
1533#define ADC_SMPR2_SMP18_Pos (24U)
1534#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos)
1535#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk
1536#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos)
1537#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos)
1538#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos)
1540/******************** Bit definition for ADC_TR1 register *******************/
1541#define ADC_TR1_LT1_Pos (0U)
1542#define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos)
1543#define ADC_TR1_LT1 ADC_TR1_LT1_Msk
1544#define ADC_TR1_LT1_0 (0x001UL << ADC_TR1_LT1_Pos)
1545#define ADC_TR1_LT1_1 (0x002UL << ADC_TR1_LT1_Pos)
1546#define ADC_TR1_LT1_2 (0x004UL << ADC_TR1_LT1_Pos)
1547#define ADC_TR1_LT1_3 (0x008UL << ADC_TR1_LT1_Pos)
1548#define ADC_TR1_LT1_4 (0x010UL << ADC_TR1_LT1_Pos)
1549#define ADC_TR1_LT1_5 (0x020UL << ADC_TR1_LT1_Pos)
1550#define ADC_TR1_LT1_6 (0x040UL << ADC_TR1_LT1_Pos)
1551#define ADC_TR1_LT1_7 (0x080UL << ADC_TR1_LT1_Pos)
1552#define ADC_TR1_LT1_8 (0x100UL << ADC_TR1_LT1_Pos)
1553#define ADC_TR1_LT1_9 (0x200UL << ADC_TR1_LT1_Pos)
1554#define ADC_TR1_LT1_10 (0x400UL << ADC_TR1_LT1_Pos)
1555#define ADC_TR1_LT1_11 (0x800UL << ADC_TR1_LT1_Pos)
1557#define ADC_TR1_HT1_Pos (16U)
1558#define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos)
1559#define ADC_TR1_HT1 ADC_TR1_HT1_Msk
1560#define ADC_TR1_HT1_0 (0x001UL << ADC_TR1_HT1_Pos)
1561#define ADC_TR1_HT1_1 (0x002UL << ADC_TR1_HT1_Pos)
1562#define ADC_TR1_HT1_2 (0x004UL << ADC_TR1_HT1_Pos)
1563#define ADC_TR1_HT1_3 (0x008UL << ADC_TR1_HT1_Pos)
1564#define ADC_TR1_HT1_4 (0x010UL << ADC_TR1_HT1_Pos)
1565#define ADC_TR1_HT1_5 (0x020UL << ADC_TR1_HT1_Pos)
1566#define ADC_TR1_HT1_6 (0x040UL << ADC_TR1_HT1_Pos)
1567#define ADC_TR1_HT1_7 (0x080UL << ADC_TR1_HT1_Pos)
1568#define ADC_TR1_HT1_8 (0x100UL << ADC_TR1_HT1_Pos)
1569#define ADC_TR1_HT1_9 (0x200UL << ADC_TR1_HT1_Pos)
1570#define ADC_TR1_HT1_10 (0x400UL << ADC_TR1_HT1_Pos)
1571#define ADC_TR1_HT1_11 (0x800UL << ADC_TR1_HT1_Pos)
1573/******************** Bit definition for ADC_TR2 register *******************/
1574#define ADC_TR2_LT2_Pos (0U)
1575#define ADC_TR2_LT2_Msk (0xFFUL << ADC_TR2_LT2_Pos)
1576#define ADC_TR2_LT2 ADC_TR2_LT2_Msk
1577#define ADC_TR2_LT2_0 (0x01UL << ADC_TR2_LT2_Pos)
1578#define ADC_TR2_LT2_1 (0x02UL << ADC_TR2_LT2_Pos)
1579#define ADC_TR2_LT2_2 (0x04UL << ADC_TR2_LT2_Pos)
1580#define ADC_TR2_LT2_3 (0x08UL << ADC_TR2_LT2_Pos)
1581#define ADC_TR2_LT2_4 (0x10UL << ADC_TR2_LT2_Pos)
1582#define ADC_TR2_LT2_5 (0x20UL << ADC_TR2_LT2_Pos)
1583#define ADC_TR2_LT2_6 (0x40UL << ADC_TR2_LT2_Pos)
1584#define ADC_TR2_LT2_7 (0x80UL << ADC_TR2_LT2_Pos)
1586#define ADC_TR2_HT2_Pos (16U)
1587#define ADC_TR2_HT2_Msk (0xFFUL << ADC_TR2_HT2_Pos)
1588#define ADC_TR2_HT2 ADC_TR2_HT2_Msk
1589#define ADC_TR2_HT2_0 (0x01UL << ADC_TR2_HT2_Pos)
1590#define ADC_TR2_HT2_1 (0x02UL << ADC_TR2_HT2_Pos)
1591#define ADC_TR2_HT2_2 (0x04UL << ADC_TR2_HT2_Pos)
1592#define ADC_TR2_HT2_3 (0x08UL << ADC_TR2_HT2_Pos)
1593#define ADC_TR2_HT2_4 (0x10UL << ADC_TR2_HT2_Pos)
1594#define ADC_TR2_HT2_5 (0x20UL << ADC_TR2_HT2_Pos)
1595#define ADC_TR2_HT2_6 (0x40UL << ADC_TR2_HT2_Pos)
1596#define ADC_TR2_HT2_7 (0x80UL << ADC_TR2_HT2_Pos)
1598/******************** Bit definition for ADC_TR3 register *******************/
1599#define ADC_TR3_LT3_Pos (0U)
1600#define ADC_TR3_LT3_Msk (0xFFUL << ADC_TR3_LT3_Pos)
1601#define ADC_TR3_LT3 ADC_TR3_LT3_Msk
1602#define ADC_TR3_LT3_0 (0x01UL << ADC_TR3_LT3_Pos)
1603#define ADC_TR3_LT3_1 (0x02UL << ADC_TR3_LT3_Pos)
1604#define ADC_TR3_LT3_2 (0x04UL << ADC_TR3_LT3_Pos)
1605#define ADC_TR3_LT3_3 (0x08UL << ADC_TR3_LT3_Pos)
1606#define ADC_TR3_LT3_4 (0x10UL << ADC_TR3_LT3_Pos)
1607#define ADC_TR3_LT3_5 (0x20UL << ADC_TR3_LT3_Pos)
1608#define ADC_TR3_LT3_6 (0x40UL << ADC_TR3_LT3_Pos)
1609#define ADC_TR3_LT3_7 (0x80UL << ADC_TR3_LT3_Pos)
1611#define ADC_TR3_HT3_Pos (16U)
1612#define ADC_TR3_HT3_Msk (0xFFUL << ADC_TR3_HT3_Pos)
1613#define ADC_TR3_HT3 ADC_TR3_HT3_Msk
1614#define ADC_TR3_HT3_0 (0x01UL << ADC_TR3_HT3_Pos)
1615#define ADC_TR3_HT3_1 (0x02UL << ADC_TR3_HT3_Pos)
1616#define ADC_TR3_HT3_2 (0x04UL << ADC_TR3_HT3_Pos)
1617#define ADC_TR3_HT3_3 (0x08UL << ADC_TR3_HT3_Pos)
1618#define ADC_TR3_HT3_4 (0x10UL << ADC_TR3_HT3_Pos)
1619#define ADC_TR3_HT3_5 (0x20UL << ADC_TR3_HT3_Pos)
1620#define ADC_TR3_HT3_6 (0x40UL << ADC_TR3_HT3_Pos)
1621#define ADC_TR3_HT3_7 (0x80UL << ADC_TR3_HT3_Pos)
1623/******************** Bit definition for ADC_SQR1 register ******************/
1624#define ADC_SQR1_L_Pos (0U)
1625#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos)
1626#define ADC_SQR1_L ADC_SQR1_L_Msk
1627#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos)
1628#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos)
1629#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos)
1630#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos)
1632#define ADC_SQR1_SQ1_Pos (6U)
1633#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos)
1634#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk
1635#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos)
1636#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos)
1637#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos)
1638#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos)
1639#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos)
1641#define ADC_SQR1_SQ2_Pos (12U)
1642#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos)
1643#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk
1644#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos)
1645#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos)
1646#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos)
1647#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos)
1648#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos)
1650#define ADC_SQR1_SQ3_Pos (18U)
1651#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos)
1652#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk
1653#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos)
1654#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos)
1655#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos)
1656#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos)
1657#define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos)
1659#define ADC_SQR1_SQ4_Pos (24U)
1660#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos)
1661#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk
1662#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos)
1663#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos)
1664#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos)
1665#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos)
1666#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos)
1668/******************** Bit definition for ADC_SQR2 register ******************/
1669#define ADC_SQR2_SQ5_Pos (0U)
1670#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos)
1671#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk
1672#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos)
1673#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos)
1674#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos)
1675#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos)
1676#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos)
1678#define ADC_SQR2_SQ6_Pos (6U)
1679#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos)
1680#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk
1681#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos)
1682#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos)
1683#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos)
1684#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos)
1685#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos)
1687#define ADC_SQR2_SQ7_Pos (12U)
1688#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos)
1689#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk
1690#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos)
1691#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos)
1692#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos)
1693#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos)
1694#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos)
1696#define ADC_SQR2_SQ8_Pos (18U)
1697#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos)
1698#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk
1699#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos)
1700#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos)
1701#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos)
1702#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos)
1703#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos)
1705#define ADC_SQR2_SQ9_Pos (24U)
1706#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos)
1707#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk
1708#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos)
1709#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos)
1710#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos)
1711#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos)
1712#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos)
1714/******************** Bit definition for ADC_SQR3 register ******************/
1715#define ADC_SQR3_SQ10_Pos (0U)
1716#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos)
1717#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk
1718#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos)
1719#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos)
1720#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos)
1721#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos)
1722#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos)
1724#define ADC_SQR3_SQ11_Pos (6U)
1725#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos)
1726#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk
1727#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos)
1728#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos)
1729#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos)
1730#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos)
1731#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos)
1733#define ADC_SQR3_SQ12_Pos (12U)
1734#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos)
1735#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk
1736#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos)
1737#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos)
1738#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos)
1739#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos)
1740#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos)
1742#define ADC_SQR3_SQ13_Pos (18U)
1743#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos)
1744#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk
1745#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos)
1746#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos)
1747#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos)
1748#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos)
1749#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos)
1751#define ADC_SQR3_SQ14_Pos (24U)
1752#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos)
1753#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk
1754#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos)
1755#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos)
1756#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos)
1757#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos)
1758#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos)
1760/******************** Bit definition for ADC_SQR4 register ******************/
1761#define ADC_SQR4_SQ15_Pos (0U)
1762#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos)
1763#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk
1764#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos)
1765#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos)
1766#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos)
1767#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos)
1768#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos)
1770#define ADC_SQR4_SQ16_Pos (6U)
1771#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos)
1772#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk
1773#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos)
1774#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos)
1775#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos)
1776#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos)
1777#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos)
1779/******************** Bit definition for ADC_DR register ********************/
1780#define ADC_DR_RDATA_Pos (0U)
1781#define ADC_DR_RDATA_Msk (0xFFFFUL << ADC_DR_RDATA_Pos)
1782#define ADC_DR_RDATA ADC_DR_RDATA_Msk
1783#define ADC_DR_RDATA_0 (0x0001UL << ADC_DR_RDATA_Pos)
1784#define ADC_DR_RDATA_1 (0x0002UL << ADC_DR_RDATA_Pos)
1785#define ADC_DR_RDATA_2 (0x0004UL << ADC_DR_RDATA_Pos)
1786#define ADC_DR_RDATA_3 (0x0008UL << ADC_DR_RDATA_Pos)
1787#define ADC_DR_RDATA_4 (0x0010UL << ADC_DR_RDATA_Pos)
1788#define ADC_DR_RDATA_5 (0x0020UL << ADC_DR_RDATA_Pos)
1789#define ADC_DR_RDATA_6 (0x0040UL << ADC_DR_RDATA_Pos)
1790#define ADC_DR_RDATA_7 (0x0080UL << ADC_DR_RDATA_Pos)
1791#define ADC_DR_RDATA_8 (0x0100UL << ADC_DR_RDATA_Pos)
1792#define ADC_DR_RDATA_9 (0x0200UL << ADC_DR_RDATA_Pos)
1793#define ADC_DR_RDATA_10 (0x0400UL << ADC_DR_RDATA_Pos)
1794#define ADC_DR_RDATA_11 (0x0800UL << ADC_DR_RDATA_Pos)
1795#define ADC_DR_RDATA_12 (0x1000UL << ADC_DR_RDATA_Pos)
1796#define ADC_DR_RDATA_13 (0x2000UL << ADC_DR_RDATA_Pos)
1797#define ADC_DR_RDATA_14 (0x4000UL << ADC_DR_RDATA_Pos)
1798#define ADC_DR_RDATA_15 (0x8000UL << ADC_DR_RDATA_Pos)
1800/******************** Bit definition for ADC_JSQR register ******************/
1801#define ADC_JSQR_JL_Pos (0U)
1802#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos)
1803#define ADC_JSQR_JL ADC_JSQR_JL_Msk
1804#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos)
1805#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos)
1807#define ADC_JSQR_JEXTSEL_Pos (2U)
1808#define ADC_JSQR_JEXTSEL_Msk (0xFUL << ADC_JSQR_JEXTSEL_Pos)
1809#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk
1810#define ADC_JSQR_JEXTSEL_0 (0x1UL << ADC_JSQR_JEXTSEL_Pos)
1811#define ADC_JSQR_JEXTSEL_1 (0x2UL << ADC_JSQR_JEXTSEL_Pos)
1812#define ADC_JSQR_JEXTSEL_2 (0x4UL << ADC_JSQR_JEXTSEL_Pos)
1813#define ADC_JSQR_JEXTSEL_3 (0x8UL << ADC_JSQR_JEXTSEL_Pos)
1815#define ADC_JSQR_JEXTEN_Pos (6U)
1816#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos)
1817#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk
1818#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos)
1819#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos)
1821#define ADC_JSQR_JSQ1_Pos (8U)
1822#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos)
1823#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk
1824#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos)
1825#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos)
1826#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos)
1827#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos)
1828#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos)
1830#define ADC_JSQR_JSQ2_Pos (14U)
1831#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos)
1832#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk
1833#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos)
1834#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos)
1835#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos)
1836#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos)
1837#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos)
1839#define ADC_JSQR_JSQ3_Pos (20U)
1840#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos)
1841#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk
1842#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos)
1843#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos)
1844#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos)
1845#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos)
1846#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos)
1848#define ADC_JSQR_JSQ4_Pos (26U)
1849#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos)
1850#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk
1851#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos)
1852#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos)
1853#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos)
1854#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos)
1855#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos)
1857/******************** Bit definition for ADC_OFR1 register ******************/
1858#define ADC_OFR1_OFFSET1_Pos (0U)
1859#define ADC_OFR1_OFFSET1_Msk (0xFFFUL << ADC_OFR1_OFFSET1_Pos)
1860#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk
1861#define ADC_OFR1_OFFSET1_0 (0x001UL << ADC_OFR1_OFFSET1_Pos)
1862#define ADC_OFR1_OFFSET1_1 (0x002UL << ADC_OFR1_OFFSET1_Pos)
1863#define ADC_OFR1_OFFSET1_2 (0x004UL << ADC_OFR1_OFFSET1_Pos)
1864#define ADC_OFR1_OFFSET1_3 (0x008UL << ADC_OFR1_OFFSET1_Pos)
1865#define ADC_OFR1_OFFSET1_4 (0x010UL << ADC_OFR1_OFFSET1_Pos)
1866#define ADC_OFR1_OFFSET1_5 (0x020UL << ADC_OFR1_OFFSET1_Pos)
1867#define ADC_OFR1_OFFSET1_6 (0x040UL << ADC_OFR1_OFFSET1_Pos)
1868#define ADC_OFR1_OFFSET1_7 (0x080UL << ADC_OFR1_OFFSET1_Pos)
1869#define ADC_OFR1_OFFSET1_8 (0x100UL << ADC_OFR1_OFFSET1_Pos)
1870#define ADC_OFR1_OFFSET1_9 (0x200UL << ADC_OFR1_OFFSET1_Pos)
1871#define ADC_OFR1_OFFSET1_10 (0x400UL << ADC_OFR1_OFFSET1_Pos)
1872#define ADC_OFR1_OFFSET1_11 (0x800UL << ADC_OFR1_OFFSET1_Pos)
1874#define ADC_OFR1_OFFSET1_CH_Pos (26U)
1875#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos)
1876#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk
1877#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos)
1878#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos)
1879#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos)
1880#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos)
1881#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos)
1883#define ADC_OFR1_OFFSET1_EN_Pos (31U)
1884#define ADC_OFR1_OFFSET1_EN_Msk (0x1UL << ADC_OFR1_OFFSET1_EN_Pos)
1885#define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk
1887/******************** Bit definition for ADC_OFR2 register ******************/
1888#define ADC_OFR2_OFFSET2_Pos (0U)
1889#define ADC_OFR2_OFFSET2_Msk (0xFFFUL << ADC_OFR2_OFFSET2_Pos)
1890#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk
1891#define ADC_OFR2_OFFSET2_0 (0x001UL << ADC_OFR2_OFFSET2_Pos)
1892#define ADC_OFR2_OFFSET2_1 (0x002UL << ADC_OFR2_OFFSET2_Pos)
1893#define ADC_OFR2_OFFSET2_2 (0x004UL << ADC_OFR2_OFFSET2_Pos)
1894#define ADC_OFR2_OFFSET2_3 (0x008UL << ADC_OFR2_OFFSET2_Pos)
1895#define ADC_OFR2_OFFSET2_4 (0x010UL << ADC_OFR2_OFFSET2_Pos)
1896#define ADC_OFR2_OFFSET2_5 (0x020UL << ADC_OFR2_OFFSET2_Pos)
1897#define ADC_OFR2_OFFSET2_6 (0x040UL << ADC_OFR2_OFFSET2_Pos)
1898#define ADC_OFR2_OFFSET2_7 (0x080UL << ADC_OFR2_OFFSET2_Pos)
1899#define ADC_OFR2_OFFSET2_8 (0x100UL << ADC_OFR2_OFFSET2_Pos)
1900#define ADC_OFR2_OFFSET2_9 (0x200UL << ADC_OFR2_OFFSET2_Pos)
1901#define ADC_OFR2_OFFSET2_10 (0x400UL << ADC_OFR2_OFFSET2_Pos)
1902#define ADC_OFR2_OFFSET2_11 (0x800UL << ADC_OFR2_OFFSET2_Pos)
1904#define ADC_OFR2_OFFSET2_CH_Pos (26U)
1905#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos)
1906#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk
1907#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos)
1908#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos)
1909#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos)
1910#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos)
1911#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos)
1913#define ADC_OFR2_OFFSET2_EN_Pos (31U)
1914#define ADC_OFR2_OFFSET2_EN_Msk (0x1UL << ADC_OFR2_OFFSET2_EN_Pos)
1915#define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk
1917/******************** Bit definition for ADC_OFR3 register ******************/
1918#define ADC_OFR3_OFFSET3_Pos (0U)
1919#define ADC_OFR3_OFFSET3_Msk (0xFFFUL << ADC_OFR3_OFFSET3_Pos)
1920#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk
1921#define ADC_OFR3_OFFSET3_0 (0x001UL << ADC_OFR3_OFFSET3_Pos)
1922#define ADC_OFR3_OFFSET3_1 (0x002UL << ADC_OFR3_OFFSET3_Pos)
1923#define ADC_OFR3_OFFSET3_2 (0x004UL << ADC_OFR3_OFFSET3_Pos)
1924#define ADC_OFR3_OFFSET3_3 (0x008UL << ADC_OFR3_OFFSET3_Pos)
1925#define ADC_OFR3_OFFSET3_4 (0x010UL << ADC_OFR3_OFFSET3_Pos)
1926#define ADC_OFR3_OFFSET3_5 (0x020UL << ADC_OFR3_OFFSET3_Pos)
1927#define ADC_OFR3_OFFSET3_6 (0x040UL << ADC_OFR3_OFFSET3_Pos)
1928#define ADC_OFR3_OFFSET3_7 (0x080UL << ADC_OFR3_OFFSET3_Pos)
1929#define ADC_OFR3_OFFSET3_8 (0x100UL << ADC_OFR3_OFFSET3_Pos)
1930#define ADC_OFR3_OFFSET3_9 (0x200UL << ADC_OFR3_OFFSET3_Pos)
1931#define ADC_OFR3_OFFSET3_10 (0x400UL << ADC_OFR3_OFFSET3_Pos)
1932#define ADC_OFR3_OFFSET3_11 (0x800UL << ADC_OFR3_OFFSET3_Pos)
1934#define ADC_OFR3_OFFSET3_CH_Pos (26U)
1935#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos)
1936#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk
1937#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos)
1938#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos)
1939#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos)
1940#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos)
1941#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos)
1943#define ADC_OFR3_OFFSET3_EN_Pos (31U)
1944#define ADC_OFR3_OFFSET3_EN_Msk (0x1UL << ADC_OFR3_OFFSET3_EN_Pos)
1945#define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk
1947/******************** Bit definition for ADC_OFR4 register ******************/
1948#define ADC_OFR4_OFFSET4_Pos (0U)
1949#define ADC_OFR4_OFFSET4_Msk (0xFFFUL << ADC_OFR4_OFFSET4_Pos)
1950#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk
1951#define ADC_OFR4_OFFSET4_0 (0x001UL << ADC_OFR4_OFFSET4_Pos)
1952#define ADC_OFR4_OFFSET4_1 (0x002UL << ADC_OFR4_OFFSET4_Pos)
1953#define ADC_OFR4_OFFSET4_2 (0x004UL << ADC_OFR4_OFFSET4_Pos)
1954#define ADC_OFR4_OFFSET4_3 (0x008UL << ADC_OFR4_OFFSET4_Pos)
1955#define ADC_OFR4_OFFSET4_4 (0x010UL << ADC_OFR4_OFFSET4_Pos)
1956#define ADC_OFR4_OFFSET4_5 (0x020UL << ADC_OFR4_OFFSET4_Pos)
1957#define ADC_OFR4_OFFSET4_6 (0x040UL << ADC_OFR4_OFFSET4_Pos)
1958#define ADC_OFR4_OFFSET4_7 (0x080UL << ADC_OFR4_OFFSET4_Pos)
1959#define ADC_OFR4_OFFSET4_8 (0x100UL << ADC_OFR4_OFFSET4_Pos)
1960#define ADC_OFR4_OFFSET4_9 (0x200UL << ADC_OFR4_OFFSET4_Pos)
1961#define ADC_OFR4_OFFSET4_10 (0x400UL << ADC_OFR4_OFFSET4_Pos)
1962#define ADC_OFR4_OFFSET4_11 (0x800UL << ADC_OFR4_OFFSET4_Pos)
1964#define ADC_OFR4_OFFSET4_CH_Pos (26U)
1965#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos)
1966#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk
1967#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos)
1968#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos)
1969#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos)
1970#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos)
1971#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos)
1973#define ADC_OFR4_OFFSET4_EN_Pos (31U)
1974#define ADC_OFR4_OFFSET4_EN_Msk (0x1UL << ADC_OFR4_OFFSET4_EN_Pos)
1975#define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk
1977/******************** Bit definition for ADC_JDR1 register ******************/
1978#define ADC_JDR1_JDATA_Pos (0U)
1979#define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos)
1980#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk
1981#define ADC_JDR1_JDATA_0 (0x0001UL << ADC_JDR1_JDATA_Pos)
1982#define ADC_JDR1_JDATA_1 (0x0002UL << ADC_JDR1_JDATA_Pos)
1983#define ADC_JDR1_JDATA_2 (0x0004UL << ADC_JDR1_JDATA_Pos)
1984#define ADC_JDR1_JDATA_3 (0x0008UL << ADC_JDR1_JDATA_Pos)
1985#define ADC_JDR1_JDATA_4 (0x0010UL << ADC_JDR1_JDATA_Pos)
1986#define ADC_JDR1_JDATA_5 (0x0020UL << ADC_JDR1_JDATA_Pos)
1987#define ADC_JDR1_JDATA_6 (0x0040UL << ADC_JDR1_JDATA_Pos)
1988#define ADC_JDR1_JDATA_7 (0x0080UL << ADC_JDR1_JDATA_Pos)
1989#define ADC_JDR1_JDATA_8 (0x0100UL << ADC_JDR1_JDATA_Pos)
1990#define ADC_JDR1_JDATA_9 (0x0200UL << ADC_JDR1_JDATA_Pos)
1991#define ADC_JDR1_JDATA_10 (0x0400UL << ADC_JDR1_JDATA_Pos)
1992#define ADC_JDR1_JDATA_11 (0x0800UL << ADC_JDR1_JDATA_Pos)
1993#define ADC_JDR1_JDATA_12 (0x1000UL << ADC_JDR1_JDATA_Pos)
1994#define ADC_JDR1_JDATA_13 (0x2000UL << ADC_JDR1_JDATA_Pos)
1995#define ADC_JDR1_JDATA_14 (0x4000UL << ADC_JDR1_JDATA_Pos)
1996#define ADC_JDR1_JDATA_15 (0x8000UL << ADC_JDR1_JDATA_Pos)
1998/******************** Bit definition for ADC_JDR2 register ******************/
1999#define ADC_JDR2_JDATA_Pos (0U)
2000#define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos)
2001#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk
2002#define ADC_JDR2_JDATA_0 (0x0001UL << ADC_JDR2_JDATA_Pos)
2003#define ADC_JDR2_JDATA_1 (0x0002UL << ADC_JDR2_JDATA_Pos)
2004#define ADC_JDR2_JDATA_2 (0x0004UL << ADC_JDR2_JDATA_Pos)
2005#define ADC_JDR2_JDATA_3 (0x0008UL << ADC_JDR2_JDATA_Pos)
2006#define ADC_JDR2_JDATA_4 (0x0010UL << ADC_JDR2_JDATA_Pos)
2007#define ADC_JDR2_JDATA_5 (0x0020UL << ADC_JDR2_JDATA_Pos)
2008#define ADC_JDR2_JDATA_6 (0x0040UL << ADC_JDR2_JDATA_Pos)
2009#define ADC_JDR2_JDATA_7 (0x0080UL << ADC_JDR2_JDATA_Pos)
2010#define ADC_JDR2_JDATA_8 (0x0100UL << ADC_JDR2_JDATA_Pos)
2011#define ADC_JDR2_JDATA_9 (0x0200UL << ADC_JDR2_JDATA_Pos)
2012#define ADC_JDR2_JDATA_10 (0x0400UL << ADC_JDR2_JDATA_Pos)
2013#define ADC_JDR2_JDATA_11 (0x0800UL << ADC_JDR2_JDATA_Pos)
2014#define ADC_JDR2_JDATA_12 (0x1000UL << ADC_JDR2_JDATA_Pos)
2015#define ADC_JDR2_JDATA_13 (0x2000UL << ADC_JDR2_JDATA_Pos)
2016#define ADC_JDR2_JDATA_14 (0x4000UL << ADC_JDR2_JDATA_Pos)
2017#define ADC_JDR2_JDATA_15 (0x8000UL << ADC_JDR2_JDATA_Pos)
2019/******************** Bit definition for ADC_JDR3 register ******************/
2020#define ADC_JDR3_JDATA_Pos (0U)
2021#define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos)
2022#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk
2023#define ADC_JDR3_JDATA_0 (0x0001UL << ADC_JDR3_JDATA_Pos)
2024#define ADC_JDR3_JDATA_1 (0x0002UL << ADC_JDR3_JDATA_Pos)
2025#define ADC_JDR3_JDATA_2 (0x0004UL << ADC_JDR3_JDATA_Pos)
2026#define ADC_JDR3_JDATA_3 (0x0008UL << ADC_JDR3_JDATA_Pos)
2027#define ADC_JDR3_JDATA_4 (0x0010UL << ADC_JDR3_JDATA_Pos)
2028#define ADC_JDR3_JDATA_5 (0x0020UL << ADC_JDR3_JDATA_Pos)
2029#define ADC_JDR3_JDATA_6 (0x0040UL << ADC_JDR3_JDATA_Pos)
2030#define ADC_JDR3_JDATA_7 (0x0080UL << ADC_JDR3_JDATA_Pos)
2031#define ADC_JDR3_JDATA_8 (0x0100UL << ADC_JDR3_JDATA_Pos)
2032#define ADC_JDR3_JDATA_9 (0x0200UL << ADC_JDR3_JDATA_Pos)
2033#define ADC_JDR3_JDATA_10 (0x0400UL << ADC_JDR3_JDATA_Pos)
2034#define ADC_JDR3_JDATA_11 (0x0800UL << ADC_JDR3_JDATA_Pos)
2035#define ADC_JDR3_JDATA_12 (0x1000UL << ADC_JDR3_JDATA_Pos)
2036#define ADC_JDR3_JDATA_13 (0x2000UL << ADC_JDR3_JDATA_Pos)
2037#define ADC_JDR3_JDATA_14 (0x4000UL << ADC_JDR3_JDATA_Pos)
2038#define ADC_JDR3_JDATA_15 (0x8000UL << ADC_JDR3_JDATA_Pos)
2040/******************** Bit definition for ADC_JDR4 register ******************/
2041#define ADC_JDR4_JDATA_Pos (0U)
2042#define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos)
2043#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk
2044#define ADC_JDR4_JDATA_0 (0x0001UL << ADC_JDR4_JDATA_Pos)
2045#define ADC_JDR4_JDATA_1 (0x0002UL << ADC_JDR4_JDATA_Pos)
2046#define ADC_JDR4_JDATA_2 (0x0004UL << ADC_JDR4_JDATA_Pos)
2047#define ADC_JDR4_JDATA_3 (0x0008UL << ADC_JDR4_JDATA_Pos)
2048#define ADC_JDR4_JDATA_4 (0x0010UL << ADC_JDR4_JDATA_Pos)
2049#define ADC_JDR4_JDATA_5 (0x0020UL << ADC_JDR4_JDATA_Pos)
2050#define ADC_JDR4_JDATA_6 (0x0040UL << ADC_JDR4_JDATA_Pos)
2051#define ADC_JDR4_JDATA_7 (0x0080UL << ADC_JDR4_JDATA_Pos)
2052#define ADC_JDR4_JDATA_8 (0x0100UL << ADC_JDR4_JDATA_Pos)
2053#define ADC_JDR4_JDATA_9 (0x0200UL << ADC_JDR4_JDATA_Pos)
2054#define ADC_JDR4_JDATA_10 (0x0400UL << ADC_JDR4_JDATA_Pos)
2055#define ADC_JDR4_JDATA_11 (0x0800UL << ADC_JDR4_JDATA_Pos)
2056#define ADC_JDR4_JDATA_12 (0x1000UL << ADC_JDR4_JDATA_Pos)
2057#define ADC_JDR4_JDATA_13 (0x2000UL << ADC_JDR4_JDATA_Pos)
2058#define ADC_JDR4_JDATA_14 (0x4000UL << ADC_JDR4_JDATA_Pos)
2059#define ADC_JDR4_JDATA_15 (0x8000UL << ADC_JDR4_JDATA_Pos)
2061/******************** Bit definition for ADC_AWD2CR register ****************/
2062#define ADC_AWD2CR_AWD2CH_Pos (0U)
2063#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos)
2064#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk
2065#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos)
2066#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos)
2067#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos)
2068#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos)
2069#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos)
2070#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos)
2071#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos)
2072#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos)
2073#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos)
2074#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos)
2075#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos)
2076#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos)
2077#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos)
2078#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos)
2079#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos)
2080#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos)
2081#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos)
2082#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos)
2083#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos)
2085/******************** Bit definition for ADC_AWD3CR register ****************/
2086#define ADC_AWD3CR_AWD3CH_Pos (0U)
2087#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos)
2088#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk
2089#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos)
2090#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos)
2091#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos)
2092#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos)
2093#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos)
2094#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos)
2095#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos)
2096#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos)
2097#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos)
2098#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos)
2099#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos)
2100#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos)
2101#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos)
2102#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos)
2103#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos)
2104#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos)
2105#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos)
2106#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos)
2107#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos)
2109/******************** Bit definition for ADC_DIFSEL register ****************/
2110#define ADC_DIFSEL_DIFSEL_Pos (0U)
2111#define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFUL << ADC_DIFSEL_DIFSEL_Pos)
2112#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk
2113#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos)
2114#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos)
2115#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos)
2116#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos)
2117#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos)
2118#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos)
2119#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos)
2120#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos)
2121#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos)
2122#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos)
2123#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos)
2124#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos)
2125#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos)
2126#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos)
2127#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos)
2128#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos)
2129#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos)
2130#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos)
2131#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos)
2133/******************** Bit definition for ADC_CALFACT register ***************/
2134#define ADC_CALFACT_CALFACT_S_Pos (0U)
2135#define ADC_CALFACT_CALFACT_S_Msk (0x7FUL << ADC_CALFACT_CALFACT_S_Pos)
2136#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk
2137#define ADC_CALFACT_CALFACT_S_0 (0x01UL << ADC_CALFACT_CALFACT_S_Pos)
2138#define ADC_CALFACT_CALFACT_S_1 (0x02UL << ADC_CALFACT_CALFACT_S_Pos)
2139#define ADC_CALFACT_CALFACT_S_2 (0x04UL << ADC_CALFACT_CALFACT_S_Pos)
2140#define ADC_CALFACT_CALFACT_S_3 (0x08UL << ADC_CALFACT_CALFACT_S_Pos)
2141#define ADC_CALFACT_CALFACT_S_4 (0x10UL << ADC_CALFACT_CALFACT_S_Pos)
2142#define ADC_CALFACT_CALFACT_S_5 (0x20UL << ADC_CALFACT_CALFACT_S_Pos)
2143#define ADC_CALFACT_CALFACT_S_6 (0x40UL << ADC_CALFACT_CALFACT_S_Pos)
2145#define ADC_CALFACT_CALFACT_D_Pos (16U)
2146#define ADC_CALFACT_CALFACT_D_Msk (0x7FUL << ADC_CALFACT_CALFACT_D_Pos)
2147#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk
2148#define ADC_CALFACT_CALFACT_D_0 (0x01UL << ADC_CALFACT_CALFACT_D_Pos)
2149#define ADC_CALFACT_CALFACT_D_1 (0x02UL << ADC_CALFACT_CALFACT_D_Pos)
2150#define ADC_CALFACT_CALFACT_D_2 (0x04UL << ADC_CALFACT_CALFACT_D_Pos)
2151#define ADC_CALFACT_CALFACT_D_3 (0x08UL << ADC_CALFACT_CALFACT_D_Pos)
2152#define ADC_CALFACT_CALFACT_D_4 (0x10UL << ADC_CALFACT_CALFACT_D_Pos)
2153#define ADC_CALFACT_CALFACT_D_5 (0x20UL << ADC_CALFACT_CALFACT_D_Pos)
2154#define ADC_CALFACT_CALFACT_D_6 (0x40UL << ADC_CALFACT_CALFACT_D_Pos)
2156/************************* ADC Common registers *****************************/
2157/******************** Bit definition for ADC_CCR register *******************/
2158#define ADC_CCR_CKMODE_Pos (16U)
2159#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos)
2160#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk
2161#define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos)
2162#define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos)
2164#define ADC_CCR_PRESC_Pos (18U)
2165#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos)
2166#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk
2167#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos)
2168#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos)
2169#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos)
2170#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos)
2172#define ADC_CCR_VREFEN_Pos (22U)
2173#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos)
2174#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk
2175#define ADC_CCR_TSEN_Pos (23U)
2176#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos)
2177#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk
2178#define ADC_CCR_VBATEN_Pos (24U)
2179#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos)
2180#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk
2182/******************************************************************************/
2183/* */
2184/* Controller Area Network */
2185/* */
2186/******************************************************************************/
2188/******************* Bit definition for CAN_MCR register ********************/
2189#define CAN_MCR_INRQ_Pos (0U)
2190#define CAN_MCR_INRQ_Msk (0x1UL << CAN_MCR_INRQ_Pos)
2191#define CAN_MCR_INRQ CAN_MCR_INRQ_Msk
2192#define CAN_MCR_SLEEP_Pos (1U)
2193#define CAN_MCR_SLEEP_Msk (0x1UL << CAN_MCR_SLEEP_Pos)
2194#define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk
2195#define CAN_MCR_TXFP_Pos (2U)
2196#define CAN_MCR_TXFP_Msk (0x1UL << CAN_MCR_TXFP_Pos)
2197#define CAN_MCR_TXFP CAN_MCR_TXFP_Msk
2198#define CAN_MCR_RFLM_Pos (3U)
2199#define CAN_MCR_RFLM_Msk (0x1UL << CAN_MCR_RFLM_Pos)
2200#define CAN_MCR_RFLM CAN_MCR_RFLM_Msk
2201#define CAN_MCR_NART_Pos (4U)
2202#define CAN_MCR_NART_Msk (0x1UL << CAN_MCR_NART_Pos)
2203#define CAN_MCR_NART CAN_MCR_NART_Msk
2204#define CAN_MCR_AWUM_Pos (5U)
2205#define CAN_MCR_AWUM_Msk (0x1UL << CAN_MCR_AWUM_Pos)
2206#define CAN_MCR_AWUM CAN_MCR_AWUM_Msk
2207#define CAN_MCR_ABOM_Pos (6U)
2208#define CAN_MCR_ABOM_Msk (0x1UL << CAN_MCR_ABOM_Pos)
2209#define CAN_MCR_ABOM CAN_MCR_ABOM_Msk
2210#define CAN_MCR_TTCM_Pos (7U)
2211#define CAN_MCR_TTCM_Msk (0x1UL << CAN_MCR_TTCM_Pos)
2212#define CAN_MCR_TTCM CAN_MCR_TTCM_Msk
2213#define CAN_MCR_RESET_Pos (15U)
2214#define CAN_MCR_RESET_Msk (0x1UL << CAN_MCR_RESET_Pos)
2215#define CAN_MCR_RESET CAN_MCR_RESET_Msk
2217/******************* Bit definition for CAN_MSR register ********************/
2218#define CAN_MSR_INAK_Pos (0U)
2219#define CAN_MSR_INAK_Msk (0x1UL << CAN_MSR_INAK_Pos)
2220#define CAN_MSR_INAK CAN_MSR_INAK_Msk
2221#define CAN_MSR_SLAK_Pos (1U)
2222#define CAN_MSR_SLAK_Msk (0x1UL << CAN_MSR_SLAK_Pos)
2223#define CAN_MSR_SLAK CAN_MSR_SLAK_Msk
2224#define CAN_MSR_ERRI_Pos (2U)
2225#define CAN_MSR_ERRI_Msk (0x1UL << CAN_MSR_ERRI_Pos)
2226#define CAN_MSR_ERRI CAN_MSR_ERRI_Msk
2227#define CAN_MSR_WKUI_Pos (3U)
2228#define CAN_MSR_WKUI_Msk (0x1UL << CAN_MSR_WKUI_Pos)
2229#define CAN_MSR_WKUI CAN_MSR_WKUI_Msk
2230#define CAN_MSR_SLAKI_Pos (4U)
2231#define CAN_MSR_SLAKI_Msk (0x1UL << CAN_MSR_SLAKI_Pos)
2232#define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk
2233#define CAN_MSR_TXM_Pos (8U)
2234#define CAN_MSR_TXM_Msk (0x1UL << CAN_MSR_TXM_Pos)
2235#define CAN_MSR_TXM CAN_MSR_TXM_Msk
2236#define CAN_MSR_RXM_Pos (9U)
2237#define CAN_MSR_RXM_Msk (0x1UL << CAN_MSR_RXM_Pos)
2238#define CAN_MSR_RXM CAN_MSR_RXM_Msk
2239#define CAN_MSR_SAMP_Pos (10U)
2240#define CAN_MSR_SAMP_Msk (0x1UL << CAN_MSR_SAMP_Pos)
2241#define CAN_MSR_SAMP CAN_MSR_SAMP_Msk
2242#define CAN_MSR_RX_Pos (11U)
2243#define CAN_MSR_RX_Msk (0x1UL << CAN_MSR_RX_Pos)
2244#define CAN_MSR_RX CAN_MSR_RX_Msk
2246/******************* Bit definition for CAN_TSR register ********************/
2247#define CAN_TSR_RQCP0_Pos (0U)
2248#define CAN_TSR_RQCP0_Msk (0x1UL << CAN_TSR_RQCP0_Pos)
2249#define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk
2250#define CAN_TSR_TXOK0_Pos (1U)
2251#define CAN_TSR_TXOK0_Msk (0x1UL << CAN_TSR_TXOK0_Pos)
2252#define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk
2253#define CAN_TSR_ALST0_Pos (2U)
2254#define CAN_TSR_ALST0_Msk (0x1UL << CAN_TSR_ALST0_Pos)
2255#define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk
2256#define CAN_TSR_TERR0_Pos (3U)
2257#define CAN_TSR_TERR0_Msk (0x1UL << CAN_TSR_TERR0_Pos)
2258#define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk
2259#define CAN_TSR_ABRQ0_Pos (7U)
2260#define CAN_TSR_ABRQ0_Msk (0x1UL << CAN_TSR_ABRQ0_Pos)
2261#define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk
2262#define CAN_TSR_RQCP1_Pos (8U)
2263#define CAN_TSR_RQCP1_Msk (0x1UL << CAN_TSR_RQCP1_Pos)
2264#define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk
2265#define CAN_TSR_TXOK1_Pos (9U)
2266#define CAN_TSR_TXOK1_Msk (0x1UL << CAN_TSR_TXOK1_Pos)
2267#define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk
2268#define CAN_TSR_ALST1_Pos (10U)
2269#define CAN_TSR_ALST1_Msk (0x1UL << CAN_TSR_ALST1_Pos)
2270#define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk
2271#define CAN_TSR_TERR1_Pos (11U)
2272#define CAN_TSR_TERR1_Msk (0x1UL << CAN_TSR_TERR1_Pos)
2273#define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk
2274#define CAN_TSR_ABRQ1_Pos (15U)
2275#define CAN_TSR_ABRQ1_Msk (0x1UL << CAN_TSR_ABRQ1_Pos)
2276#define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk
2277#define CAN_TSR_RQCP2_Pos (16U)
2278#define CAN_TSR_RQCP2_Msk (0x1UL << CAN_TSR_RQCP2_Pos)
2279#define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk
2280#define CAN_TSR_TXOK2_Pos (17U)
2281#define CAN_TSR_TXOK2_Msk (0x1UL << CAN_TSR_TXOK2_Pos)
2282#define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk
2283#define CAN_TSR_ALST2_Pos (18U)
2284#define CAN_TSR_ALST2_Msk (0x1UL << CAN_TSR_ALST2_Pos)
2285#define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk
2286#define CAN_TSR_TERR2_Pos (19U)
2287#define CAN_TSR_TERR2_Msk (0x1UL << CAN_TSR_TERR2_Pos)
2288#define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk
2289#define CAN_TSR_ABRQ2_Pos (23U)
2290#define CAN_TSR_ABRQ2_Msk (0x1UL << CAN_TSR_ABRQ2_Pos)
2291#define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk
2292#define CAN_TSR_CODE_Pos (24U)
2293#define CAN_TSR_CODE_Msk (0x3UL << CAN_TSR_CODE_Pos)
2294#define CAN_TSR_CODE CAN_TSR_CODE_Msk
2296#define CAN_TSR_TME_Pos (26U)
2297#define CAN_TSR_TME_Msk (0x7UL << CAN_TSR_TME_Pos)
2298#define CAN_TSR_TME CAN_TSR_TME_Msk
2299#define CAN_TSR_TME0_Pos (26U)
2300#define CAN_TSR_TME0_Msk (0x1UL << CAN_TSR_TME0_Pos)
2301#define CAN_TSR_TME0 CAN_TSR_TME0_Msk
2302#define CAN_TSR_TME1_Pos (27U)
2303#define CAN_TSR_TME1_Msk (0x1UL << CAN_TSR_TME1_Pos)
2304#define CAN_TSR_TME1 CAN_TSR_TME1_Msk
2305#define CAN_TSR_TME2_Pos (28U)
2306#define CAN_TSR_TME2_Msk (0x1UL << CAN_TSR_TME2_Pos)
2307#define CAN_TSR_TME2 CAN_TSR_TME2_Msk
2309#define CAN_TSR_LOW_Pos (29U)
2310#define CAN_TSR_LOW_Msk (0x7UL << CAN_TSR_LOW_Pos)
2311#define CAN_TSR_LOW CAN_TSR_LOW_Msk
2312#define CAN_TSR_LOW0_Pos (29U)
2313#define CAN_TSR_LOW0_Msk (0x1UL << CAN_TSR_LOW0_Pos)
2314#define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk
2315#define CAN_TSR_LOW1_Pos (30U)
2316#define CAN_TSR_LOW1_Msk (0x1UL << CAN_TSR_LOW1_Pos)
2317#define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk
2318#define CAN_TSR_LOW2_Pos (31U)
2319#define CAN_TSR_LOW2_Msk (0x1UL << CAN_TSR_LOW2_Pos)
2320#define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk
2322/******************* Bit definition for CAN_RF0R register *******************/
2323#define CAN_RF0R_FMP0_Pos (0U)
2324#define CAN_RF0R_FMP0_Msk (0x3UL << CAN_RF0R_FMP0_Pos)
2325#define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk
2326#define CAN_RF0R_FULL0_Pos (3U)
2327#define CAN_RF0R_FULL0_Msk (0x1UL << CAN_RF0R_FULL0_Pos)
2328#define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk
2329#define CAN_RF0R_FOVR0_Pos (4U)
2330#define CAN_RF0R_FOVR0_Msk (0x1UL << CAN_RF0R_FOVR0_Pos)
2331#define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk
2332#define CAN_RF0R_RFOM0_Pos (5U)
2333#define CAN_RF0R_RFOM0_Msk (0x1UL << CAN_RF0R_RFOM0_Pos)
2334#define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk
2336/******************* Bit definition for CAN_RF1R register *******************/
2337#define CAN_RF1R_FMP1_Pos (0U)
2338#define CAN_RF1R_FMP1_Msk (0x3UL << CAN_RF1R_FMP1_Pos)
2339#define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk
2340#define CAN_RF1R_FULL1_Pos (3U)
2341#define CAN_RF1R_FULL1_Msk (0x1UL << CAN_RF1R_FULL1_Pos)
2342#define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk
2343#define CAN_RF1R_FOVR1_Pos (4U)
2344#define CAN_RF1R_FOVR1_Msk (0x1UL << CAN_RF1R_FOVR1_Pos)
2345#define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk
2346#define CAN_RF1R_RFOM1_Pos (5U)
2347#define CAN_RF1R_RFOM1_Msk (0x1UL << CAN_RF1R_RFOM1_Pos)
2348#define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk
2350/******************** Bit definition for CAN_IER register *******************/
2351#define CAN_IER_TMEIE_Pos (0U)
2352#define CAN_IER_TMEIE_Msk (0x1UL << CAN_IER_TMEIE_Pos)
2353#define CAN_IER_TMEIE CAN_IER_TMEIE_Msk
2354#define CAN_IER_FMPIE0_Pos (1U)
2355#define CAN_IER_FMPIE0_Msk (0x1UL << CAN_IER_FMPIE0_Pos)
2356#define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk
2357#define CAN_IER_FFIE0_Pos (2U)
2358#define CAN_IER_FFIE0_Msk (0x1UL << CAN_IER_FFIE0_Pos)
2359#define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk
2360#define CAN_IER_FOVIE0_Pos (3U)
2361#define CAN_IER_FOVIE0_Msk (0x1UL << CAN_IER_FOVIE0_Pos)
2362#define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk
2363#define CAN_IER_FMPIE1_Pos (4U)
2364#define CAN_IER_FMPIE1_Msk (0x1UL << CAN_IER_FMPIE1_Pos)
2365#define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk
2366#define CAN_IER_FFIE1_Pos (5U)
2367#define CAN_IER_FFIE1_Msk (0x1UL << CAN_IER_FFIE1_Pos)
2368#define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk
2369#define CAN_IER_FOVIE1_Pos (6U)
2370#define CAN_IER_FOVIE1_Msk (0x1UL << CAN_IER_FOVIE1_Pos)
2371#define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk
2372#define CAN_IER_EWGIE_Pos (8U)
2373#define CAN_IER_EWGIE_Msk (0x1UL << CAN_IER_EWGIE_Pos)
2374#define CAN_IER_EWGIE CAN_IER_EWGIE_Msk
2375#define CAN_IER_EPVIE_Pos (9U)
2376#define CAN_IER_EPVIE_Msk (0x1UL << CAN_IER_EPVIE_Pos)
2377#define CAN_IER_EPVIE CAN_IER_EPVIE_Msk
2378#define CAN_IER_BOFIE_Pos (10U)
2379#define CAN_IER_BOFIE_Msk (0x1UL << CAN_IER_BOFIE_Pos)
2380#define CAN_IER_BOFIE CAN_IER_BOFIE_Msk
2381#define CAN_IER_LECIE_Pos (11U)
2382#define CAN_IER_LECIE_Msk (0x1UL << CAN_IER_LECIE_Pos)
2383#define CAN_IER_LECIE CAN_IER_LECIE_Msk
2384#define CAN_IER_ERRIE_Pos (15U)
2385#define CAN_IER_ERRIE_Msk (0x1UL << CAN_IER_ERRIE_Pos)
2386#define CAN_IER_ERRIE CAN_IER_ERRIE_Msk
2387#define CAN_IER_WKUIE_Pos (16U)
2388#define CAN_IER_WKUIE_Msk (0x1UL << CAN_IER_WKUIE_Pos)
2389#define CAN_IER_WKUIE CAN_IER_WKUIE_Msk
2390#define CAN_IER_SLKIE_Pos (17U)
2391#define CAN_IER_SLKIE_Msk (0x1UL << CAN_IER_SLKIE_Pos)
2392#define CAN_IER_SLKIE CAN_IER_SLKIE_Msk
2394/******************** Bit definition for CAN_ESR register *******************/
2395#define CAN_ESR_EWGF_Pos (0U)
2396#define CAN_ESR_EWGF_Msk (0x1UL << CAN_ESR_EWGF_Pos)
2397#define CAN_ESR_EWGF CAN_ESR_EWGF_Msk
2398#define CAN_ESR_EPVF_Pos (1U)
2399#define CAN_ESR_EPVF_Msk (0x1UL << CAN_ESR_EPVF_Pos)
2400#define CAN_ESR_EPVF CAN_ESR_EPVF_Msk
2401#define CAN_ESR_BOFF_Pos (2U)
2402#define CAN_ESR_BOFF_Msk (0x1UL << CAN_ESR_BOFF_Pos)
2403#define CAN_ESR_BOFF CAN_ESR_BOFF_Msk
2405#define CAN_ESR_LEC_Pos (4U)
2406#define CAN_ESR_LEC_Msk (0x7UL << CAN_ESR_LEC_Pos)
2407#define CAN_ESR_LEC CAN_ESR_LEC_Msk
2408#define CAN_ESR_LEC_0 (0x1UL << CAN_ESR_LEC_Pos)
2409#define CAN_ESR_LEC_1 (0x2UL << CAN_ESR_LEC_Pos)
2410#define CAN_ESR_LEC_2 (0x4UL << CAN_ESR_LEC_Pos)
2412#define CAN_ESR_TEC_Pos (16U)
2413#define CAN_ESR_TEC_Msk (0xFFUL << CAN_ESR_TEC_Pos)
2414#define CAN_ESR_TEC CAN_ESR_TEC_Msk
2415#define CAN_ESR_REC_Pos (24U)
2416#define CAN_ESR_REC_Msk (0xFFUL << CAN_ESR_REC_Pos)
2417#define CAN_ESR_REC CAN_ESR_REC_Msk
2419/******************* Bit definition for CAN_BTR register ********************/
2420#define CAN_BTR_BRP_Pos (0U)
2421#define CAN_BTR_BRP_Msk (0x3FFUL << CAN_BTR_BRP_Pos)
2422#define CAN_BTR_BRP CAN_BTR_BRP_Msk
2423#define CAN_BTR_TS1_Pos (16U)
2424#define CAN_BTR_TS1_Msk (0xFUL << CAN_BTR_TS1_Pos)
2425#define CAN_BTR_TS1 CAN_BTR_TS1_Msk
2426#define CAN_BTR_TS1_0 (0x1UL << CAN_BTR_TS1_Pos)
2427#define CAN_BTR_TS1_1 (0x2UL << CAN_BTR_TS1_Pos)
2428#define CAN_BTR_TS1_2 (0x4UL << CAN_BTR_TS1_Pos)
2429#define CAN_BTR_TS1_3 (0x8UL << CAN_BTR_TS1_Pos)
2430#define CAN_BTR_TS2_Pos (20U)
2431#define CAN_BTR_TS2_Msk (0x7UL << CAN_BTR_TS2_Pos)
2432#define CAN_BTR_TS2 CAN_BTR_TS2_Msk
2433#define CAN_BTR_TS2_0 (0x1UL << CAN_BTR_TS2_Pos)
2434#define CAN_BTR_TS2_1 (0x2UL << CAN_BTR_TS2_Pos)
2435#define CAN_BTR_TS2_2 (0x4UL << CAN_BTR_TS2_Pos)
2436#define CAN_BTR_SJW_Pos (24U)
2437#define CAN_BTR_SJW_Msk (0x3UL << CAN_BTR_SJW_Pos)
2438#define CAN_BTR_SJW CAN_BTR_SJW_Msk
2439#define CAN_BTR_SJW_0 (0x1UL << CAN_BTR_SJW_Pos)
2440#define CAN_BTR_SJW_1 (0x2UL << CAN_BTR_SJW_Pos)
2441#define CAN_BTR_LBKM_Pos (30U)
2442#define CAN_BTR_LBKM_Msk (0x1UL << CAN_BTR_LBKM_Pos)
2443#define CAN_BTR_LBKM CAN_BTR_LBKM_Msk
2444#define CAN_BTR_SILM_Pos (31U)
2445#define CAN_BTR_SILM_Msk (0x1UL << CAN_BTR_SILM_Pos)
2446#define CAN_BTR_SILM CAN_BTR_SILM_Msk
2449/****************** Bit definition for CAN_TI0R register ********************/
2450#define CAN_TI0R_TXRQ_Pos (0U)
2451#define CAN_TI0R_TXRQ_Msk (0x1UL << CAN_TI0R_TXRQ_Pos)
2452#define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk
2453#define CAN_TI0R_RTR_Pos (1U)
2454#define CAN_TI0R_RTR_Msk (0x1UL << CAN_TI0R_RTR_Pos)
2455#define CAN_TI0R_RTR CAN_TI0R_RTR_Msk
2456#define CAN_TI0R_IDE_Pos (2U)
2457#define CAN_TI0R_IDE_Msk (0x1UL << CAN_TI0R_IDE_Pos)
2458#define CAN_TI0R_IDE CAN_TI0R_IDE_Msk
2459#define CAN_TI0R_EXID_Pos (3U)
2460#define CAN_TI0R_EXID_Msk (0x3FFFFUL << CAN_TI0R_EXID_Pos)
2461#define CAN_TI0R_EXID CAN_TI0R_EXID_Msk
2462#define CAN_TI0R_STID_Pos (21U)
2463#define CAN_TI0R_STID_Msk (0x7FFUL << CAN_TI0R_STID_Pos)
2464#define CAN_TI0R_STID CAN_TI0R_STID_Msk
2466/****************** Bit definition for CAN_TDT0R register *******************/
2467#define CAN_TDT0R_DLC_Pos (0U)
2468#define CAN_TDT0R_DLC_Msk (0xFUL << CAN_TDT0R_DLC_Pos)
2469#define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk
2470#define CAN_TDT0R_TGT_Pos (8U)
2471#define CAN_TDT0R_TGT_Msk (0x1UL << CAN_TDT0R_TGT_Pos)
2472#define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk
2473#define CAN_TDT0R_TIME_Pos (16U)
2474#define CAN_TDT0R_TIME_Msk (0xFFFFUL << CAN_TDT0R_TIME_Pos)
2475#define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk
2477/****************** Bit definition for CAN_TDL0R register *******************/
2478#define CAN_TDL0R_DATA0_Pos (0U)
2479#define CAN_TDL0R_DATA0_Msk (0xFFUL << CAN_TDL0R_DATA0_Pos)
2480#define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk
2481#define CAN_TDL0R_DATA1_Pos (8U)
2482#define CAN_TDL0R_DATA1_Msk (0xFFUL << CAN_TDL0R_DATA1_Pos)
2483#define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk
2484#define CAN_TDL0R_DATA2_Pos (16U)
2485#define CAN_TDL0R_DATA2_Msk (0xFFUL << CAN_TDL0R_DATA2_Pos)
2486#define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk
2487#define CAN_TDL0R_DATA3_Pos (24U)
2488#define CAN_TDL0R_DATA3_Msk (0xFFUL << CAN_TDL0R_DATA3_Pos)
2489#define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk
2491/****************** Bit definition for CAN_TDH0R register *******************/
2492#define CAN_TDH0R_DATA4_Pos (0U)
2493#define CAN_TDH0R_DATA4_Msk (0xFFUL << CAN_TDH0R_DATA4_Pos)
2494#define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk
2495#define CAN_TDH0R_DATA5_Pos (8U)
2496#define CAN_TDH0R_DATA5_Msk (0xFFUL << CAN_TDH0R_DATA5_Pos)
2497#define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk
2498#define CAN_TDH0R_DATA6_Pos (16U)
2499#define CAN_TDH0R_DATA6_Msk (0xFFUL << CAN_TDH0R_DATA6_Pos)
2500#define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk
2501#define CAN_TDH0R_DATA7_Pos (24U)
2502#define CAN_TDH0R_DATA7_Msk (0xFFUL << CAN_TDH0R_DATA7_Pos)
2503#define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk
2505/******************* Bit definition for CAN_TI1R register *******************/
2506#define CAN_TI1R_TXRQ_Pos (0U)
2507#define CAN_TI1R_TXRQ_Msk (0x1UL << CAN_TI1R_TXRQ_Pos)
2508#define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk
2509#define CAN_TI1R_RTR_Pos (1U)
2510#define CAN_TI1R_RTR_Msk (0x1UL << CAN_TI1R_RTR_Pos)
2511#define CAN_TI1R_RTR CAN_TI1R_RTR_Msk
2512#define CAN_TI1R_IDE_Pos (2U)
2513#define CAN_TI1R_IDE_Msk (0x1UL << CAN_TI1R_IDE_Pos)
2514#define CAN_TI1R_IDE CAN_TI1R_IDE_Msk
2515#define CAN_TI1R_EXID_Pos (3U)
2516#define CAN_TI1R_EXID_Msk (0x3FFFFUL << CAN_TI1R_EXID_Pos)
2517#define CAN_TI1R_EXID CAN_TI1R_EXID_Msk
2518#define CAN_TI1R_STID_Pos (21U)
2519#define CAN_TI1R_STID_Msk (0x7FFUL << CAN_TI1R_STID_Pos)
2520#define CAN_TI1R_STID CAN_TI1R_STID_Msk
2522/******************* Bit definition for CAN_TDT1R register ******************/
2523#define CAN_TDT1R_DLC_Pos (0U)
2524#define CAN_TDT1R_DLC_Msk (0xFUL << CAN_TDT1R_DLC_Pos)
2525#define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk
2526#define CAN_TDT1R_TGT_Pos (8U)
2527#define CAN_TDT1R_TGT_Msk (0x1UL << CAN_TDT1R_TGT_Pos)
2528#define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk
2529#define CAN_TDT1R_TIME_Pos (16U)
2530#define CAN_TDT1R_TIME_Msk (0xFFFFUL << CAN_TDT1R_TIME_Pos)
2531#define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk
2533/******************* Bit definition for CAN_TDL1R register ******************/
2534#define CAN_TDL1R_DATA0_Pos (0U)
2535#define CAN_TDL1R_DATA0_Msk (0xFFUL << CAN_TDL1R_DATA0_Pos)
2536#define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk
2537#define CAN_TDL1R_DATA1_Pos (8U)
2538#define CAN_TDL1R_DATA1_Msk (0xFFUL << CAN_TDL1R_DATA1_Pos)
2539#define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk
2540#define CAN_TDL1R_DATA2_Pos (16U)
2541#define CAN_TDL1R_DATA2_Msk (0xFFUL << CAN_TDL1R_DATA2_Pos)
2542#define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk
2543#define CAN_TDL1R_DATA3_Pos (24U)
2544#define CAN_TDL1R_DATA3_Msk (0xFFUL << CAN_TDL1R_DATA3_Pos)
2545#define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk
2547/******************* Bit definition for CAN_TDH1R register ******************/
2548#define CAN_TDH1R_DATA4_Pos (0U)
2549#define CAN_TDH1R_DATA4_Msk (0xFFUL << CAN_TDH1R_DATA4_Pos)
2550#define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk
2551#define CAN_TDH1R_DATA5_Pos (8U)
2552#define CAN_TDH1R_DATA5_Msk (0xFFUL << CAN_TDH1R_DATA5_Pos)
2553#define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk
2554#define CAN_TDH1R_DATA6_Pos (16U)
2555#define CAN_TDH1R_DATA6_Msk (0xFFUL << CAN_TDH1R_DATA6_Pos)
2556#define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk
2557#define CAN_TDH1R_DATA7_Pos (24U)
2558#define CAN_TDH1R_DATA7_Msk (0xFFUL << CAN_TDH1R_DATA7_Pos)
2559#define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk
2561/******************* Bit definition for CAN_TI2R register *******************/
2562#define CAN_TI2R_TXRQ_Pos (0U)
2563#define CAN_TI2R_TXRQ_Msk (0x1UL << CAN_TI2R_TXRQ_Pos)
2564#define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk
2565#define CAN_TI2R_RTR_Pos (1U)
2566#define CAN_TI2R_RTR_Msk (0x1UL << CAN_TI2R_RTR_Pos)
2567#define CAN_TI2R_RTR CAN_TI2R_RTR_Msk
2568#define CAN_TI2R_IDE_Pos (2U)
2569#define CAN_TI2R_IDE_Msk (0x1UL << CAN_TI2R_IDE_Pos)
2570#define CAN_TI2R_IDE CAN_TI2R_IDE_Msk
2571#define CAN_TI2R_EXID_Pos (3U)
2572#define CAN_TI2R_EXID_Msk (0x3FFFFUL << CAN_TI2R_EXID_Pos)
2573#define CAN_TI2R_EXID CAN_TI2R_EXID_Msk
2574#define CAN_TI2R_STID_Pos (21U)
2575#define CAN_TI2R_STID_Msk (0x7FFUL << CAN_TI2R_STID_Pos)
2576#define CAN_TI2R_STID CAN_TI2R_STID_Msk
2578/******************* Bit definition for CAN_TDT2R register ******************/
2579#define CAN_TDT2R_DLC_Pos (0U)
2580#define CAN_TDT2R_DLC_Msk (0xFUL << CAN_TDT2R_DLC_Pos)
2581#define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk
2582#define CAN_TDT2R_TGT_Pos (8U)
2583#define CAN_TDT2R_TGT_Msk (0x1UL << CAN_TDT2R_TGT_Pos)
2584#define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk
2585#define CAN_TDT2R_TIME_Pos (16U)
2586#define CAN_TDT2R_TIME_Msk (0xFFFFUL << CAN_TDT2R_TIME_Pos)
2587#define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk
2589/******************* Bit definition for CAN_TDL2R register ******************/
2590#define CAN_TDL2R_DATA0_Pos (0U)
2591#define CAN_TDL2R_DATA0_Msk (0xFFUL << CAN_TDL2R_DATA0_Pos)
2592#define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk
2593#define CAN_TDL2R_DATA1_Pos (8U)
2594#define CAN_TDL2R_DATA1_Msk (0xFFUL << CAN_TDL2R_DATA1_Pos)
2595#define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk
2596#define CAN_TDL2R_DATA2_Pos (16U)
2597#define CAN_TDL2R_DATA2_Msk (0xFFUL << CAN_TDL2R_DATA2_Pos)
2598#define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk
2599#define CAN_TDL2R_DATA3_Pos (24U)
2600#define CAN_TDL2R_DATA3_Msk (0xFFUL << CAN_TDL2R_DATA3_Pos)
2601#define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk
2603/******************* Bit definition for CAN_TDH2R register ******************/
2604#define CAN_TDH2R_DATA4_Pos (0U)
2605#define CAN_TDH2R_DATA4_Msk (0xFFUL << CAN_TDH2R_DATA4_Pos)
2606#define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk
2607#define CAN_TDH2R_DATA5_Pos (8U)
2608#define CAN_TDH2R_DATA5_Msk (0xFFUL << CAN_TDH2R_DATA5_Pos)
2609#define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk
2610#define CAN_TDH2R_DATA6_Pos (16U)
2611#define CAN_TDH2R_DATA6_Msk (0xFFUL << CAN_TDH2R_DATA6_Pos)
2612#define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk
2613#define CAN_TDH2R_DATA7_Pos (24U)
2614#define CAN_TDH2R_DATA7_Msk (0xFFUL << CAN_TDH2R_DATA7_Pos)
2615#define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk
2617/******************* Bit definition for CAN_RI0R register *******************/
2618#define CAN_RI0R_RTR_Pos (1U)
2619#define CAN_RI0R_RTR_Msk (0x1UL << CAN_RI0R_RTR_Pos)
2620#define CAN_RI0R_RTR CAN_RI0R_RTR_Msk
2621#define CAN_RI0R_IDE_Pos (2U)
2622#define CAN_RI0R_IDE_Msk (0x1UL << CAN_RI0R_IDE_Pos)
2623#define CAN_RI0R_IDE CAN_RI0R_IDE_Msk
2624#define CAN_RI0R_EXID_Pos (3U)
2625#define CAN_RI0R_EXID_Msk (0x3FFFFUL << CAN_RI0R_EXID_Pos)
2626#define CAN_RI0R_EXID CAN_RI0R_EXID_Msk
2627#define CAN_RI0R_STID_Pos (21U)
2628#define CAN_RI0R_STID_Msk (0x7FFUL << CAN_RI0R_STID_Pos)
2629#define CAN_RI0R_STID CAN_RI0R_STID_Msk
2631/******************* Bit definition for CAN_RDT0R register ******************/
2632#define CAN_RDT0R_DLC_Pos (0U)
2633#define CAN_RDT0R_DLC_Msk (0xFUL << CAN_RDT0R_DLC_Pos)
2634#define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk
2635#define CAN_RDT0R_FMI_Pos (8U)
2636#define CAN_RDT0R_FMI_Msk (0xFFUL << CAN_RDT0R_FMI_Pos)
2637#define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk
2638#define CAN_RDT0R_TIME_Pos (16U)
2639#define CAN_RDT0R_TIME_Msk (0xFFFFUL << CAN_RDT0R_TIME_Pos)
2640#define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk
2642/******************* Bit definition for CAN_RDL0R register ******************/
2643#define CAN_RDL0R_DATA0_Pos (0U)
2644#define CAN_RDL0R_DATA0_Msk (0xFFUL << CAN_RDL0R_DATA0_Pos)
2645#define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk
2646#define CAN_RDL0R_DATA1_Pos (8U)
2647#define CAN_RDL0R_DATA1_Msk (0xFFUL << CAN_RDL0R_DATA1_Pos)
2648#define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk
2649#define CAN_RDL0R_DATA2_Pos (16U)
2650#define CAN_RDL0R_DATA2_Msk (0xFFUL << CAN_RDL0R_DATA2_Pos)
2651#define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk
2652#define CAN_RDL0R_DATA3_Pos (24U)
2653#define CAN_RDL0R_DATA3_Msk (0xFFUL << CAN_RDL0R_DATA3_Pos)
2654#define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk
2656/******************* Bit definition for CAN_RDH0R register ******************/
2657#define CAN_RDH0R_DATA4_Pos (0U)
2658#define CAN_RDH0R_DATA4_Msk (0xFFUL << CAN_RDH0R_DATA4_Pos)
2659#define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk
2660#define CAN_RDH0R_DATA5_Pos (8U)
2661#define CAN_RDH0R_DATA5_Msk (0xFFUL << CAN_RDH0R_DATA5_Pos)
2662#define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk
2663#define CAN_RDH0R_DATA6_Pos (16U)
2664#define CAN_RDH0R_DATA6_Msk (0xFFUL << CAN_RDH0R_DATA6_Pos)
2665#define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk
2666#define CAN_RDH0R_DATA7_Pos (24U)
2667#define CAN_RDH0R_DATA7_Msk (0xFFUL << CAN_RDH0R_DATA7_Pos)
2668#define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk
2670/******************* Bit definition for CAN_RI1R register *******************/
2671#define CAN_RI1R_RTR_Pos (1U)
2672#define CAN_RI1R_RTR_Msk (0x1UL << CAN_RI1R_RTR_Pos)
2673#define CAN_RI1R_RTR CAN_RI1R_RTR_Msk
2674#define CAN_RI1R_IDE_Pos (2U)
2675#define CAN_RI1R_IDE_Msk (0x1UL << CAN_RI1R_IDE_Pos)
2676#define CAN_RI1R_IDE CAN_RI1R_IDE_Msk
2677#define CAN_RI1R_EXID_Pos (3U)
2678#define CAN_RI1R_EXID_Msk (0x3FFFFUL << CAN_RI1R_EXID_Pos)
2679#define CAN_RI1R_EXID CAN_RI1R_EXID_Msk
2680#define CAN_RI1R_STID_Pos (21U)
2681#define CAN_RI1R_STID_Msk (0x7FFUL << CAN_RI1R_STID_Pos)
2682#define CAN_RI1R_STID CAN_RI1R_STID_Msk
2684/******************* Bit definition for CAN_RDT1R register ******************/
2685#define CAN_RDT1R_DLC_Pos (0U)
2686#define CAN_RDT1R_DLC_Msk (0xFUL << CAN_RDT1R_DLC_Pos)
2687#define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk
2688#define CAN_RDT1R_FMI_Pos (8U)
2689#define CAN_RDT1R_FMI_Msk (0xFFUL << CAN_RDT1R_FMI_Pos)
2690#define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk
2691#define CAN_RDT1R_TIME_Pos (16U)
2692#define CAN_RDT1R_TIME_Msk (0xFFFFUL << CAN_RDT1R_TIME_Pos)
2693#define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk
2695/******************* Bit definition for CAN_RDL1R register ******************/
2696#define CAN_RDL1R_DATA0_Pos (0U)
2697#define CAN_RDL1R_DATA0_Msk (0xFFUL << CAN_RDL1R_DATA0_Pos)
2698#define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk
2699#define CAN_RDL1R_DATA1_Pos (8U)
2700#define CAN_RDL1R_DATA1_Msk (0xFFUL << CAN_RDL1R_DATA1_Pos)
2701#define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk
2702#define CAN_RDL1R_DATA2_Pos (16U)
2703#define CAN_RDL1R_DATA2_Msk (0xFFUL << CAN_RDL1R_DATA2_Pos)
2704#define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk
2705#define CAN_RDL1R_DATA3_Pos (24U)
2706#define CAN_RDL1R_DATA3_Msk (0xFFUL << CAN_RDL1R_DATA3_Pos)
2707#define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk
2709/******************* Bit definition for CAN_RDH1R register ******************/
2710#define CAN_RDH1R_DATA4_Pos (0U)
2711#define CAN_RDH1R_DATA4_Msk (0xFFUL << CAN_RDH1R_DATA4_Pos)
2712#define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk
2713#define CAN_RDH1R_DATA5_Pos (8U)
2714#define CAN_RDH1R_DATA5_Msk (0xFFUL << CAN_RDH1R_DATA5_Pos)
2715#define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk
2716#define CAN_RDH1R_DATA6_Pos (16U)
2717#define CAN_RDH1R_DATA6_Msk (0xFFUL << CAN_RDH1R_DATA6_Pos)
2718#define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk
2719#define CAN_RDH1R_DATA7_Pos (24U)
2720#define CAN_RDH1R_DATA7_Msk (0xFFUL << CAN_RDH1R_DATA7_Pos)
2721#define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk
2724/******************* Bit definition for CAN_FMR register ********************/
2725#define CAN_FMR_FINIT_Pos (0U)
2726#define CAN_FMR_FINIT_Msk (0x1UL << CAN_FMR_FINIT_Pos)
2727#define CAN_FMR_FINIT CAN_FMR_FINIT_Msk
2729/******************* Bit definition for CAN_FM1R register *******************/
2730#define CAN_FM1R_FBM_Pos (0U)
2731#define CAN_FM1R_FBM_Msk (0x3FFFUL << CAN_FM1R_FBM_Pos)
2732#define CAN_FM1R_FBM CAN_FM1R_FBM_Msk
2733#define CAN_FM1R_FBM0_Pos (0U)
2734#define CAN_FM1R_FBM0_Msk (0x1UL << CAN_FM1R_FBM0_Pos)
2735#define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk
2736#define CAN_FM1R_FBM1_Pos (1U)
2737#define CAN_FM1R_FBM1_Msk (0x1UL << CAN_FM1R_FBM1_Pos)
2738#define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk
2739#define CAN_FM1R_FBM2_Pos (2U)
2740#define CAN_FM1R_FBM2_Msk (0x1UL << CAN_FM1R_FBM2_Pos)
2741#define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk
2742#define CAN_FM1R_FBM3_Pos (3U)
2743#define CAN_FM1R_FBM3_Msk (0x1UL << CAN_FM1R_FBM3_Pos)
2744#define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk
2745#define CAN_FM1R_FBM4_Pos (4U)
2746#define CAN_FM1R_FBM4_Msk (0x1UL << CAN_FM1R_FBM4_Pos)
2747#define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk
2748#define CAN_FM1R_FBM5_Pos (5U)
2749#define CAN_FM1R_FBM5_Msk (0x1UL << CAN_FM1R_FBM5_Pos)
2750#define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk
2751#define CAN_FM1R_FBM6_Pos (6U)
2752#define CAN_FM1R_FBM6_Msk (0x1UL << CAN_FM1R_FBM6_Pos)
2753#define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk
2754#define CAN_FM1R_FBM7_Pos (7U)
2755#define CAN_FM1R_FBM7_Msk (0x1UL << CAN_FM1R_FBM7_Pos)
2756#define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk
2757#define CAN_FM1R_FBM8_Pos (8U)
2758#define CAN_FM1R_FBM8_Msk (0x1UL << CAN_FM1R_FBM8_Pos)
2759#define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk
2760#define CAN_FM1R_FBM9_Pos (9U)
2761#define CAN_FM1R_FBM9_Msk (0x1UL << CAN_FM1R_FBM9_Pos)
2762#define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk
2763#define CAN_FM1R_FBM10_Pos (10U)
2764#define CAN_FM1R_FBM10_Msk (0x1UL << CAN_FM1R_FBM10_Pos)
2765#define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk
2766#define CAN_FM1R_FBM11_Pos (11U)
2767#define CAN_FM1R_FBM11_Msk (0x1UL << CAN_FM1R_FBM11_Pos)
2768#define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk
2769#define CAN_FM1R_FBM12_Pos (12U)
2770#define CAN_FM1R_FBM12_Msk (0x1UL << CAN_FM1R_FBM12_Pos)
2771#define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk
2772#define CAN_FM1R_FBM13_Pos (13U)
2773#define CAN_FM1R_FBM13_Msk (0x1UL << CAN_FM1R_FBM13_Pos)
2774#define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk
2776/******************* Bit definition for CAN_FS1R register *******************/
2777#define CAN_FS1R_FSC_Pos (0U)
2778#define CAN_FS1R_FSC_Msk (0x3FFFUL << CAN_FS1R_FSC_Pos)
2779#define CAN_FS1R_FSC CAN_FS1R_FSC_Msk
2780#define CAN_FS1R_FSC0_Pos (0U)
2781#define CAN_FS1R_FSC0_Msk (0x1UL << CAN_FS1R_FSC0_Pos)
2782#define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk
2783#define CAN_FS1R_FSC1_Pos (1U)
2784#define CAN_FS1R_FSC1_Msk (0x1UL << CAN_FS1R_FSC1_Pos)
2785#define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk
2786#define CAN_FS1R_FSC2_Pos (2U)
2787#define CAN_FS1R_FSC2_Msk (0x1UL << CAN_FS1R_FSC2_Pos)
2788#define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk
2789#define CAN_FS1R_FSC3_Pos (3U)
2790#define CAN_FS1R_FSC3_Msk (0x1UL << CAN_FS1R_FSC3_Pos)
2791#define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk
2792#define CAN_FS1R_FSC4_Pos (4U)
2793#define CAN_FS1R_FSC4_Msk (0x1UL << CAN_FS1R_FSC4_Pos)
2794#define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk
2795#define CAN_FS1R_FSC5_Pos (5U)
2796#define CAN_FS1R_FSC5_Msk (0x1UL << CAN_FS1R_FSC5_Pos)
2797#define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk
2798#define CAN_FS1R_FSC6_Pos (6U)
2799#define CAN_FS1R_FSC6_Msk (0x1UL << CAN_FS1R_FSC6_Pos)
2800#define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk
2801#define CAN_FS1R_FSC7_Pos (7U)
2802#define CAN_FS1R_FSC7_Msk (0x1UL << CAN_FS1R_FSC7_Pos)
2803#define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk
2804#define CAN_FS1R_FSC8_Pos (8U)
2805#define CAN_FS1R_FSC8_Msk (0x1UL << CAN_FS1R_FSC8_Pos)
2806#define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk
2807#define CAN_FS1R_FSC9_Pos (9U)
2808#define CAN_FS1R_FSC9_Msk (0x1UL << CAN_FS1R_FSC9_Pos)
2809#define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk
2810#define CAN_FS1R_FSC10_Pos (10U)
2811#define CAN_FS1R_FSC10_Msk (0x1UL << CAN_FS1R_FSC10_Pos)
2812#define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk
2813#define CAN_FS1R_FSC11_Pos (11U)
2814#define CAN_FS1R_FSC11_Msk (0x1UL << CAN_FS1R_FSC11_Pos)
2815#define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk
2816#define CAN_FS1R_FSC12_Pos (12U)
2817#define CAN_FS1R_FSC12_Msk (0x1UL << CAN_FS1R_FSC12_Pos)
2818#define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk
2819#define CAN_FS1R_FSC13_Pos (13U)
2820#define CAN_FS1R_FSC13_Msk (0x1UL << CAN_FS1R_FSC13_Pos)
2821#define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk
2823/****************** Bit definition for CAN_FFA1R register *******************/
2824#define CAN_FFA1R_FFA_Pos (0U)
2825#define CAN_FFA1R_FFA_Msk (0x3FFFUL << CAN_FFA1R_FFA_Pos)
2826#define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk
2827#define CAN_FFA1R_FFA0_Pos (0U)
2828#define CAN_FFA1R_FFA0_Msk (0x1UL << CAN_FFA1R_FFA0_Pos)
2829#define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk
2830#define CAN_FFA1R_FFA1_Pos (1U)
2831#define CAN_FFA1R_FFA1_Msk (0x1UL << CAN_FFA1R_FFA1_Pos)
2832#define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk
2833#define CAN_FFA1R_FFA2_Pos (2U)
2834#define CAN_FFA1R_FFA2_Msk (0x1UL << CAN_FFA1R_FFA2_Pos)
2835#define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk
2836#define CAN_FFA1R_FFA3_Pos (3U)
2837#define CAN_FFA1R_FFA3_Msk (0x1UL << CAN_FFA1R_FFA3_Pos)
2838#define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk
2839#define CAN_FFA1R_FFA4_Pos (4U)
2840#define CAN_FFA1R_FFA4_Msk (0x1UL << CAN_FFA1R_FFA4_Pos)
2841#define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk
2842#define CAN_FFA1R_FFA5_Pos (5U)
2843#define CAN_FFA1R_FFA5_Msk (0x1UL << CAN_FFA1R_FFA5_Pos)
2844#define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk
2845#define CAN_FFA1R_FFA6_Pos (6U)
2846#define CAN_FFA1R_FFA6_Msk (0x1UL << CAN_FFA1R_FFA6_Pos)
2847#define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk
2848#define CAN_FFA1R_FFA7_Pos (7U)
2849#define CAN_FFA1R_FFA7_Msk (0x1UL << CAN_FFA1R_FFA7_Pos)
2850#define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk
2851#define CAN_FFA1R_FFA8_Pos (8U)
2852#define CAN_FFA1R_FFA8_Msk (0x1UL << CAN_FFA1R_FFA8_Pos)
2853#define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk
2854#define CAN_FFA1R_FFA9_Pos (9U)
2855#define CAN_FFA1R_FFA9_Msk (0x1UL << CAN_FFA1R_FFA9_Pos)
2856#define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk
2857#define CAN_FFA1R_FFA10_Pos (10U)
2858#define CAN_FFA1R_FFA10_Msk (0x1UL << CAN_FFA1R_FFA10_Pos)
2859#define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk
2860#define CAN_FFA1R_FFA11_Pos (11U)
2861#define CAN_FFA1R_FFA11_Msk (0x1UL << CAN_FFA1R_FFA11_Pos)
2862#define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk
2863#define CAN_FFA1R_FFA12_Pos (12U)
2864#define CAN_FFA1R_FFA12_Msk (0x1UL << CAN_FFA1R_FFA12_Pos)
2865#define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk
2866#define CAN_FFA1R_FFA13_Pos (13U)
2867#define CAN_FFA1R_FFA13_Msk (0x1UL << CAN_FFA1R_FFA13_Pos)
2868#define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk
2870/******************* Bit definition for CAN_FA1R register *******************/
2871#define CAN_FA1R_FACT_Pos (0U)
2872#define CAN_FA1R_FACT_Msk (0x3FFFUL << CAN_FA1R_FACT_Pos)
2873#define CAN_FA1R_FACT CAN_FA1R_FACT_Msk
2874#define CAN_FA1R_FACT0_Pos (0U)
2875#define CAN_FA1R_FACT0_Msk (0x1UL << CAN_FA1R_FACT0_Pos)
2876#define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk
2877#define CAN_FA1R_FACT1_Pos (1U)
2878#define CAN_FA1R_FACT1_Msk (0x1UL << CAN_FA1R_FACT1_Pos)
2879#define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk
2880#define CAN_FA1R_FACT2_Pos (2U)
2881#define CAN_FA1R_FACT2_Msk (0x1UL << CAN_FA1R_FACT2_Pos)
2882#define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk
2883#define CAN_FA1R_FACT3_Pos (3U)
2884#define CAN_FA1R_FACT3_Msk (0x1UL << CAN_FA1R_FACT3_Pos)
2885#define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk
2886#define CAN_FA1R_FACT4_Pos (4U)
2887#define CAN_FA1R_FACT4_Msk (0x1UL << CAN_FA1R_FACT4_Pos)
2888#define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk
2889#define CAN_FA1R_FACT5_Pos (5U)
2890#define CAN_FA1R_FACT5_Msk (0x1UL << CAN_FA1R_FACT5_Pos)
2891#define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk
2892#define CAN_FA1R_FACT6_Pos (6U)
2893#define CAN_FA1R_FACT6_Msk (0x1UL << CAN_FA1R_FACT6_Pos)
2894#define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk
2895#define CAN_FA1R_FACT7_Pos (7U)
2896#define CAN_FA1R_FACT7_Msk (0x1UL << CAN_FA1R_FACT7_Pos)
2897#define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk
2898#define CAN_FA1R_FACT8_Pos (8U)
2899#define CAN_FA1R_FACT8_Msk (0x1UL << CAN_FA1R_FACT8_Pos)
2900#define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk
2901#define CAN_FA1R_FACT9_Pos (9U)
2902#define CAN_FA1R_FACT9_Msk (0x1UL << CAN_FA1R_FACT9_Pos)
2903#define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk
2904#define CAN_FA1R_FACT10_Pos (10U)
2905#define CAN_FA1R_FACT10_Msk (0x1UL << CAN_FA1R_FACT10_Pos)
2906#define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk
2907#define CAN_FA1R_FACT11_Pos (11U)
2908#define CAN_FA1R_FACT11_Msk (0x1UL << CAN_FA1R_FACT11_Pos)
2909#define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk
2910#define CAN_FA1R_FACT12_Pos (12U)
2911#define CAN_FA1R_FACT12_Msk (0x1UL << CAN_FA1R_FACT12_Pos)
2912#define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk
2913#define CAN_FA1R_FACT13_Pos (13U)
2914#define CAN_FA1R_FACT13_Msk (0x1UL << CAN_FA1R_FACT13_Pos)
2915#define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk
2917/******************* Bit definition for CAN_F0R1 register *******************/
2918#define CAN_F0R1_FB0_Pos (0U)
2919#define CAN_F0R1_FB0_Msk (0x1UL << CAN_F0R1_FB0_Pos)
2920#define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk
2921#define CAN_F0R1_FB1_Pos (1U)
2922#define CAN_F0R1_FB1_Msk (0x1UL << CAN_F0R1_FB1_Pos)
2923#define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk
2924#define CAN_F0R1_FB2_Pos (2U)
2925#define CAN_F0R1_FB2_Msk (0x1UL << CAN_F0R1_FB2_Pos)
2926#define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk
2927#define CAN_F0R1_FB3_Pos (3U)
2928#define CAN_F0R1_FB3_Msk (0x1UL << CAN_F0R1_FB3_Pos)
2929#define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk
2930#define CAN_F0R1_FB4_Pos (4U)
2931#define CAN_F0R1_FB4_Msk (0x1UL << CAN_F0R1_FB4_Pos)
2932#define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk
2933#define CAN_F0R1_FB5_Pos (5U)
2934#define CAN_F0R1_FB5_Msk (0x1UL << CAN_F0R1_FB5_Pos)
2935#define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk
2936#define CAN_F0R1_FB6_Pos (6U)
2937#define CAN_F0R1_FB6_Msk (0x1UL << CAN_F0R1_FB6_Pos)
2938#define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk
2939#define CAN_F0R1_FB7_Pos (7U)
2940#define CAN_F0R1_FB7_Msk (0x1UL << CAN_F0R1_FB7_Pos)
2941#define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk
2942#define CAN_F0R1_FB8_Pos (8U)
2943#define CAN_F0R1_FB8_Msk (0x1UL << CAN_F0R1_FB8_Pos)
2944#define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk
2945#define CAN_F0R1_FB9_Pos (9U)
2946#define CAN_F0R1_FB9_Msk (0x1UL << CAN_F0R1_FB9_Pos)
2947#define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk
2948#define CAN_F0R1_FB10_Pos (10U)
2949#define CAN_F0R1_FB10_Msk (0x1UL << CAN_F0R1_FB10_Pos)
2950#define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk
2951#define CAN_F0R1_FB11_Pos (11U)
2952#define CAN_F0R1_FB11_Msk (0x1UL << CAN_F0R1_FB11_Pos)
2953#define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk
2954#define CAN_F0R1_FB12_Pos (12U)
2955#define CAN_F0R1_FB12_Msk (0x1UL << CAN_F0R1_FB12_Pos)
2956#define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk
2957#define CAN_F0R1_FB13_Pos (13U)
2958#define CAN_F0R1_FB13_Msk (0x1UL << CAN_F0R1_FB13_Pos)
2959#define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk
2960#define CAN_F0R1_FB14_Pos (14U)
2961#define CAN_F0R1_FB14_Msk (0x1UL << CAN_F0R1_FB14_Pos)
2962#define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk
2963#define CAN_F0R1_FB15_Pos (15U)
2964#define CAN_F0R1_FB15_Msk (0x1UL << CAN_F0R1_FB15_Pos)
2965#define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk
2966#define CAN_F0R1_FB16_Pos (16U)
2967#define CAN_F0R1_FB16_Msk (0x1UL << CAN_F0R1_FB16_Pos)
2968#define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk
2969#define CAN_F0R1_FB17_Pos (17U)
2970#define CAN_F0R1_FB17_Msk (0x1UL << CAN_F0R1_FB17_Pos)
2971#define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk
2972#define CAN_F0R1_FB18_Pos (18U)
2973#define CAN_F0R1_FB18_Msk (0x1UL << CAN_F0R1_FB18_Pos)
2974#define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk
2975#define CAN_F0R1_FB19_Pos (19U)
2976#define CAN_F0R1_FB19_Msk (0x1UL << CAN_F0R1_FB19_Pos)
2977#define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk
2978#define CAN_F0R1_FB20_Pos (20U)
2979#define CAN_F0R1_FB20_Msk (0x1UL << CAN_F0R1_FB20_Pos)
2980#define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk
2981#define CAN_F0R1_FB21_Pos (21U)
2982#define CAN_F0R1_FB21_Msk (0x1UL << CAN_F0R1_FB21_Pos)
2983#define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk
2984#define CAN_F0R1_FB22_Pos (22U)
2985#define CAN_F0R1_FB22_Msk (0x1UL << CAN_F0R1_FB22_Pos)
2986#define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk
2987#define CAN_F0R1_FB23_Pos (23U)
2988#define CAN_F0R1_FB23_Msk (0x1UL << CAN_F0R1_FB23_Pos)
2989#define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk
2990#define CAN_F0R1_FB24_Pos (24U)
2991#define CAN_F0R1_FB24_Msk (0x1UL << CAN_F0R1_FB24_Pos)
2992#define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk
2993#define CAN_F0R1_FB25_Pos (25U)
2994#define CAN_F0R1_FB25_Msk (0x1UL << CAN_F0R1_FB25_Pos)
2995#define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk
2996#define CAN_F0R1_FB26_Pos (26U)
2997#define CAN_F0R1_FB26_Msk (0x1UL << CAN_F0R1_FB26_Pos)
2998#define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk
2999#define CAN_F0R1_FB27_Pos (27U)
3000#define CAN_F0R1_FB27_Msk (0x1UL << CAN_F0R1_FB27_Pos)
3001#define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk
3002#define CAN_F0R1_FB28_Pos (28U)
3003#define CAN_F0R1_FB28_Msk (0x1UL << CAN_F0R1_FB28_Pos)
3004#define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk
3005#define CAN_F0R1_FB29_Pos (29U)
3006#define CAN_F0R1_FB29_Msk (0x1UL << CAN_F0R1_FB29_Pos)
3007#define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk
3008#define CAN_F0R1_FB30_Pos (30U)
3009#define CAN_F0R1_FB30_Msk (0x1UL << CAN_F0R1_FB30_Pos)
3010#define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk
3011#define CAN_F0R1_FB31_Pos (31U)
3012#define CAN_F0R1_FB31_Msk (0x1UL << CAN_F0R1_FB31_Pos)
3013#define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk
3015/******************* Bit definition for CAN_F1R1 register *******************/
3016#define CAN_F1R1_FB0_Pos (0U)
3017#define CAN_F1R1_FB0_Msk (0x1UL << CAN_F1R1_FB0_Pos)
3018#define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk
3019#define CAN_F1R1_FB1_Pos (1U)
3020#define CAN_F1R1_FB1_Msk (0x1UL << CAN_F1R1_FB1_Pos)
3021#define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk
3022#define CAN_F1R1_FB2_Pos (2U)
3023#define CAN_F1R1_FB2_Msk (0x1UL << CAN_F1R1_FB2_Pos)
3024#define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk
3025#define CAN_F1R1_FB3_Pos (3U)
3026#define CAN_F1R1_FB3_Msk (0x1UL << CAN_F1R1_FB3_Pos)
3027#define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk
3028#define CAN_F1R1_FB4_Pos (4U)
3029#define CAN_F1R1_FB4_Msk (0x1UL << CAN_F1R1_FB4_Pos)
3030#define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk
3031#define CAN_F1R1_FB5_Pos (5U)
3032#define CAN_F1R1_FB5_Msk (0x1UL << CAN_F1R1_FB5_Pos)
3033#define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk
3034#define CAN_F1R1_FB6_Pos (6U)
3035#define CAN_F1R1_FB6_Msk (0x1UL << CAN_F1R1_FB6_Pos)
3036#define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk
3037#define CAN_F1R1_FB7_Pos (7U)
3038#define CAN_F1R1_FB7_Msk (0x1UL << CAN_F1R1_FB7_Pos)
3039#define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk
3040#define CAN_F1R1_FB8_Pos (8U)
3041#define CAN_F1R1_FB8_Msk (0x1UL << CAN_F1R1_FB8_Pos)
3042#define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk
3043#define CAN_F1R1_FB9_Pos (9U)
3044#define CAN_F1R1_FB9_Msk (0x1UL << CAN_F1R1_FB9_Pos)
3045#define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk
3046#define CAN_F1R1_FB10_Pos (10U)
3047#define CAN_F1R1_FB10_Msk (0x1UL << CAN_F1R1_FB10_Pos)
3048#define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk
3049#define CAN_F1R1_FB11_Pos (11U)
3050#define CAN_F1R1_FB11_Msk (0x1UL << CAN_F1R1_FB11_Pos)
3051#define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk
3052#define CAN_F1R1_FB12_Pos (12U)
3053#define CAN_F1R1_FB12_Msk (0x1UL << CAN_F1R1_FB12_Pos)
3054#define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk
3055#define CAN_F1R1_FB13_Pos (13U)
3056#define CAN_F1R1_FB13_Msk (0x1UL << CAN_F1R1_FB13_Pos)
3057#define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk
3058#define CAN_F1R1_FB14_Pos (14U)
3059#define CAN_F1R1_FB14_Msk (0x1UL << CAN_F1R1_FB14_Pos)
3060#define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk
3061#define CAN_F1R1_FB15_Pos (15U)
3062#define CAN_F1R1_FB15_Msk (0x1UL << CAN_F1R1_FB15_Pos)
3063#define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk
3064#define CAN_F1R1_FB16_Pos (16U)
3065#define CAN_F1R1_FB16_Msk (0x1UL << CAN_F1R1_FB16_Pos)
3066#define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk
3067#define CAN_F1R1_FB17_Pos (17U)
3068#define CAN_F1R1_FB17_Msk (0x1UL << CAN_F1R1_FB17_Pos)
3069#define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk
3070#define CAN_F1R1_FB18_Pos (18U)
3071#define CAN_F1R1_FB18_Msk (0x1UL << CAN_F1R1_FB18_Pos)
3072#define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk
3073#define CAN_F1R1_FB19_Pos (19U)
3074#define CAN_F1R1_FB19_Msk (0x1UL << CAN_F1R1_FB19_Pos)
3075#define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk
3076#define CAN_F1R1_FB20_Pos (20U)
3077#define CAN_F1R1_FB20_Msk (0x1UL << CAN_F1R1_FB20_Pos)
3078#define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk
3079#define CAN_F1R1_FB21_Pos (21U)
3080#define CAN_F1R1_FB21_Msk (0x1UL << CAN_F1R1_FB21_Pos)
3081#define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk
3082#define CAN_F1R1_FB22_Pos (22U)
3083#define CAN_F1R1_FB22_Msk (0x1UL << CAN_F1R1_FB22_Pos)
3084#define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk
3085#define CAN_F1R1_FB23_Pos (23U)
3086#define CAN_F1R1_FB23_Msk (0x1UL << CAN_F1R1_FB23_Pos)
3087#define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk
3088#define CAN_F1R1_FB24_Pos (24U)
3089#define CAN_F1R1_FB24_Msk (0x1UL << CAN_F1R1_FB24_Pos)
3090#define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk
3091#define CAN_F1R1_FB25_Pos (25U)
3092#define CAN_F1R1_FB25_Msk (0x1UL << CAN_F1R1_FB25_Pos)
3093#define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk
3094#define CAN_F1R1_FB26_Pos (26U)
3095#define CAN_F1R1_FB26_Msk (0x1UL << CAN_F1R1_FB26_Pos)
3096#define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk
3097#define CAN_F1R1_FB27_Pos (27U)
3098#define CAN_F1R1_FB27_Msk (0x1UL << CAN_F1R1_FB27_Pos)
3099#define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk
3100#define CAN_F1R1_FB28_Pos (28U)
3101#define CAN_F1R1_FB28_Msk (0x1UL << CAN_F1R1_FB28_Pos)
3102#define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk
3103#define CAN_F1R1_FB29_Pos (29U)
3104#define CAN_F1R1_FB29_Msk (0x1UL << CAN_F1R1_FB29_Pos)
3105#define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk
3106#define CAN_F1R1_FB30_Pos (30U)
3107#define CAN_F1R1_FB30_Msk (0x1UL << CAN_F1R1_FB30_Pos)
3108#define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk
3109#define CAN_F1R1_FB31_Pos (31U)
3110#define CAN_F1R1_FB31_Msk (0x1UL << CAN_F1R1_FB31_Pos)
3111#define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk
3113/******************* Bit definition for CAN_F2R1 register *******************/
3114#define CAN_F2R1_FB0_Pos (0U)
3115#define CAN_F2R1_FB0_Msk (0x1UL << CAN_F2R1_FB0_Pos)
3116#define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk
3117#define CAN_F2R1_FB1_Pos (1U)
3118#define CAN_F2R1_FB1_Msk (0x1UL << CAN_F2R1_FB1_Pos)
3119#define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk
3120#define CAN_F2R1_FB2_Pos (2U)
3121#define CAN_F2R1_FB2_Msk (0x1UL << CAN_F2R1_FB2_Pos)
3122#define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk
3123#define CAN_F2R1_FB3_Pos (3U)
3124#define CAN_F2R1_FB3_Msk (0x1UL << CAN_F2R1_FB3_Pos)
3125#define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk
3126#define CAN_F2R1_FB4_Pos (4U)
3127#define CAN_F2R1_FB4_Msk (0x1UL << CAN_F2R1_FB4_Pos)
3128#define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk
3129#define CAN_F2R1_FB5_Pos (5U)
3130#define CAN_F2R1_FB5_Msk (0x1UL << CAN_F2R1_FB5_Pos)
3131#define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk
3132#define CAN_F2R1_FB6_Pos (6U)
3133#define CAN_F2R1_FB6_Msk (0x1UL << CAN_F2R1_FB6_Pos)
3134#define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk
3135#define CAN_F2R1_FB7_Pos (7U)
3136#define CAN_F2R1_FB7_Msk (0x1UL << CAN_F2R1_FB7_Pos)
3137#define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk
3138#define CAN_F2R1_FB8_Pos (8U)
3139#define CAN_F2R1_FB8_Msk (0x1UL << CAN_F2R1_FB8_Pos)
3140#define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk
3141#define CAN_F2R1_FB9_Pos (9U)
3142#define CAN_F2R1_FB9_Msk (0x1UL << CAN_F2R1_FB9_Pos)
3143#define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk
3144#define CAN_F2R1_FB10_Pos (10U)
3145#define CAN_F2R1_FB10_Msk (0x1UL << CAN_F2R1_FB10_Pos)
3146#define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk
3147#define CAN_F2R1_FB11_Pos (11U)
3148#define CAN_F2R1_FB11_Msk (0x1UL << CAN_F2R1_FB11_Pos)
3149#define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk
3150#define CAN_F2R1_FB12_Pos (12U)
3151#define CAN_F2R1_FB12_Msk (0x1UL << CAN_F2R1_FB12_Pos)
3152#define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk
3153#define CAN_F2R1_FB13_Pos (13U)
3154#define CAN_F2R1_FB13_Msk (0x1UL << CAN_F2R1_FB13_Pos)
3155#define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk
3156#define CAN_F2R1_FB14_Pos (14U)
3157#define CAN_F2R1_FB14_Msk (0x1UL << CAN_F2R1_FB14_Pos)
3158#define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk
3159#define CAN_F2R1_FB15_Pos (15U)
3160#define CAN_F2R1_FB15_Msk (0x1UL << CAN_F2R1_FB15_Pos)
3161#define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk
3162#define CAN_F2R1_FB16_Pos (16U)
3163#define CAN_F2R1_FB16_Msk (0x1UL << CAN_F2R1_FB16_Pos)
3164#define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk
3165#define CAN_F2R1_FB17_Pos (17U)
3166#define CAN_F2R1_FB17_Msk (0x1UL << CAN_F2R1_FB17_Pos)
3167#define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk
3168#define CAN_F2R1_FB18_Pos (18U)
3169#define CAN_F2R1_FB18_Msk (0x1UL << CAN_F2R1_FB18_Pos)
3170#define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk
3171#define CAN_F2R1_FB19_Pos (19U)
3172#define CAN_F2R1_FB19_Msk (0x1UL << CAN_F2R1_FB19_Pos)
3173#define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk
3174#define CAN_F2R1_FB20_Pos (20U)
3175#define CAN_F2R1_FB20_Msk (0x1UL << CAN_F2R1_FB20_Pos)
3176#define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk
3177#define CAN_F2R1_FB21_Pos (21U)
3178#define CAN_F2R1_FB21_Msk (0x1UL << CAN_F2R1_FB21_Pos)
3179#define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk
3180#define CAN_F2R1_FB22_Pos (22U)
3181#define CAN_F2R1_FB22_Msk (0x1UL << CAN_F2R1_FB22_Pos)
3182#define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk
3183#define CAN_F2R1_FB23_Pos (23U)
3184#define CAN_F2R1_FB23_Msk (0x1UL << CAN_F2R1_FB23_Pos)
3185#define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk
3186#define CAN_F2R1_FB24_Pos (24U)
3187#define CAN_F2R1_FB24_Msk (0x1UL << CAN_F2R1_FB24_Pos)
3188#define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk
3189#define CAN_F2R1_FB25_Pos (25U)
3190#define CAN_F2R1_FB25_Msk (0x1UL << CAN_F2R1_FB25_Pos)
3191#define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk
3192#define CAN_F2R1_FB26_Pos (26U)
3193#define CAN_F2R1_FB26_Msk (0x1UL << CAN_F2R1_FB26_Pos)
3194#define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk
3195#define CAN_F2R1_FB27_Pos (27U)
3196#define CAN_F2R1_FB27_Msk (0x1UL << CAN_F2R1_FB27_Pos)
3197#define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk
3198#define CAN_F2R1_FB28_Pos (28U)
3199#define CAN_F2R1_FB28_Msk (0x1UL << CAN_F2R1_FB28_Pos)
3200#define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk
3201#define CAN_F2R1_FB29_Pos (29U)
3202#define CAN_F2R1_FB29_Msk (0x1UL << CAN_F2R1_FB29_Pos)
3203#define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk
3204#define CAN_F2R1_FB30_Pos (30U)
3205#define CAN_F2R1_FB30_Msk (0x1UL << CAN_F2R1_FB30_Pos)
3206#define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk
3207#define CAN_F2R1_FB31_Pos (31U)
3208#define CAN_F2R1_FB31_Msk (0x1UL << CAN_F2R1_FB31_Pos)
3209#define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk
3211/******************* Bit definition for CAN_F3R1 register *******************/
3212#define CAN_F3R1_FB0_Pos (0U)
3213#define CAN_F3R1_FB0_Msk (0x1UL << CAN_F3R1_FB0_Pos)
3214#define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk
3215#define CAN_F3R1_FB1_Pos (1U)
3216#define CAN_F3R1_FB1_Msk (0x1UL << CAN_F3R1_FB1_Pos)
3217#define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk
3218#define CAN_F3R1_FB2_Pos (2U)
3219#define CAN_F3R1_FB2_Msk (0x1UL << CAN_F3R1_FB2_Pos)
3220#define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk
3221#define CAN_F3R1_FB3_Pos (3U)
3222#define CAN_F3R1_FB3_Msk (0x1UL << CAN_F3R1_FB3_Pos)
3223#define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk
3224#define CAN_F3R1_FB4_Pos (4U)
3225#define CAN_F3R1_FB4_Msk (0x1UL << CAN_F3R1_FB4_Pos)
3226#define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk
3227#define CAN_F3R1_FB5_Pos (5U)
3228#define CAN_F3R1_FB5_Msk (0x1UL << CAN_F3R1_FB5_Pos)
3229#define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk
3230#define CAN_F3R1_FB6_Pos (6U)
3231#define CAN_F3R1_FB6_Msk (0x1UL << CAN_F3R1_FB6_Pos)
3232#define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk
3233#define CAN_F3R1_FB7_Pos (7U)
3234#define CAN_F3R1_FB7_Msk (0x1UL << CAN_F3R1_FB7_Pos)
3235#define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk
3236#define CAN_F3R1_FB8_Pos (8U)
3237#define CAN_F3R1_FB8_Msk (0x1UL << CAN_F3R1_FB8_Pos)
3238#define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk
3239#define CAN_F3R1_FB9_Pos (9U)
3240#define CAN_F3R1_FB9_Msk (0x1UL << CAN_F3R1_FB9_Pos)
3241#define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk
3242#define CAN_F3R1_FB10_Pos (10U)
3243#define CAN_F3R1_FB10_Msk (0x1UL << CAN_F3R1_FB10_Pos)
3244#define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk
3245#define CAN_F3R1_FB11_Pos (11U)
3246#define CAN_F3R1_FB11_Msk (0x1UL << CAN_F3R1_FB11_Pos)
3247#define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk
3248#define CAN_F3R1_FB12_Pos (12U)
3249#define CAN_F3R1_FB12_Msk (0x1UL << CAN_F3R1_FB12_Pos)
3250#define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk
3251#define CAN_F3R1_FB13_Pos (13U)
3252#define CAN_F3R1_FB13_Msk (0x1UL << CAN_F3R1_FB13_Pos)
3253#define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk
3254#define CAN_F3R1_FB14_Pos (14U)
3255#define CAN_F3R1_FB14_Msk (0x1UL << CAN_F3R1_FB14_Pos)
3256#define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk
3257#define CAN_F3R1_FB15_Pos (15U)
3258#define CAN_F3R1_FB15_Msk (0x1UL << CAN_F3R1_FB15_Pos)
3259#define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk
3260#define CAN_F3R1_FB16_Pos (16U)
3261#define CAN_F3R1_FB16_Msk (0x1UL << CAN_F3R1_FB16_Pos)
3262#define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk
3263#define CAN_F3R1_FB17_Pos (17U)
3264#define CAN_F3R1_FB17_Msk (0x1UL << CAN_F3R1_FB17_Pos)
3265#define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk
3266#define CAN_F3R1_FB18_Pos (18U)
3267#define CAN_F3R1_FB18_Msk (0x1UL << CAN_F3R1_FB18_Pos)
3268#define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk
3269#define CAN_F3R1_FB19_Pos (19U)
3270#define CAN_F3R1_FB19_Msk (0x1UL << CAN_F3R1_FB19_Pos)
3271#define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk
3272#define CAN_F3R1_FB20_Pos (20U)
3273#define CAN_F3R1_FB20_Msk (0x1UL << CAN_F3R1_FB20_Pos)
3274#define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk
3275#define CAN_F3R1_FB21_Pos (21U)
3276#define CAN_F3R1_FB21_Msk (0x1UL << CAN_F3R1_FB21_Pos)
3277#define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk
3278#define CAN_F3R1_FB22_Pos (22U)
3279#define CAN_F3R1_FB22_Msk (0x1UL << CAN_F3R1_FB22_Pos)
3280#define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk
3281#define CAN_F3R1_FB23_Pos (23U)
3282#define CAN_F3R1_FB23_Msk (0x1UL << CAN_F3R1_FB23_Pos)
3283#define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk
3284#define CAN_F3R1_FB24_Pos (24U)
3285#define CAN_F3R1_FB24_Msk (0x1UL << CAN_F3R1_FB24_Pos)
3286#define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk
3287#define CAN_F3R1_FB25_Pos (25U)
3288#define CAN_F3R1_FB25_Msk (0x1UL << CAN_F3R1_FB25_Pos)
3289#define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk
3290#define CAN_F3R1_FB26_Pos (26U)
3291#define CAN_F3R1_FB26_Msk (0x1UL << CAN_F3R1_FB26_Pos)
3292#define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk
3293#define CAN_F3R1_FB27_Pos (27U)
3294#define CAN_F3R1_FB27_Msk (0x1UL << CAN_F3R1_FB27_Pos)
3295#define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk
3296#define CAN_F3R1_FB28_Pos (28U)
3297#define CAN_F3R1_FB28_Msk (0x1UL << CAN_F3R1_FB28_Pos)
3298#define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk
3299#define CAN_F3R1_FB29_Pos (29U)
3300#define CAN_F3R1_FB29_Msk (0x1UL << CAN_F3R1_FB29_Pos)
3301#define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk
3302#define CAN_F3R1_FB30_Pos (30U)
3303#define CAN_F3R1_FB30_Msk (0x1UL << CAN_F3R1_FB30_Pos)
3304#define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk
3305#define CAN_F3R1_FB31_Pos (31U)
3306#define CAN_F3R1_FB31_Msk (0x1UL << CAN_F3R1_FB31_Pos)
3307#define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk
3309/******************* Bit definition for CAN_F4R1 register *******************/
3310#define CAN_F4R1_FB0_Pos (0U)
3311#define CAN_F4R1_FB0_Msk (0x1UL << CAN_F4R1_FB0_Pos)
3312#define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk
3313#define CAN_F4R1_FB1_Pos (1U)
3314#define CAN_F4R1_FB1_Msk (0x1UL << CAN_F4R1_FB1_Pos)
3315#define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk
3316#define CAN_F4R1_FB2_Pos (2U)
3317#define CAN_F4R1_FB2_Msk (0x1UL << CAN_F4R1_FB2_Pos)
3318#define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk
3319#define CAN_F4R1_FB3_Pos (3U)
3320#define CAN_F4R1_FB3_Msk (0x1UL << CAN_F4R1_FB3_Pos)
3321#define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk
3322#define CAN_F4R1_FB4_Pos (4U)
3323#define CAN_F4R1_FB4_Msk (0x1UL << CAN_F4R1_FB4_Pos)
3324#define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk
3325#define CAN_F4R1_FB5_Pos (5U)
3326#define CAN_F4R1_FB5_Msk (0x1UL << CAN_F4R1_FB5_Pos)
3327#define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk
3328#define CAN_F4R1_FB6_Pos (6U)
3329#define CAN_F4R1_FB6_Msk (0x1UL << CAN_F4R1_FB6_Pos)
3330#define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk
3331#define CAN_F4R1_FB7_Pos (7U)
3332#define CAN_F4R1_FB7_Msk (0x1UL << CAN_F4R1_FB7_Pos)
3333#define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk
3334#define CAN_F4R1_FB8_Pos (8U)
3335#define CAN_F4R1_FB8_Msk (0x1UL << CAN_F4R1_FB8_Pos)
3336#define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk
3337#define CAN_F4R1_FB9_Pos (9U)
3338#define CAN_F4R1_FB9_Msk (0x1UL << CAN_F4R1_FB9_Pos)
3339#define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk
3340#define CAN_F4R1_FB10_Pos (10U)
3341#define CAN_F4R1_FB10_Msk (0x1UL << CAN_F4R1_FB10_Pos)
3342#define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk
3343#define CAN_F4R1_FB11_Pos (11U)
3344#define CAN_F4R1_FB11_Msk (0x1UL << CAN_F4R1_FB11_Pos)
3345#define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk
3346#define CAN_F4R1_FB12_Pos (12U)
3347#define CAN_F4R1_FB12_Msk (0x1UL << CAN_F4R1_FB12_Pos)
3348#define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk
3349#define CAN_F4R1_FB13_Pos (13U)
3350#define CAN_F4R1_FB13_Msk (0x1UL << CAN_F4R1_FB13_Pos)
3351#define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk
3352#define CAN_F4R1_FB14_Pos (14U)
3353#define CAN_F4R1_FB14_Msk (0x1UL << CAN_F4R1_FB14_Pos)
3354#define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk
3355#define CAN_F4R1_FB15_Pos (15U)
3356#define CAN_F4R1_FB15_Msk (0x1UL << CAN_F4R1_FB15_Pos)
3357#define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk
3358#define CAN_F4R1_FB16_Pos (16U)
3359#define CAN_F4R1_FB16_Msk (0x1UL << CAN_F4R1_FB16_Pos)
3360#define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk
3361#define CAN_F4R1_FB17_Pos (17U)
3362#define CAN_F4R1_FB17_Msk (0x1UL << CAN_F4R1_FB17_Pos)
3363#define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk
3364#define CAN_F4R1_FB18_Pos (18U)
3365#define CAN_F4R1_FB18_Msk (0x1UL << CAN_F4R1_FB18_Pos)
3366#define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk
3367#define CAN_F4R1_FB19_Pos (19U)
3368#define CAN_F4R1_FB19_Msk (0x1UL << CAN_F4R1_FB19_Pos)
3369#define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk
3370#define CAN_F4R1_FB20_Pos (20U)
3371#define CAN_F4R1_FB20_Msk (0x1UL << CAN_F4R1_FB20_Pos)
3372#define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk
3373#define CAN_F4R1_FB21_Pos (21U)
3374#define CAN_F4R1_FB21_Msk (0x1UL << CAN_F4R1_FB21_Pos)
3375#define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk
3376#define CAN_F4R1_FB22_Pos (22U)
3377#define CAN_F4R1_FB22_Msk (0x1UL << CAN_F4R1_FB22_Pos)
3378#define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk
3379#define CAN_F4R1_FB23_Pos (23U)
3380#define CAN_F4R1_FB23_Msk (0x1UL << CAN_F4R1_FB23_Pos)
3381#define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk
3382#define CAN_F4R1_FB24_Pos (24U)
3383#define CAN_F4R1_FB24_Msk (0x1UL << CAN_F4R1_FB24_Pos)
3384#define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk
3385#define CAN_F4R1_FB25_Pos (25U)
3386#define CAN_F4R1_FB25_Msk (0x1UL << CAN_F4R1_FB25_Pos)
3387#define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk
3388#define CAN_F4R1_FB26_Pos (26U)
3389#define CAN_F4R1_FB26_Msk (0x1UL << CAN_F4R1_FB26_Pos)
3390#define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk
3391#define CAN_F4R1_FB27_Pos (27U)
3392#define CAN_F4R1_FB27_Msk (0x1UL << CAN_F4R1_FB27_Pos)
3393#define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk
3394#define CAN_F4R1_FB28_Pos (28U)
3395#define CAN_F4R1_FB28_Msk (0x1UL << CAN_F4R1_FB28_Pos)
3396#define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk
3397#define CAN_F4R1_FB29_Pos (29U)
3398#define CAN_F4R1_FB29_Msk (0x1UL << CAN_F4R1_FB29_Pos)
3399#define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk
3400#define CAN_F4R1_FB30_Pos (30U)
3401#define CAN_F4R1_FB30_Msk (0x1UL << CAN_F4R1_FB30_Pos)
3402#define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk
3403#define CAN_F4R1_FB31_Pos (31U)
3404#define CAN_F4R1_FB31_Msk (0x1UL << CAN_F4R1_FB31_Pos)
3405#define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk
3407/******************* Bit definition for CAN_F5R1 register *******************/
3408#define CAN_F5R1_FB0_Pos (0U)
3409#define CAN_F5R1_FB0_Msk (0x1UL << CAN_F5R1_FB0_Pos)
3410#define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk
3411#define CAN_F5R1_FB1_Pos (1U)
3412#define CAN_F5R1_FB1_Msk (0x1UL << CAN_F5R1_FB1_Pos)
3413#define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk
3414#define CAN_F5R1_FB2_Pos (2U)
3415#define CAN_F5R1_FB2_Msk (0x1UL << CAN_F5R1_FB2_Pos)
3416#define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk
3417#define CAN_F5R1_FB3_Pos (3U)
3418#define CAN_F5R1_FB3_Msk (0x1UL << CAN_F5R1_FB3_Pos)
3419#define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk
3420#define CAN_F5R1_FB4_Pos (4U)
3421#define CAN_F5R1_FB4_Msk (0x1UL << CAN_F5R1_FB4_Pos)
3422#define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk
3423#define CAN_F5R1_FB5_Pos (5U)
3424#define CAN_F5R1_FB5_Msk (0x1UL << CAN_F5R1_FB5_Pos)
3425#define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk
3426#define CAN_F5R1_FB6_Pos (6U)
3427#define CAN_F5R1_FB6_Msk (0x1UL << CAN_F5R1_FB6_Pos)
3428#define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk
3429#define CAN_F5R1_FB7_Pos (7U)
3430#define CAN_F5R1_FB7_Msk (0x1UL << CAN_F5R1_FB7_Pos)
3431#define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk
3432#define CAN_F5R1_FB8_Pos (8U)
3433#define CAN_F5R1_FB8_Msk (0x1UL << CAN_F5R1_FB8_Pos)
3434#define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk
3435#define CAN_F5R1_FB9_Pos (9U)
3436#define CAN_F5R1_FB9_Msk (0x1UL << CAN_F5R1_FB9_Pos)
3437#define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk
3438#define CAN_F5R1_FB10_Pos (10U)
3439#define CAN_F5R1_FB10_Msk (0x1UL << CAN_F5R1_FB10_Pos)
3440#define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk
3441#define CAN_F5R1_FB11_Pos (11U)
3442#define CAN_F5R1_FB11_Msk (0x1UL << CAN_F5R1_FB11_Pos)
3443#define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk
3444#define CAN_F5R1_FB12_Pos (12U)
3445#define CAN_F5R1_FB12_Msk (0x1UL << CAN_F5R1_FB12_Pos)
3446#define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk
3447#define CAN_F5R1_FB13_Pos (13U)
3448#define CAN_F5R1_FB13_Msk (0x1UL << CAN_F5R1_FB13_Pos)
3449#define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk
3450#define CAN_F5R1_FB14_Pos (14U)
3451#define CAN_F5R1_FB14_Msk (0x1UL << CAN_F5R1_FB14_Pos)
3452#define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk
3453#define CAN_F5R1_FB15_Pos (15U)
3454#define CAN_F5R1_FB15_Msk (0x1UL << CAN_F5R1_FB15_Pos)
3455#define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk
3456#define CAN_F5R1_FB16_Pos (16U)
3457#define CAN_F5R1_FB16_Msk (0x1UL << CAN_F5R1_FB16_Pos)
3458#define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk
3459#define CAN_F5R1_FB17_Pos (17U)
3460#define CAN_F5R1_FB17_Msk (0x1UL << CAN_F5R1_FB17_Pos)
3461#define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk
3462#define CAN_F5R1_FB18_Pos (18U)
3463#define CAN_F5R1_FB18_Msk (0x1UL << CAN_F5R1_FB18_Pos)
3464#define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk
3465#define CAN_F5R1_FB19_Pos (19U)
3466#define CAN_F5R1_FB19_Msk (0x1UL << CAN_F5R1_FB19_Pos)
3467#define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk
3468#define CAN_F5R1_FB20_Pos (20U)
3469#define CAN_F5R1_FB20_Msk (0x1UL << CAN_F5R1_FB20_Pos)
3470#define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk
3471#define CAN_F5R1_FB21_Pos (21U)
3472#define CAN_F5R1_FB21_Msk (0x1UL << CAN_F5R1_FB21_Pos)
3473#define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk
3474#define CAN_F5R1_FB22_Pos (22U)
3475#define CAN_F5R1_FB22_Msk (0x1UL << CAN_F5R1_FB22_Pos)
3476#define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk
3477#define CAN_F5R1_FB23_Pos (23U)
3478#define CAN_F5R1_FB23_Msk (0x1UL << CAN_F5R1_FB23_Pos)
3479#define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk
3480#define CAN_F5R1_FB24_Pos (24U)
3481#define CAN_F5R1_FB24_Msk (0x1UL << CAN_F5R1_FB24_Pos)
3482#define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk
3483#define CAN_F5R1_FB25_Pos (25U)
3484#define CAN_F5R1_FB25_Msk (0x1UL << CAN_F5R1_FB25_Pos)
3485#define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk
3486#define CAN_F5R1_FB26_Pos (26U)
3487#define CAN_F5R1_FB26_Msk (0x1UL << CAN_F5R1_FB26_Pos)
3488#define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk
3489#define CAN_F5R1_FB27_Pos (27U)
3490#define CAN_F5R1_FB27_Msk (0x1UL << CAN_F5R1_FB27_Pos)
3491#define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk
3492#define CAN_F5R1_FB28_Pos (28U)
3493#define CAN_F5R1_FB28_Msk (0x1UL << CAN_F5R1_FB28_Pos)
3494#define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk
3495#define CAN_F5R1_FB29_Pos (29U)
3496#define CAN_F5R1_FB29_Msk (0x1UL << CAN_F5R1_FB29_Pos)
3497#define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk
3498#define CAN_F5R1_FB30_Pos (30U)
3499#define CAN_F5R1_FB30_Msk (0x1UL << CAN_F5R1_FB30_Pos)
3500#define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk
3501#define CAN_F5R1_FB31_Pos (31U)
3502#define CAN_F5R1_FB31_Msk (0x1UL << CAN_F5R1_FB31_Pos)
3503#define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk
3505/******************* Bit definition for CAN_F6R1 register *******************/
3506#define CAN_F6R1_FB0_Pos (0U)
3507#define CAN_F6R1_FB0_Msk (0x1UL << CAN_F6R1_FB0_Pos)
3508#define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk
3509#define CAN_F6R1_FB1_Pos (1U)
3510#define CAN_F6R1_FB1_Msk (0x1UL << CAN_F6R1_FB1_Pos)
3511#define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk
3512#define CAN_F6R1_FB2_Pos (2U)
3513#define CAN_F6R1_FB2_Msk (0x1UL << CAN_F6R1_FB2_Pos)
3514#define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk
3515#define CAN_F6R1_FB3_Pos (3U)
3516#define CAN_F6R1_FB3_Msk (0x1UL << CAN_F6R1_FB3_Pos)
3517#define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk
3518#define CAN_F6R1_FB4_Pos (4U)
3519#define CAN_F6R1_FB4_Msk (0x1UL << CAN_F6R1_FB4_Pos)
3520#define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk
3521#define CAN_F6R1_FB5_Pos (5U)
3522#define CAN_F6R1_FB5_Msk (0x1UL << CAN_F6R1_FB5_Pos)
3523#define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk
3524#define CAN_F6R1_FB6_Pos (6U)
3525#define CAN_F6R1_FB6_Msk (0x1UL << CAN_F6R1_FB6_Pos)
3526#define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk
3527#define CAN_F6R1_FB7_Pos (7U)
3528#define CAN_F6R1_FB7_Msk (0x1UL << CAN_F6R1_FB7_Pos)
3529#define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk
3530#define CAN_F6R1_FB8_Pos (8U)
3531#define CAN_F6R1_FB8_Msk (0x1UL << CAN_F6R1_FB8_Pos)
3532#define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk
3533#define CAN_F6R1_FB9_Pos (9U)
3534#define CAN_F6R1_FB9_Msk (0x1UL << CAN_F6R1_FB9_Pos)
3535#define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk
3536#define CAN_F6R1_FB10_Pos (10U)
3537#define CAN_F6R1_FB10_Msk (0x1UL << CAN_F6R1_FB10_Pos)
3538#define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk
3539#define CAN_F6R1_FB11_Pos (11U)
3540#define CAN_F6R1_FB11_Msk (0x1UL << CAN_F6R1_FB11_Pos)
3541#define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk
3542#define CAN_F6R1_FB12_Pos (12U)
3543#define CAN_F6R1_FB12_Msk (0x1UL << CAN_F6R1_FB12_Pos)
3544#define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk
3545#define CAN_F6R1_FB13_Pos (13U)
3546#define CAN_F6R1_FB13_Msk (0x1UL << CAN_F6R1_FB13_Pos)
3547#define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk
3548#define CAN_F6R1_FB14_Pos (14U)
3549#define CAN_F6R1_FB14_Msk (0x1UL << CAN_F6R1_FB14_Pos)
3550#define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk
3551#define CAN_F6R1_FB15_Pos (15U)
3552#define CAN_F6R1_FB15_Msk (0x1UL << CAN_F6R1_FB15_Pos)
3553#define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk
3554#define CAN_F6R1_FB16_Pos (16U)
3555#define CAN_F6R1_FB16_Msk (0x1UL << CAN_F6R1_FB16_Pos)
3556#define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk
3557#define CAN_F6R1_FB17_Pos (17U)
3558#define CAN_F6R1_FB17_Msk (0x1UL << CAN_F6R1_FB17_Pos)
3559#define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk
3560#define CAN_F6R1_FB18_Pos (18U)
3561#define CAN_F6R1_FB18_Msk (0x1UL << CAN_F6R1_FB18_Pos)
3562#define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk
3563#define CAN_F6R1_FB19_Pos (19U)
3564#define CAN_F6R1_FB19_Msk (0x1UL << CAN_F6R1_FB19_Pos)
3565#define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk
3566#define CAN_F6R1_FB20_Pos (20U)
3567#define CAN_F6R1_FB20_Msk (0x1UL << CAN_F6R1_FB20_Pos)
3568#define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk
3569#define CAN_F6R1_FB21_Pos (21U)
3570#define CAN_F6R1_FB21_Msk (0x1UL << CAN_F6R1_FB21_Pos)
3571#define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk
3572#define CAN_F6R1_FB22_Pos (22U)
3573#define CAN_F6R1_FB22_Msk (0x1UL << CAN_F6R1_FB22_Pos)
3574#define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk
3575#define CAN_F6R1_FB23_Pos (23U)
3576#define CAN_F6R1_FB23_Msk (0x1UL << CAN_F6R1_FB23_Pos)
3577#define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk
3578#define CAN_F6R1_FB24_Pos (24U)
3579#define CAN_F6R1_FB24_Msk (0x1UL << CAN_F6R1_FB24_Pos)
3580#define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk
3581#define CAN_F6R1_FB25_Pos (25U)
3582#define CAN_F6R1_FB25_Msk (0x1UL << CAN_F6R1_FB25_Pos)
3583#define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk
3584#define CAN_F6R1_FB26_Pos (26U)
3585#define CAN_F6R1_FB26_Msk (0x1UL << CAN_F6R1_FB26_Pos)
3586#define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk
3587#define CAN_F6R1_FB27_Pos (27U)
3588#define CAN_F6R1_FB27_Msk (0x1UL << CAN_F6R1_FB27_Pos)
3589#define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk
3590#define CAN_F6R1_FB28_Pos (28U)
3591#define CAN_F6R1_FB28_Msk (0x1UL << CAN_F6R1_FB28_Pos)
3592#define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk
3593#define CAN_F6R1_FB29_Pos (29U)
3594#define CAN_F6R1_FB29_Msk (0x1UL << CAN_F6R1_FB29_Pos)
3595#define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk
3596#define CAN_F6R1_FB30_Pos (30U)
3597#define CAN_F6R1_FB30_Msk (0x1UL << CAN_F6R1_FB30_Pos)
3598#define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk
3599#define CAN_F6R1_FB31_Pos (31U)
3600#define CAN_F6R1_FB31_Msk (0x1UL << CAN_F6R1_FB31_Pos)
3601#define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk
3603/******************* Bit definition for CAN_F7R1 register *******************/
3604#define CAN_F7R1_FB0_Pos (0U)
3605#define CAN_F7R1_FB0_Msk (0x1UL << CAN_F7R1_FB0_Pos)
3606#define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk
3607#define CAN_F7R1_FB1_Pos (1U)
3608#define CAN_F7R1_FB1_Msk (0x1UL << CAN_F7R1_FB1_Pos)
3609#define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk
3610#define CAN_F7R1_FB2_Pos (2U)
3611#define CAN_F7R1_FB2_Msk (0x1UL << CAN_F7R1_FB2_Pos)
3612#define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk
3613#define CAN_F7R1_FB3_Pos (3U)
3614#define CAN_F7R1_FB3_Msk (0x1UL << CAN_F7R1_FB3_Pos)
3615#define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk
3616#define CAN_F7R1_FB4_Pos (4U)
3617#define CAN_F7R1_FB4_Msk (0x1UL << CAN_F7R1_FB4_Pos)
3618#define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk
3619#define CAN_F7R1_FB5_Pos (5U)
3620#define CAN_F7R1_FB5_Msk (0x1UL << CAN_F7R1_FB5_Pos)
3621#define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk
3622#define CAN_F7R1_FB6_Pos (6U)
3623#define CAN_F7R1_FB6_Msk (0x1UL << CAN_F7R1_FB6_Pos)
3624#define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk
3625#define CAN_F7R1_FB7_Pos (7U)
3626#define CAN_F7R1_FB7_Msk (0x1UL << CAN_F7R1_FB7_Pos)
3627#define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk
3628#define CAN_F7R1_FB8_Pos (8U)
3629#define CAN_F7R1_FB8_Msk (0x1UL << CAN_F7R1_FB8_Pos)
3630#define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk
3631#define CAN_F7R1_FB9_Pos (9U)
3632#define CAN_F7R1_FB9_Msk (0x1UL << CAN_F7R1_FB9_Pos)
3633#define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk
3634#define CAN_F7R1_FB10_Pos (10U)
3635#define CAN_F7R1_FB10_Msk (0x1UL << CAN_F7R1_FB10_Pos)
3636#define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk
3637#define CAN_F7R1_FB11_Pos (11U)
3638#define CAN_F7R1_FB11_Msk (0x1UL << CAN_F7R1_FB11_Pos)
3639#define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk
3640#define CAN_F7R1_FB12_Pos (12U)
3641#define CAN_F7R1_FB12_Msk (0x1UL << CAN_F7R1_FB12_Pos)
3642#define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk
3643#define CAN_F7R1_FB13_Pos (13U)
3644#define CAN_F7R1_FB13_Msk (0x1UL << CAN_F7R1_FB13_Pos)
3645#define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk
3646#define CAN_F7R1_FB14_Pos (14U)
3647#define CAN_F7R1_FB14_Msk (0x1UL << CAN_F7R1_FB14_Pos)
3648#define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk
3649#define CAN_F7R1_FB15_Pos (15U)
3650#define CAN_F7R1_FB15_Msk (0x1UL << CAN_F7R1_FB15_Pos)
3651#define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk
3652#define CAN_F7R1_FB16_Pos (16U)
3653#define CAN_F7R1_FB16_Msk (0x1UL << CAN_F7R1_FB16_Pos)
3654#define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk
3655#define CAN_F7R1_FB17_Pos (17U)
3656#define CAN_F7R1_FB17_Msk (0x1UL << CAN_F7R1_FB17_Pos)
3657#define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk
3658#define CAN_F7R1_FB18_Pos (18U)
3659#define CAN_F7R1_FB18_Msk (0x1UL << CAN_F7R1_FB18_Pos)
3660#define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk
3661#define CAN_F7R1_FB19_Pos (19U)
3662#define CAN_F7R1_FB19_Msk (0x1UL << CAN_F7R1_FB19_Pos)
3663#define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk
3664#define CAN_F7R1_FB20_Pos (20U)
3665#define CAN_F7R1_FB20_Msk (0x1UL << CAN_F7R1_FB20_Pos)
3666#define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk
3667#define CAN_F7R1_FB21_Pos (21U)
3668#define CAN_F7R1_FB21_Msk (0x1UL << CAN_F7R1_FB21_Pos)
3669#define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk
3670#define CAN_F7R1_FB22_Pos (22U)
3671#define CAN_F7R1_FB22_Msk (0x1UL << CAN_F7R1_FB22_Pos)
3672#define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk
3673#define CAN_F7R1_FB23_Pos (23U)
3674#define CAN_F7R1_FB23_Msk (0x1UL << CAN_F7R1_FB23_Pos)
3675#define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk
3676#define CAN_F7R1_FB24_Pos (24U)
3677#define CAN_F7R1_FB24_Msk (0x1UL << CAN_F7R1_FB24_Pos)
3678#define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk
3679#define CAN_F7R1_FB25_Pos (25U)
3680#define CAN_F7R1_FB25_Msk (0x1UL << CAN_F7R1_FB25_Pos)
3681#define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk
3682#define CAN_F7R1_FB26_Pos (26U)
3683#define CAN_F7R1_FB26_Msk (0x1UL << CAN_F7R1_FB26_Pos)
3684#define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk
3685#define CAN_F7R1_FB27_Pos (27U)
3686#define CAN_F7R1_FB27_Msk (0x1UL << CAN_F7R1_FB27_Pos)
3687#define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk
3688#define CAN_F7R1_FB28_Pos (28U)
3689#define CAN_F7R1_FB28_Msk (0x1UL << CAN_F7R1_FB28_Pos)
3690#define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk
3691#define CAN_F7R1_FB29_Pos (29U)
3692#define CAN_F7R1_FB29_Msk (0x1UL << CAN_F7R1_FB29_Pos)
3693#define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk
3694#define CAN_F7R1_FB30_Pos (30U)
3695#define CAN_F7R1_FB30_Msk (0x1UL << CAN_F7R1_FB30_Pos)
3696#define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk
3697#define CAN_F7R1_FB31_Pos (31U)
3698#define CAN_F7R1_FB31_Msk (0x1UL << CAN_F7R1_FB31_Pos)
3699#define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk
3701/******************* Bit definition for CAN_F8R1 register *******************/
3702#define CAN_F8R1_FB0_Pos (0U)
3703#define CAN_F8R1_FB0_Msk (0x1UL << CAN_F8R1_FB0_Pos)
3704#define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk
3705#define CAN_F8R1_FB1_Pos (1U)
3706#define CAN_F8R1_FB1_Msk (0x1UL << CAN_F8R1_FB1_Pos)
3707#define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk
3708#define CAN_F8R1_FB2_Pos (2U)
3709#define CAN_F8R1_FB2_Msk (0x1UL << CAN_F8R1_FB2_Pos)
3710#define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk
3711#define CAN_F8R1_FB3_Pos (3U)
3712#define CAN_F8R1_FB3_Msk (0x1UL << CAN_F8R1_FB3_Pos)
3713#define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk
3714#define CAN_F8R1_FB4_Pos (4U)
3715#define CAN_F8R1_FB4_Msk (0x1UL << CAN_F8R1_FB4_Pos)
3716#define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk
3717#define CAN_F8R1_FB5_Pos (5U)
3718#define CAN_F8R1_FB5_Msk (0x1UL << CAN_F8R1_FB5_Pos)
3719#define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk
3720#define CAN_F8R1_FB6_Pos (6U)
3721#define CAN_F8R1_FB6_Msk (0x1UL << CAN_F8R1_FB6_Pos)
3722#define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk
3723#define CAN_F8R1_FB7_Pos (7U)
3724#define CAN_F8R1_FB7_Msk (0x1UL << CAN_F8R1_FB7_Pos)
3725#define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk
3726#define CAN_F8R1_FB8_Pos (8U)
3727#define CAN_F8R1_FB8_Msk (0x1UL << CAN_F8R1_FB8_Pos)
3728#define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk
3729#define CAN_F8R1_FB9_Pos (9U)
3730#define CAN_F8R1_FB9_Msk (0x1UL << CAN_F8R1_FB9_Pos)
3731#define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk
3732#define CAN_F8R1_FB10_Pos (10U)
3733#define CAN_F8R1_FB10_Msk (0x1UL << CAN_F8R1_FB10_Pos)
3734#define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk
3735#define CAN_F8R1_FB11_Pos (11U)
3736#define CAN_F8R1_FB11_Msk (0x1UL << CAN_F8R1_FB11_Pos)
3737#define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk
3738#define CAN_F8R1_FB12_Pos (12U)
3739#define CAN_F8R1_FB12_Msk (0x1UL << CAN_F8R1_FB12_Pos)
3740#define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk
3741#define CAN_F8R1_FB13_Pos (13U)
3742#define CAN_F8R1_FB13_Msk (0x1UL << CAN_F8R1_FB13_Pos)
3743#define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk
3744#define CAN_F8R1_FB14_Pos (14U)
3745#define CAN_F8R1_FB14_Msk (0x1UL << CAN_F8R1_FB14_Pos)
3746#define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk
3747#define CAN_F8R1_FB15_Pos (15U)
3748#define CAN_F8R1_FB15_Msk (0x1UL << CAN_F8R1_FB15_Pos)
3749#define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk
3750#define CAN_F8R1_FB16_Pos (16U)
3751#define CAN_F8R1_FB16_Msk (0x1UL << CAN_F8R1_FB16_Pos)
3752#define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk
3753#define CAN_F8R1_FB17_Pos (17U)
3754#define CAN_F8R1_FB17_Msk (0x1UL << CAN_F8R1_FB17_Pos)
3755#define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk
3756#define CAN_F8R1_FB18_Pos (18U)
3757#define CAN_F8R1_FB18_Msk (0x1UL << CAN_F8R1_FB18_Pos)
3758#define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk
3759#define CAN_F8R1_FB19_Pos (19U)
3760#define CAN_F8R1_FB19_Msk (0x1UL << CAN_F8R1_FB19_Pos)
3761#define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk
3762#define CAN_F8R1_FB20_Pos (20U)
3763#define CAN_F8R1_FB20_Msk (0x1UL << CAN_F8R1_FB20_Pos)
3764#define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk
3765#define CAN_F8R1_FB21_Pos (21U)
3766#define CAN_F8R1_FB21_Msk (0x1UL << CAN_F8R1_FB21_Pos)
3767#define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk
3768#define CAN_F8R1_FB22_Pos (22U)
3769#define CAN_F8R1_FB22_Msk (0x1UL << CAN_F8R1_FB22_Pos)
3770#define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk
3771#define CAN_F8R1_FB23_Pos (23U)
3772#define CAN_F8R1_FB23_Msk (0x1UL << CAN_F8R1_FB23_Pos)
3773#define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk
3774#define CAN_F8R1_FB24_Pos (24U)
3775#define CAN_F8R1_FB24_Msk (0x1UL << CAN_F8R1_FB24_Pos)
3776#define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk
3777#define CAN_F8R1_FB25_Pos (25U)
3778#define CAN_F8R1_FB25_Msk (0x1UL << CAN_F8R1_FB25_Pos)
3779#define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk
3780#define CAN_F8R1_FB26_Pos (26U)
3781#define CAN_F8R1_FB26_Msk (0x1UL << CAN_F8R1_FB26_Pos)
3782#define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk
3783#define CAN_F8R1_FB27_Pos (27U)
3784#define CAN_F8R1_FB27_Msk (0x1UL << CAN_F8R1_FB27_Pos)
3785#define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk
3786#define CAN_F8R1_FB28_Pos (28U)
3787#define CAN_F8R1_FB28_Msk (0x1UL << CAN_F8R1_FB28_Pos)
3788#define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk
3789#define CAN_F8R1_FB29_Pos (29U)
3790#define CAN_F8R1_FB29_Msk (0x1UL << CAN_F8R1_FB29_Pos)
3791#define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk
3792#define CAN_F8R1_FB30_Pos (30U)
3793#define CAN_F8R1_FB30_Msk (0x1UL << CAN_F8R1_FB30_Pos)
3794#define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk
3795#define CAN_F8R1_FB31_Pos (31U)
3796#define CAN_F8R1_FB31_Msk (0x1UL << CAN_F8R1_FB31_Pos)
3797#define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk
3799/******************* Bit definition for CAN_F9R1 register *******************/
3800#define CAN_F9R1_FB0_Pos (0U)
3801#define CAN_F9R1_FB0_Msk (0x1UL << CAN_F9R1_FB0_Pos)
3802#define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk
3803#define CAN_F9R1_FB1_Pos (1U)
3804#define CAN_F9R1_FB1_Msk (0x1UL << CAN_F9R1_FB1_Pos)
3805#define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk
3806#define CAN_F9R1_FB2_Pos (2U)
3807#define CAN_F9R1_FB2_Msk (0x1UL << CAN_F9R1_FB2_Pos)
3808#define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk
3809#define CAN_F9R1_FB3_Pos (3U)
3810#define CAN_F9R1_FB3_Msk (0x1UL << CAN_F9R1_FB3_Pos)
3811#define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk
3812#define CAN_F9R1_FB4_Pos (4U)
3813#define CAN_F9R1_FB4_Msk (0x1UL << CAN_F9R1_FB4_Pos)
3814#define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk
3815#define CAN_F9R1_FB5_Pos (5U)
3816#define CAN_F9R1_FB5_Msk (0x1UL << CAN_F9R1_FB5_Pos)
3817#define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk
3818#define CAN_F9R1_FB6_Pos (6U)
3819#define CAN_F9R1_FB6_Msk (0x1UL << CAN_F9R1_FB6_Pos)
3820#define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk
3821#define CAN_F9R1_FB7_Pos (7U)
3822#define CAN_F9R1_FB7_Msk (0x1UL << CAN_F9R1_FB7_Pos)
3823#define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk
3824#define CAN_F9R1_FB8_Pos (8U)
3825#define CAN_F9R1_FB8_Msk (0x1UL << CAN_F9R1_FB8_Pos)
3826#define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk
3827#define CAN_F9R1_FB9_Pos (9U)
3828#define CAN_F9R1_FB9_Msk (0x1UL << CAN_F9R1_FB9_Pos)
3829#define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk
3830#define CAN_F9R1_FB10_Pos (10U)
3831#define CAN_F9R1_FB10_Msk (0x1UL << CAN_F9R1_FB10_Pos)
3832#define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk
3833#define CAN_F9R1_FB11_Pos (11U)
3834#define CAN_F9R1_FB11_Msk (0x1UL << CAN_F9R1_FB11_Pos)
3835#define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk
3836#define CAN_F9R1_FB12_Pos (12U)
3837#define CAN_F9R1_FB12_Msk (0x1UL << CAN_F9R1_FB12_Pos)
3838#define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk
3839#define CAN_F9R1_FB13_Pos (13U)
3840#define CAN_F9R1_FB13_Msk (0x1UL << CAN_F9R1_FB13_Pos)
3841#define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk
3842#define CAN_F9R1_FB14_Pos (14U)
3843#define CAN_F9R1_FB14_Msk (0x1UL << CAN_F9R1_FB14_Pos)
3844#define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk
3845#define CAN_F9R1_FB15_Pos (15U)
3846#define CAN_F9R1_FB15_Msk (0x1UL << CAN_F9R1_FB15_Pos)
3847#define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk
3848#define CAN_F9R1_FB16_Pos (16U)
3849#define CAN_F9R1_FB16_Msk (0x1UL << CAN_F9R1_FB16_Pos)
3850#define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk
3851#define CAN_F9R1_FB17_Pos (17U)
3852#define CAN_F9R1_FB17_Msk (0x1UL << CAN_F9R1_FB17_Pos)
3853#define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk
3854#define CAN_F9R1_FB18_Pos (18U)
3855#define CAN_F9R1_FB18_Msk (0x1UL << CAN_F9R1_FB18_Pos)
3856#define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk
3857#define CAN_F9R1_FB19_Pos (19U)
3858#define CAN_F9R1_FB19_Msk (0x1UL << CAN_F9R1_FB19_Pos)
3859#define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk
3860#define CAN_F9R1_FB20_Pos (20U)
3861#define CAN_F9R1_FB20_Msk (0x1UL << CAN_F9R1_FB20_Pos)
3862#define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk
3863#define CAN_F9R1_FB21_Pos (21U)
3864#define CAN_F9R1_FB21_Msk (0x1UL << CAN_F9R1_FB21_Pos)
3865#define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk
3866#define CAN_F9R1_FB22_Pos (22U)
3867#define CAN_F9R1_FB22_Msk (0x1UL << CAN_F9R1_FB22_Pos)
3868#define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk
3869#define CAN_F9R1_FB23_Pos (23U)
3870#define CAN_F9R1_FB23_Msk (0x1UL << CAN_F9R1_FB23_Pos)
3871#define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk
3872#define CAN_F9R1_FB24_Pos (24U)
3873#define CAN_F9R1_FB24_Msk (0x1UL << CAN_F9R1_FB24_Pos)
3874#define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk
3875#define CAN_F9R1_FB25_Pos (25U)
3876#define CAN_F9R1_FB25_Msk (0x1UL << CAN_F9R1_FB25_Pos)
3877#define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk
3878#define CAN_F9R1_FB26_Pos (26U)
3879#define CAN_F9R1_FB26_Msk (0x1UL << CAN_F9R1_FB26_Pos)
3880#define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk
3881#define CAN_F9R1_FB27_Pos (27U)
3882#define CAN_F9R1_FB27_Msk (0x1UL << CAN_F9R1_FB27_Pos)
3883#define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk
3884#define CAN_F9R1_FB28_Pos (28U)
3885#define CAN_F9R1_FB28_Msk (0x1UL << CAN_F9R1_FB28_Pos)
3886#define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk
3887#define CAN_F9R1_FB29_Pos (29U)
3888#define CAN_F9R1_FB29_Msk (0x1UL << CAN_F9R1_FB29_Pos)
3889#define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk
3890#define CAN_F9R1_FB30_Pos (30U)
3891#define CAN_F9R1_FB30_Msk (0x1UL << CAN_F9R1_FB30_Pos)
3892#define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk
3893#define CAN_F9R1_FB31_Pos (31U)
3894#define CAN_F9R1_FB31_Msk (0x1UL << CAN_F9R1_FB31_Pos)
3895#define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk
3897/******************* Bit definition for CAN_F10R1 register ******************/
3898#define CAN_F10R1_FB0_Pos (0U)
3899#define CAN_F10R1_FB0_Msk (0x1UL << CAN_F10R1_FB0_Pos)
3900#define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk
3901#define CAN_F10R1_FB1_Pos (1U)
3902#define CAN_F10R1_FB1_Msk (0x1UL << CAN_F10R1_FB1_Pos)
3903#define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk
3904#define CAN_F10R1_FB2_Pos (2U)
3905#define CAN_F10R1_FB2_Msk (0x1UL << CAN_F10R1_FB2_Pos)
3906#define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk
3907#define CAN_F10R1_FB3_Pos (3U)
3908#define CAN_F10R1_FB3_Msk (0x1UL << CAN_F10R1_FB3_Pos)
3909#define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk
3910#define CAN_F10R1_FB4_Pos (4U)
3911#define CAN_F10R1_FB4_Msk (0x1UL << CAN_F10R1_FB4_Pos)
3912#define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk
3913#define CAN_F10R1_FB5_Pos (5U)
3914#define CAN_F10R1_FB5_Msk (0x1UL << CAN_F10R1_FB5_Pos)
3915#define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk
3916#define CAN_F10R1_FB6_Pos (6U)
3917#define CAN_F10R1_FB6_Msk (0x1UL << CAN_F10R1_FB6_Pos)
3918#define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk
3919#define CAN_F10R1_FB7_Pos (7U)
3920#define CAN_F10R1_FB7_Msk (0x1UL << CAN_F10R1_FB7_Pos)
3921#define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk
3922#define CAN_F10R1_FB8_Pos (8U)
3923#define CAN_F10R1_FB8_Msk (0x1UL << CAN_F10R1_FB8_Pos)
3924#define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk
3925#define CAN_F10R1_FB9_Pos (9U)
3926#define CAN_F10R1_FB9_Msk (0x1UL << CAN_F10R1_FB9_Pos)
3927#define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk
3928#define CAN_F10R1_FB10_Pos (10U)
3929#define CAN_F10R1_FB10_Msk (0x1UL << CAN_F10R1_FB10_Pos)
3930#define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk
3931#define CAN_F10R1_FB11_Pos (11U)
3932#define CAN_F10R1_FB11_Msk (0x1UL << CAN_F10R1_FB11_Pos)
3933#define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk
3934#define CAN_F10R1_FB12_Pos (12U)
3935#define CAN_F10R1_FB12_Msk (0x1UL << CAN_F10R1_FB12_Pos)
3936#define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk
3937#define CAN_F10R1_FB13_Pos (13U)
3938#define CAN_F10R1_FB13_Msk (0x1UL << CAN_F10R1_FB13_Pos)
3939#define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk
3940#define CAN_F10R1_FB14_Pos (14U)
3941#define CAN_F10R1_FB14_Msk (0x1UL << CAN_F10R1_FB14_Pos)
3942#define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk
3943#define CAN_F10R1_FB15_Pos (15U)
3944#define CAN_F10R1_FB15_Msk (0x1UL << CAN_F10R1_FB15_Pos)
3945#define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk
3946#define CAN_F10R1_FB16_Pos (16U)
3947#define CAN_F10R1_FB16_Msk (0x1UL << CAN_F10R1_FB16_Pos)
3948#define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk
3949#define CAN_F10R1_FB17_Pos (17U)
3950#define CAN_F10R1_FB17_Msk (0x1UL << CAN_F10R1_FB17_Pos)
3951#define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk
3952#define CAN_F10R1_FB18_Pos (18U)
3953#define CAN_F10R1_FB18_Msk (0x1UL << CAN_F10R1_FB18_Pos)
3954#define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk
3955#define CAN_F10R1_FB19_Pos (19U)
3956#define CAN_F10R1_FB19_Msk (0x1UL << CAN_F10R1_FB19_Pos)
3957#define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk
3958#define CAN_F10R1_FB20_Pos (20U)
3959#define CAN_F10R1_FB20_Msk (0x1UL << CAN_F10R1_FB20_Pos)
3960#define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk
3961#define CAN_F10R1_FB21_Pos (21U)
3962#define CAN_F10R1_FB21_Msk (0x1UL << CAN_F10R1_FB21_Pos)
3963#define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk
3964#define CAN_F10R1_FB22_Pos (22U)
3965#define CAN_F10R1_FB22_Msk (0x1UL << CAN_F10R1_FB22_Pos)
3966#define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk
3967#define CAN_F10R1_FB23_Pos (23U)
3968#define CAN_F10R1_FB23_Msk (0x1UL << CAN_F10R1_FB23_Pos)
3969#define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk
3970#define CAN_F10R1_FB24_Pos (24U)
3971#define CAN_F10R1_FB24_Msk (0x1UL << CAN_F10R1_FB24_Pos)
3972#define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk
3973#define CAN_F10R1_FB25_Pos (25U)
3974#define CAN_F10R1_FB25_Msk (0x1UL << CAN_F10R1_FB25_Pos)
3975#define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk
3976#define CAN_F10R1_FB26_Pos (26U)
3977#define CAN_F10R1_FB26_Msk (0x1UL << CAN_F10R1_FB26_Pos)
3978#define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk
3979#define CAN_F10R1_FB27_Pos (27U)
3980#define CAN_F10R1_FB27_Msk (0x1UL << CAN_F10R1_FB27_Pos)
3981#define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk
3982#define CAN_F10R1_FB28_Pos (28U)
3983#define CAN_F10R1_FB28_Msk (0x1UL << CAN_F10R1_FB28_Pos)
3984#define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk
3985#define CAN_F10R1_FB29_Pos (29U)
3986#define CAN_F10R1_FB29_Msk (0x1UL << CAN_F10R1_FB29_Pos)
3987#define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk
3988#define CAN_F10R1_FB30_Pos (30U)
3989#define CAN_F10R1_FB30_Msk (0x1UL << CAN_F10R1_FB30_Pos)
3990#define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk
3991#define CAN_F10R1_FB31_Pos (31U)
3992#define CAN_F10R1_FB31_Msk (0x1UL << CAN_F10R1_FB31_Pos)
3993#define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk
3995/******************* Bit definition for CAN_F11R1 register ******************/
3996#define CAN_F11R1_FB0_Pos (0U)
3997#define CAN_F11R1_FB0_Msk (0x1UL << CAN_F11R1_FB0_Pos)
3998#define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk
3999#define CAN_F11R1_FB1_Pos (1U)
4000#define CAN_F11R1_FB1_Msk (0x1UL << CAN_F11R1_FB1_Pos)
4001#define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk
4002#define CAN_F11R1_FB2_Pos (2U)
4003#define CAN_F11R1_FB2_Msk (0x1UL << CAN_F11R1_FB2_Pos)
4004#define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk
4005#define CAN_F11R1_FB3_Pos (3U)
4006#define CAN_F11R1_FB3_Msk (0x1UL << CAN_F11R1_FB3_Pos)
4007#define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk
4008#define CAN_F11R1_FB4_Pos (4U)
4009#define CAN_F11R1_FB4_Msk (0x1UL << CAN_F11R1_FB4_Pos)
4010#define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk
4011#define CAN_F11R1_FB5_Pos (5U)
4012#define CAN_F11R1_FB5_Msk (0x1UL << CAN_F11R1_FB5_Pos)
4013#define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk
4014#define CAN_F11R1_FB6_Pos (6U)
4015#define CAN_F11R1_FB6_Msk (0x1UL << CAN_F11R1_FB6_Pos)
4016#define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk
4017#define CAN_F11R1_FB7_Pos (7U)
4018#define CAN_F11R1_FB7_Msk (0x1UL << CAN_F11R1_FB7_Pos)
4019#define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk
4020#define CAN_F11R1_FB8_Pos (8U)
4021#define CAN_F11R1_FB8_Msk (0x1UL << CAN_F11R1_FB8_Pos)
4022#define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk
4023#define CAN_F11R1_FB9_Pos (9U)
4024#define CAN_F11R1_FB9_Msk (0x1UL << CAN_F11R1_FB9_Pos)
4025#define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk
4026#define CAN_F11R1_FB10_Pos (10U)
4027#define CAN_F11R1_FB10_Msk (0x1UL << CAN_F11R1_FB10_Pos)
4028#define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk
4029#define CAN_F11R1_FB11_Pos (11U)
4030#define CAN_F11R1_FB11_Msk (0x1UL << CAN_F11R1_FB11_Pos)
4031#define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk
4032#define CAN_F11R1_FB12_Pos (12U)
4033#define CAN_F11R1_FB12_Msk (0x1UL << CAN_F11R1_FB12_Pos)
4034#define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk
4035#define CAN_F11R1_FB13_Pos (13U)
4036#define CAN_F11R1_FB13_Msk (0x1UL << CAN_F11R1_FB13_Pos)
4037#define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk
4038#define CAN_F11R1_FB14_Pos (14U)
4039#define CAN_F11R1_FB14_Msk (0x1UL << CAN_F11R1_FB14_Pos)
4040#define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk
4041#define CAN_F11R1_FB15_Pos (15U)
4042#define CAN_F11R1_FB15_Msk (0x1UL << CAN_F11R1_FB15_Pos)
4043#define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk
4044#define CAN_F11R1_FB16_Pos (16U)
4045#define CAN_F11R1_FB16_Msk (0x1UL << CAN_F11R1_FB16_Pos)
4046#define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk
4047#define CAN_F11R1_FB17_Pos (17U)
4048#define CAN_F11R1_FB17_Msk (0x1UL << CAN_F11R1_FB17_Pos)
4049#define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk
4050#define CAN_F11R1_FB18_Pos (18U)
4051#define CAN_F11R1_FB18_Msk (0x1UL << CAN_F11R1_FB18_Pos)
4052#define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk
4053#define CAN_F11R1_FB19_Pos (19U)
4054#define CAN_F11R1_FB19_Msk (0x1UL << CAN_F11R1_FB19_Pos)
4055#define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk
4056#define CAN_F11R1_FB20_Pos (20U)
4057#define CAN_F11R1_FB20_Msk (0x1UL << CAN_F11R1_FB20_Pos)
4058#define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk
4059#define CAN_F11R1_FB21_Pos (21U)
4060#define CAN_F11R1_FB21_Msk (0x1UL << CAN_F11R1_FB21_Pos)
4061#define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk
4062#define CAN_F11R1_FB22_Pos (22U)
4063#define CAN_F11R1_FB22_Msk (0x1UL << CAN_F11R1_FB22_Pos)
4064#define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk
4065#define CAN_F11R1_FB23_Pos (23U)
4066#define CAN_F11R1_FB23_Msk (0x1UL << CAN_F11R1_FB23_Pos)
4067#define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk
4068#define CAN_F11R1_FB24_Pos (24U)
4069#define CAN_F11R1_FB24_Msk (0x1UL << CAN_F11R1_FB24_Pos)
4070#define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk
4071#define CAN_F11R1_FB25_Pos (25U)
4072#define CAN_F11R1_FB25_Msk (0x1UL << CAN_F11R1_FB25_Pos)
4073#define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk
4074#define CAN_F11R1_FB26_Pos (26U)
4075#define CAN_F11R1_FB26_Msk (0x1UL << CAN_F11R1_FB26_Pos)
4076#define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk
4077#define CAN_F11R1_FB27_Pos (27U)
4078#define CAN_F11R1_FB27_Msk (0x1UL << CAN_F11R1_FB27_Pos)
4079#define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk
4080#define CAN_F11R1_FB28_Pos (28U)
4081#define CAN_F11R1_FB28_Msk (0x1UL << CAN_F11R1_FB28_Pos)
4082#define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk
4083#define CAN_F11R1_FB29_Pos (29U)
4084#define CAN_F11R1_FB29_Msk (0x1UL << CAN_F11R1_FB29_Pos)
4085#define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk
4086#define CAN_F11R1_FB30_Pos (30U)
4087#define CAN_F11R1_FB30_Msk (0x1UL << CAN_F11R1_FB30_Pos)
4088#define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk
4089#define CAN_F11R1_FB31_Pos (31U)
4090#define CAN_F11R1_FB31_Msk (0x1UL << CAN_F11R1_FB31_Pos)
4091#define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk
4093/******************* Bit definition for CAN_F12R1 register ******************/
4094#define CAN_F12R1_FB0_Pos (0U)
4095#define CAN_F12R1_FB0_Msk (0x1UL << CAN_F12R1_FB0_Pos)
4096#define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk
4097#define CAN_F12R1_FB1_Pos (1U)
4098#define CAN_F12R1_FB1_Msk (0x1UL << CAN_F12R1_FB1_Pos)
4099#define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk
4100#define CAN_F12R1_FB2_Pos (2U)
4101#define CAN_F12R1_FB2_Msk (0x1UL << CAN_F12R1_FB2_Pos)
4102#define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk
4103#define CAN_F12R1_FB3_Pos (3U)
4104#define CAN_F12R1_FB3_Msk (0x1UL << CAN_F12R1_FB3_Pos)
4105#define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk
4106#define CAN_F12R1_FB4_Pos (4U)
4107#define CAN_F12R1_FB4_Msk (0x1UL << CAN_F12R1_FB4_Pos)
4108#define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk
4109#define CAN_F12R1_FB5_Pos (5U)
4110#define CAN_F12R1_FB5_Msk (0x1UL << CAN_F12R1_FB5_Pos)
4111#define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk
4112#define CAN_F12R1_FB6_Pos (6U)
4113#define CAN_F12R1_FB6_Msk (0x1UL << CAN_F12R1_FB6_Pos)
4114#define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk
4115#define CAN_F12R1_FB7_Pos (7U)
4116#define CAN_F12R1_FB7_Msk (0x1UL << CAN_F12R1_FB7_Pos)
4117#define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk
4118#define CAN_F12R1_FB8_Pos (8U)
4119#define CAN_F12R1_FB8_Msk (0x1UL << CAN_F12R1_FB8_Pos)
4120#define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk
4121#define CAN_F12R1_FB9_Pos (9U)
4122#define CAN_F12R1_FB9_Msk (0x1UL << CAN_F12R1_FB9_Pos)
4123#define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk
4124#define CAN_F12R1_FB10_Pos (10U)
4125#define CAN_F12R1_FB10_Msk (0x1UL << CAN_F12R1_FB10_Pos)
4126#define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk
4127#define CAN_F12R1_FB11_Pos (11U)
4128#define CAN_F12R1_FB11_Msk (0x1UL << CAN_F12R1_FB11_Pos)
4129#define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk
4130#define CAN_F12R1_FB12_Pos (12U)
4131#define CAN_F12R1_FB12_Msk (0x1UL << CAN_F12R1_FB12_Pos)
4132#define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk
4133#define CAN_F12R1_FB13_Pos (13U)
4134#define CAN_F12R1_FB13_Msk (0x1UL << CAN_F12R1_FB13_Pos)
4135#define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk
4136#define CAN_F12R1_FB14_Pos (14U)
4137#define CAN_F12R1_FB14_Msk (0x1UL << CAN_F12R1_FB14_Pos)
4138#define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk
4139#define CAN_F12R1_FB15_Pos (15U)
4140#define CAN_F12R1_FB15_Msk (0x1UL << CAN_F12R1_FB15_Pos)
4141#define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk
4142#define CAN_F12R1_FB16_Pos (16U)
4143#define CAN_F12R1_FB16_Msk (0x1UL << CAN_F12R1_FB16_Pos)
4144#define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk
4145#define CAN_F12R1_FB17_Pos (17U)
4146#define CAN_F12R1_FB17_Msk (0x1UL << CAN_F12R1_FB17_Pos)
4147#define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk
4148#define CAN_F12R1_FB18_Pos (18U)
4149#define CAN_F12R1_FB18_Msk (0x1UL << CAN_F12R1_FB18_Pos)
4150#define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk
4151#define CAN_F12R1_FB19_Pos (19U)
4152#define CAN_F12R1_FB19_Msk (0x1UL << CAN_F12R1_FB19_Pos)
4153#define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk
4154#define CAN_F12R1_FB20_Pos (20U)
4155#define CAN_F12R1_FB20_Msk (0x1UL << CAN_F12R1_FB20_Pos)
4156#define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk
4157#define CAN_F12R1_FB21_Pos (21U)
4158#define CAN_F12R1_FB21_Msk (0x1UL << CAN_F12R1_FB21_Pos)
4159#define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk
4160#define CAN_F12R1_FB22_Pos (22U)
4161#define CAN_F12R1_FB22_Msk (0x1UL << CAN_F12R1_FB22_Pos)
4162#define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk
4163#define CAN_F12R1_FB23_Pos (23U)
4164#define CAN_F12R1_FB23_Msk (0x1UL << CAN_F12R1_FB23_Pos)
4165#define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk
4166#define CAN_F12R1_FB24_Pos (24U)
4167#define CAN_F12R1_FB24_Msk (0x1UL << CAN_F12R1_FB24_Pos)
4168#define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk
4169#define CAN_F12R1_FB25_Pos (25U)
4170#define CAN_F12R1_FB25_Msk (0x1UL << CAN_F12R1_FB25_Pos)
4171#define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk
4172#define CAN_F12R1_FB26_Pos (26U)
4173#define CAN_F12R1_FB26_Msk (0x1UL << CAN_F12R1_FB26_Pos)
4174#define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk
4175#define CAN_F12R1_FB27_Pos (27U)
4176#define CAN_F12R1_FB27_Msk (0x1UL << CAN_F12R1_FB27_Pos)
4177#define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk
4178#define CAN_F12R1_FB28_Pos (28U)
4179#define CAN_F12R1_FB28_Msk (0x1UL << CAN_F12R1_FB28_Pos)
4180#define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk
4181#define CAN_F12R1_FB29_Pos (29U)
4182#define CAN_F12R1_FB29_Msk (0x1UL << CAN_F12R1_FB29_Pos)
4183#define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk
4184#define CAN_F12R1_FB30_Pos (30U)
4185#define CAN_F12R1_FB30_Msk (0x1UL << CAN_F12R1_FB30_Pos)
4186#define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk
4187#define CAN_F12R1_FB31_Pos (31U)
4188#define CAN_F12R1_FB31_Msk (0x1UL << CAN_F12R1_FB31_Pos)
4189#define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk
4191/******************* Bit definition for CAN_F13R1 register ******************/
4192#define CAN_F13R1_FB0_Pos (0U)
4193#define CAN_F13R1_FB0_Msk (0x1UL << CAN_F13R1_FB0_Pos)
4194#define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk
4195#define CAN_F13R1_FB1_Pos (1U)
4196#define CAN_F13R1_FB1_Msk (0x1UL << CAN_F13R1_FB1_Pos)
4197#define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk
4198#define CAN_F13R1_FB2_Pos (2U)
4199#define CAN_F13R1_FB2_Msk (0x1UL << CAN_F13R1_FB2_Pos)
4200#define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk
4201#define CAN_F13R1_FB3_Pos (3U)
4202#define CAN_F13R1_FB3_Msk (0x1UL << CAN_F13R1_FB3_Pos)
4203#define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk
4204#define CAN_F13R1_FB4_Pos (4U)
4205#define CAN_F13R1_FB4_Msk (0x1UL << CAN_F13R1_FB4_Pos)
4206#define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk
4207#define CAN_F13R1_FB5_Pos (5U)
4208#define CAN_F13R1_FB5_Msk (0x1UL << CAN_F13R1_FB5_Pos)
4209#define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk
4210#define CAN_F13R1_FB6_Pos (6U)
4211#define CAN_F13R1_FB6_Msk (0x1UL << CAN_F13R1_FB6_Pos)
4212#define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk
4213#define CAN_F13R1_FB7_Pos (7U)
4214#define CAN_F13R1_FB7_Msk (0x1UL << CAN_F13R1_FB7_Pos)
4215#define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk
4216#define CAN_F13R1_FB8_Pos (8U)
4217#define CAN_F13R1_FB8_Msk (0x1UL << CAN_F13R1_FB8_Pos)
4218#define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk
4219#define CAN_F13R1_FB9_Pos (9U)
4220#define CAN_F13R1_FB9_Msk (0x1UL << CAN_F13R1_FB9_Pos)
4221#define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk
4222#define CAN_F13R1_FB10_Pos (10U)
4223#define CAN_F13R1_FB10_Msk (0x1UL << CAN_F13R1_FB10_Pos)
4224#define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk
4225#define CAN_F13R1_FB11_Pos (11U)
4226#define CAN_F13R1_FB11_Msk (0x1UL << CAN_F13R1_FB11_Pos)
4227#define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk
4228#define CAN_F13R1_FB12_Pos (12U)
4229#define CAN_F13R1_FB12_Msk (0x1UL << CAN_F13R1_FB12_Pos)
4230#define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk
4231#define CAN_F13R1_FB13_Pos (13U)
4232#define CAN_F13R1_FB13_Msk (0x1UL << CAN_F13R1_FB13_Pos)
4233#define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk
4234#define CAN_F13R1_FB14_Pos (14U)
4235#define CAN_F13R1_FB14_Msk (0x1UL << CAN_F13R1_FB14_Pos)
4236#define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk
4237#define CAN_F13R1_FB15_Pos (15U)
4238#define CAN_F13R1_FB15_Msk (0x1UL << CAN_F13R1_FB15_Pos)
4239#define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk
4240#define CAN_F13R1_FB16_Pos (16U)
4241#define CAN_F13R1_FB16_Msk (0x1UL << CAN_F13R1_FB16_Pos)
4242#define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk
4243#define CAN_F13R1_FB17_Pos (17U)
4244#define CAN_F13R1_FB17_Msk (0x1UL << CAN_F13R1_FB17_Pos)
4245#define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk
4246#define CAN_F13R1_FB18_Pos (18U)
4247#define CAN_F13R1_FB18_Msk (0x1UL << CAN_F13R1_FB18_Pos)
4248#define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk
4249#define CAN_F13R1_FB19_Pos (19U)
4250#define CAN_F13R1_FB19_Msk (0x1UL << CAN_F13R1_FB19_Pos)
4251#define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk
4252#define CAN_F13R1_FB20_Pos (20U)
4253#define CAN_F13R1_FB20_Msk (0x1UL << CAN_F13R1_FB20_Pos)
4254#define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk
4255#define CAN_F13R1_FB21_Pos (21U)
4256#define CAN_F13R1_FB21_Msk (0x1UL << CAN_F13R1_FB21_Pos)
4257#define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk
4258#define CAN_F13R1_FB22_Pos (22U)
4259#define CAN_F13R1_FB22_Msk (0x1UL << CAN_F13R1_FB22_Pos)
4260#define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk
4261#define CAN_F13R1_FB23_Pos (23U)
4262#define CAN_F13R1_FB23_Msk (0x1UL << CAN_F13R1_FB23_Pos)
4263#define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk
4264#define CAN_F13R1_FB24_Pos (24U)
4265#define CAN_F13R1_FB24_Msk (0x1UL << CAN_F13R1_FB24_Pos)
4266#define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk
4267#define CAN_F13R1_FB25_Pos (25U)
4268#define CAN_F13R1_FB25_Msk (0x1UL << CAN_F13R1_FB25_Pos)
4269#define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk
4270#define CAN_F13R1_FB26_Pos (26U)
4271#define CAN_F13R1_FB26_Msk (0x1UL << CAN_F13R1_FB26_Pos)
4272#define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk
4273#define CAN_F13R1_FB27_Pos (27U)
4274#define CAN_F13R1_FB27_Msk (0x1UL << CAN_F13R1_FB27_Pos)
4275#define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk
4276#define CAN_F13R1_FB28_Pos (28U)
4277#define CAN_F13R1_FB28_Msk (0x1UL << CAN_F13R1_FB28_Pos)
4278#define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk
4279#define CAN_F13R1_FB29_Pos (29U)
4280#define CAN_F13R1_FB29_Msk (0x1UL << CAN_F13R1_FB29_Pos)
4281#define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk
4282#define CAN_F13R1_FB30_Pos (30U)
4283#define CAN_F13R1_FB30_Msk (0x1UL << CAN_F13R1_FB30_Pos)
4284#define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk
4285#define CAN_F13R1_FB31_Pos (31U)
4286#define CAN_F13R1_FB31_Msk (0x1UL << CAN_F13R1_FB31_Pos)
4287#define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk
4289/******************* Bit definition for CAN_F0R2 register *******************/
4290#define CAN_F0R2_FB0_Pos (0U)
4291#define CAN_F0R2_FB0_Msk (0x1UL << CAN_F0R2_FB0_Pos)
4292#define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk
4293#define CAN_F0R2_FB1_Pos (1U)
4294#define CAN_F0R2_FB1_Msk (0x1UL << CAN_F0R2_FB1_Pos)
4295#define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk
4296#define CAN_F0R2_FB2_Pos (2U)
4297#define CAN_F0R2_FB2_Msk (0x1UL << CAN_F0R2_FB2_Pos)
4298#define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk
4299#define CAN_F0R2_FB3_Pos (3U)
4300#define CAN_F0R2_FB3_Msk (0x1UL << CAN_F0R2_FB3_Pos)
4301#define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk
4302#define CAN_F0R2_FB4_Pos (4U)
4303#define CAN_F0R2_FB4_Msk (0x1UL << CAN_F0R2_FB4_Pos)
4304#define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk
4305#define CAN_F0R2_FB5_Pos (5U)
4306#define CAN_F0R2_FB5_Msk (0x1UL << CAN_F0R2_FB5_Pos)
4307#define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk
4308#define CAN_F0R2_FB6_Pos (6U)
4309#define CAN_F0R2_FB6_Msk (0x1UL << CAN_F0R2_FB6_Pos)
4310#define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk
4311#define CAN_F0R2_FB7_Pos (7U)
4312#define CAN_F0R2_FB7_Msk (0x1UL << CAN_F0R2_FB7_Pos)
4313#define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk
4314#define CAN_F0R2_FB8_Pos (8U)
4315#define CAN_F0R2_FB8_Msk (0x1UL << CAN_F0R2_FB8_Pos)
4316#define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk
4317#define CAN_F0R2_FB9_Pos (9U)
4318#define CAN_F0R2_FB9_Msk (0x1UL << CAN_F0R2_FB9_Pos)
4319#define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk
4320#define CAN_F0R2_FB10_Pos (10U)
4321#define CAN_F0R2_FB10_Msk (0x1UL << CAN_F0R2_FB10_Pos)
4322#define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk
4323#define CAN_F0R2_FB11_Pos (11U)
4324#define CAN_F0R2_FB11_Msk (0x1UL << CAN_F0R2_FB11_Pos)
4325#define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk
4326#define CAN_F0R2_FB12_Pos (12U)
4327#define CAN_F0R2_FB12_Msk (0x1UL << CAN_F0R2_FB12_Pos)
4328#define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk
4329#define CAN_F0R2_FB13_Pos (13U)
4330#define CAN_F0R2_FB13_Msk (0x1UL << CAN_F0R2_FB13_Pos)
4331#define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk
4332#define CAN_F0R2_FB14_Pos (14U)
4333#define CAN_F0R2_FB14_Msk (0x1UL << CAN_F0R2_FB14_Pos)
4334#define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk
4335#define CAN_F0R2_FB15_Pos (15U)
4336#define CAN_F0R2_FB15_Msk (0x1UL << CAN_F0R2_FB15_Pos)
4337#define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk
4338#define CAN_F0R2_FB16_Pos (16U)
4339#define CAN_F0R2_FB16_Msk (0x1UL << CAN_F0R2_FB16_Pos)
4340#define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk
4341#define CAN_F0R2_FB17_Pos (17U)
4342#define CAN_F0R2_FB17_Msk (0x1UL << CAN_F0R2_FB17_Pos)
4343#define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk
4344#define CAN_F0R2_FB18_Pos (18U)
4345#define CAN_F0R2_FB18_Msk (0x1UL << CAN_F0R2_FB18_Pos)
4346#define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk
4347#define CAN_F0R2_FB19_Pos (19U)
4348#define CAN_F0R2_FB19_Msk (0x1UL << CAN_F0R2_FB19_Pos)
4349#define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk
4350#define CAN_F0R2_FB20_Pos (20U)
4351#define CAN_F0R2_FB20_Msk (0x1UL << CAN_F0R2_FB20_Pos)
4352#define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk
4353#define CAN_F0R2_FB21_Pos (21U)
4354#define CAN_F0R2_FB21_Msk (0x1UL << CAN_F0R2_FB21_Pos)
4355#define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk
4356#define CAN_F0R2_FB22_Pos (22U)
4357#define CAN_F0R2_FB22_Msk (0x1UL << CAN_F0R2_FB22_Pos)
4358#define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk
4359#define CAN_F0R2_FB23_Pos (23U)
4360#define CAN_F0R2_FB23_Msk (0x1UL << CAN_F0R2_FB23_Pos)
4361#define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk
4362#define CAN_F0R2_FB24_Pos (24U)
4363#define CAN_F0R2_FB24_Msk (0x1UL << CAN_F0R2_FB24_Pos)
4364#define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk
4365#define CAN_F0R2_FB25_Pos (25U)
4366#define CAN_F0R2_FB25_Msk (0x1UL << CAN_F0R2_FB25_Pos)
4367#define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk
4368#define CAN_F0R2_FB26_Pos (26U)
4369#define CAN_F0R2_FB26_Msk (0x1UL << CAN_F0R2_FB26_Pos)
4370#define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk
4371#define CAN_F0R2_FB27_Pos (27U)
4372#define CAN_F0R2_FB27_Msk (0x1UL << CAN_F0R2_FB27_Pos)
4373#define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk
4374#define CAN_F0R2_FB28_Pos (28U)
4375#define CAN_F0R2_FB28_Msk (0x1UL << CAN_F0R2_FB28_Pos)
4376#define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk
4377#define CAN_F0R2_FB29_Pos (29U)
4378#define CAN_F0R2_FB29_Msk (0x1UL << CAN_F0R2_FB29_Pos)
4379#define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk
4380#define CAN_F0R2_FB30_Pos (30U)
4381#define CAN_F0R2_FB30_Msk (0x1UL << CAN_F0R2_FB30_Pos)
4382#define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk
4383#define CAN_F0R2_FB31_Pos (31U)
4384#define CAN_F0R2_FB31_Msk (0x1UL << CAN_F0R2_FB31_Pos)
4385#define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk
4387/******************* Bit definition for CAN_F1R2 register *******************/
4388#define CAN_F1R2_FB0_Pos (0U)
4389#define CAN_F1R2_FB0_Msk (0x1UL << CAN_F1R2_FB0_Pos)
4390#define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk
4391#define CAN_F1R2_FB1_Pos (1U)
4392#define CAN_F1R2_FB1_Msk (0x1UL << CAN_F1R2_FB1_Pos)
4393#define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk
4394#define CAN_F1R2_FB2_Pos (2U)
4395#define CAN_F1R2_FB2_Msk (0x1UL << CAN_F1R2_FB2_Pos)
4396#define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk
4397#define CAN_F1R2_FB3_Pos (3U)
4398#define CAN_F1R2_FB3_Msk (0x1UL << CAN_F1R2_FB3_Pos)
4399#define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk
4400#define CAN_F1R2_FB4_Pos (4U)
4401#define CAN_F1R2_FB4_Msk (0x1UL << CAN_F1R2_FB4_Pos)
4402#define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk
4403#define CAN_F1R2_FB5_Pos (5U)
4404#define CAN_F1R2_FB5_Msk (0x1UL << CAN_F1R2_FB5_Pos)
4405#define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk
4406#define CAN_F1R2_FB6_Pos (6U)
4407#define CAN_F1R2_FB6_Msk (0x1UL << CAN_F1R2_FB6_Pos)
4408#define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk
4409#define CAN_F1R2_FB7_Pos (7U)
4410#define CAN_F1R2_FB7_Msk (0x1UL << CAN_F1R2_FB7_Pos)
4411#define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk
4412#define CAN_F1R2_FB8_Pos (8U)
4413#define CAN_F1R2_FB8_Msk (0x1UL << CAN_F1R2_FB8_Pos)
4414#define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk
4415#define CAN_F1R2_FB9_Pos (9U)
4416#define CAN_F1R2_FB9_Msk (0x1UL << CAN_F1R2_FB9_Pos)
4417#define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk
4418#define CAN_F1R2_FB10_Pos (10U)
4419#define CAN_F1R2_FB10_Msk (0x1UL << CAN_F1R2_FB10_Pos)
4420#define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk
4421#define CAN_F1R2_FB11_Pos (11U)
4422#define CAN_F1R2_FB11_Msk (0x1UL << CAN_F1R2_FB11_Pos)
4423#define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk
4424#define CAN_F1R2_FB12_Pos (12U)
4425#define CAN_F1R2_FB12_Msk (0x1UL << CAN_F1R2_FB12_Pos)
4426#define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk
4427#define CAN_F1R2_FB13_Pos (13U)
4428#define CAN_F1R2_FB13_Msk (0x1UL << CAN_F1R2_FB13_Pos)
4429#define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk
4430#define CAN_F1R2_FB14_Pos (14U)
4431#define CAN_F1R2_FB14_Msk (0x1UL << CAN_F1R2_FB14_Pos)
4432#define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk
4433#define CAN_F1R2_FB15_Pos (15U)
4434#define CAN_F1R2_FB15_Msk (0x1UL << CAN_F1R2_FB15_Pos)
4435#define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk
4436#define CAN_F1R2_FB16_Pos (16U)
4437#define CAN_F1R2_FB16_Msk (0x1UL << CAN_F1R2_FB16_Pos)
4438#define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk
4439#define CAN_F1R2_FB17_Pos (17U)
4440#define CAN_F1R2_FB17_Msk (0x1UL << CAN_F1R2_FB17_Pos)
4441#define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk
4442#define CAN_F1R2_FB18_Pos (18U)
4443#define CAN_F1R2_FB18_Msk (0x1UL << CAN_F1R2_FB18_Pos)
4444#define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk
4445#define CAN_F1R2_FB19_Pos (19U)
4446#define CAN_F1R2_FB19_Msk (0x1UL << CAN_F1R2_FB19_Pos)
4447#define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk
4448#define CAN_F1R2_FB20_Pos (20U)
4449#define CAN_F1R2_FB20_Msk (0x1UL << CAN_F1R2_FB20_Pos)
4450#define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk
4451#define CAN_F1R2_FB21_Pos (21U)
4452#define CAN_F1R2_FB21_Msk (0x1UL << CAN_F1R2_FB21_Pos)
4453#define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk
4454#define CAN_F1R2_FB22_Pos (22U)
4455#define CAN_F1R2_FB22_Msk (0x1UL << CAN_F1R2_FB22_Pos)
4456#define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk
4457#define CAN_F1R2_FB23_Pos (23U)
4458#define CAN_F1R2_FB23_Msk (0x1UL << CAN_F1R2_FB23_Pos)
4459#define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk
4460#define CAN_F1R2_FB24_Pos (24U)
4461#define CAN_F1R2_FB24_Msk (0x1UL << CAN_F1R2_FB24_Pos)
4462#define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk
4463#define CAN_F1R2_FB25_Pos (25U)
4464#define CAN_F1R2_FB25_Msk (0x1UL << CAN_F1R2_FB25_Pos)
4465#define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk
4466#define CAN_F1R2_FB26_Pos (26U)
4467#define CAN_F1R2_FB26_Msk (0x1UL << CAN_F1R2_FB26_Pos)
4468#define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk
4469#define CAN_F1R2_FB27_Pos (27U)
4470#define CAN_F1R2_FB27_Msk (0x1UL << CAN_F1R2_FB27_Pos)
4471#define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk
4472#define CAN_F1R2_FB28_Pos (28U)
4473#define CAN_F1R2_FB28_Msk (0x1UL << CAN_F1R2_FB28_Pos)
4474#define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk
4475#define CAN_F1R2_FB29_Pos (29U)
4476#define CAN_F1R2_FB29_Msk (0x1UL << CAN_F1R2_FB29_Pos)
4477#define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk
4478#define CAN_F1R2_FB30_Pos (30U)
4479#define CAN_F1R2_FB30_Msk (0x1UL << CAN_F1R2_FB30_Pos)
4480#define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk
4481#define CAN_F1R2_FB31_Pos (31U)
4482#define CAN_F1R2_FB31_Msk (0x1UL << CAN_F1R2_FB31_Pos)
4483#define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk
4485/******************* Bit definition for CAN_F2R2 register *******************/
4486#define CAN_F2R2_FB0_Pos (0U)
4487#define CAN_F2R2_FB0_Msk (0x1UL << CAN_F2R2_FB0_Pos)
4488#define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk
4489#define CAN_F2R2_FB1_Pos (1U)
4490#define CAN_F2R2_FB1_Msk (0x1UL << CAN_F2R2_FB1_Pos)
4491#define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk
4492#define CAN_F2R2_FB2_Pos (2U)
4493#define CAN_F2R2_FB2_Msk (0x1UL << CAN_F2R2_FB2_Pos)
4494#define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk
4495#define CAN_F2R2_FB3_Pos (3U)
4496#define CAN_F2R2_FB3_Msk (0x1UL << CAN_F2R2_FB3_Pos)
4497#define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk
4498#define CAN_F2R2_FB4_Pos (4U)
4499#define CAN_F2R2_FB4_Msk (0x1UL << CAN_F2R2_FB4_Pos)
4500#define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk
4501#define CAN_F2R2_FB5_Pos (5U)
4502#define CAN_F2R2_FB5_Msk (0x1UL << CAN_F2R2_FB5_Pos)
4503#define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk
4504#define CAN_F2R2_FB6_Pos (6U)
4505#define CAN_F2R2_FB6_Msk (0x1UL << CAN_F2R2_FB6_Pos)
4506#define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk
4507#define CAN_F2R2_FB7_Pos (7U)
4508#define CAN_F2R2_FB7_Msk (0x1UL << CAN_F2R2_FB7_Pos)
4509#define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk
4510#define CAN_F2R2_FB8_Pos (8U)
4511#define CAN_F2R2_FB8_Msk (0x1UL << CAN_F2R2_FB8_Pos)
4512#define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk
4513#define CAN_F2R2_FB9_Pos (9U)
4514#define CAN_F2R2_FB9_Msk (0x1UL << CAN_F2R2_FB9_Pos)
4515#define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk
4516#define CAN_F2R2_FB10_Pos (10U)
4517#define CAN_F2R2_FB10_Msk (0x1UL << CAN_F2R2_FB10_Pos)
4518#define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk
4519#define CAN_F2R2_FB11_Pos (11U)
4520#define CAN_F2R2_FB11_Msk (0x1UL << CAN_F2R2_FB11_Pos)
4521#define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk
4522#define CAN_F2R2_FB12_Pos (12U)
4523#define CAN_F2R2_FB12_Msk (0x1UL << CAN_F2R2_FB12_Pos)
4524#define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk
4525#define CAN_F2R2_FB13_Pos (13U)
4526#define CAN_F2R2_FB13_Msk (0x1UL << CAN_F2R2_FB13_Pos)
4527#define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk
4528#define CAN_F2R2_FB14_Pos (14U)
4529#define CAN_F2R2_FB14_Msk (0x1UL << CAN_F2R2_FB14_Pos)
4530#define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk
4531#define CAN_F2R2_FB15_Pos (15U)
4532#define CAN_F2R2_FB15_Msk (0x1UL << CAN_F2R2_FB15_Pos)
4533#define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk
4534#define CAN_F2R2_FB16_Pos (16U)
4535#define CAN_F2R2_FB16_Msk (0x1UL << CAN_F2R2_FB16_Pos)
4536#define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk
4537#define CAN_F2R2_FB17_Pos (17U)
4538#define CAN_F2R2_FB17_Msk (0x1UL << CAN_F2R2_FB17_Pos)
4539#define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk
4540#define CAN_F2R2_FB18_Pos (18U)
4541#define CAN_F2R2_FB18_Msk (0x1UL << CAN_F2R2_FB18_Pos)
4542#define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk
4543#define CAN_F2R2_FB19_Pos (19U)
4544#define CAN_F2R2_FB19_Msk (0x1UL << CAN_F2R2_FB19_Pos)
4545#define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk
4546#define CAN_F2R2_FB20_Pos (20U)
4547#define CAN_F2R2_FB20_Msk (0x1UL << CAN_F2R2_FB20_Pos)
4548#define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk
4549#define CAN_F2R2_FB21_Pos (21U)
4550#define CAN_F2R2_FB21_Msk (0x1UL << CAN_F2R2_FB21_Pos)
4551#define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk
4552#define CAN_F2R2_FB22_Pos (22U)
4553#define CAN_F2R2_FB22_Msk (0x1UL << CAN_F2R2_FB22_Pos)
4554#define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk
4555#define CAN_F2R2_FB23_Pos (23U)
4556#define CAN_F2R2_FB23_Msk (0x1UL << CAN_F2R2_FB23_Pos)
4557#define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk
4558#define CAN_F2R2_FB24_Pos (24U)
4559#define CAN_F2R2_FB24_Msk (0x1UL << CAN_F2R2_FB24_Pos)
4560#define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk
4561#define CAN_F2R2_FB25_Pos (25U)
4562#define CAN_F2R2_FB25_Msk (0x1UL << CAN_F2R2_FB25_Pos)
4563#define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk
4564#define CAN_F2R2_FB26_Pos (26U)
4565#define CAN_F2R2_FB26_Msk (0x1UL << CAN_F2R2_FB26_Pos)
4566#define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk
4567#define CAN_F2R2_FB27_Pos (27U)
4568#define CAN_F2R2_FB27_Msk (0x1UL << CAN_F2R2_FB27_Pos)
4569#define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk
4570#define CAN_F2R2_FB28_Pos (28U)
4571#define CAN_F2R2_FB28_Msk (0x1UL << CAN_F2R2_FB28_Pos)
4572#define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk
4573#define CAN_F2R2_FB29_Pos (29U)
4574#define CAN_F2R2_FB29_Msk (0x1UL << CAN_F2R2_FB29_Pos)
4575#define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk
4576#define CAN_F2R2_FB30_Pos (30U)
4577#define CAN_F2R2_FB30_Msk (0x1UL << CAN_F2R2_FB30_Pos)
4578#define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk
4579#define CAN_F2R2_FB31_Pos (31U)
4580#define CAN_F2R2_FB31_Msk (0x1UL << CAN_F2R2_FB31_Pos)
4581#define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk
4583/******************* Bit definition for CAN_F3R2 register *******************/
4584#define CAN_F3R2_FB0_Pos (0U)
4585#define CAN_F3R2_FB0_Msk (0x1UL << CAN_F3R2_FB0_Pos)
4586#define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk
4587#define CAN_F3R2_FB1_Pos (1U)
4588#define CAN_F3R2_FB1_Msk (0x1UL << CAN_F3R2_FB1_Pos)
4589#define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk
4590#define CAN_F3R2_FB2_Pos (2U)
4591#define CAN_F3R2_FB2_Msk (0x1UL << CAN_F3R2_FB2_Pos)
4592#define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk
4593#define CAN_F3R2_FB3_Pos (3U)
4594#define CAN_F3R2_FB3_Msk (0x1UL << CAN_F3R2_FB3_Pos)
4595#define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk
4596#define CAN_F3R2_FB4_Pos (4U)
4597#define CAN_F3R2_FB4_Msk (0x1UL << CAN_F3R2_FB4_Pos)
4598#define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk
4599#define CAN_F3R2_FB5_Pos (5U)
4600#define CAN_F3R2_FB5_Msk (0x1UL << CAN_F3R2_FB5_Pos)
4601#define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk
4602#define CAN_F3R2_FB6_Pos (6U)
4603#define CAN_F3R2_FB6_Msk (0x1UL << CAN_F3R2_FB6_Pos)
4604#define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk
4605#define CAN_F3R2_FB7_Pos (7U)
4606#define CAN_F3R2_FB7_Msk (0x1UL << CAN_F3R2_FB7_Pos)
4607#define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk
4608#define CAN_F3R2_FB8_Pos (8U)
4609#define CAN_F3R2_FB8_Msk (0x1UL << CAN_F3R2_FB8_Pos)
4610#define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk
4611#define CAN_F3R2_FB9_Pos (9U)
4612#define CAN_F3R2_FB9_Msk (0x1UL << CAN_F3R2_FB9_Pos)
4613#define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk
4614#define CAN_F3R2_FB10_Pos (10U)
4615#define CAN_F3R2_FB10_Msk (0x1UL << CAN_F3R2_FB10_Pos)
4616#define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk
4617#define CAN_F3R2_FB11_Pos (11U)
4618#define CAN_F3R2_FB11_Msk (0x1UL << CAN_F3R2_FB11_Pos)
4619#define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk
4620#define CAN_F3R2_FB12_Pos (12U)
4621#define CAN_F3R2_FB12_Msk (0x1UL << CAN_F3R2_FB12_Pos)
4622#define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk
4623#define CAN_F3R2_FB13_Pos (13U)
4624#define CAN_F3R2_FB13_Msk (0x1UL << CAN_F3R2_FB13_Pos)
4625#define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk
4626#define CAN_F3R2_FB14_Pos (14U)
4627#define CAN_F3R2_FB14_Msk (0x1UL << CAN_F3R2_FB14_Pos)
4628#define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk
4629#define CAN_F3R2_FB15_Pos (15U)
4630#define CAN_F3R2_FB15_Msk (0x1UL << CAN_F3R2_FB15_Pos)
4631#define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk
4632#define CAN_F3R2_FB16_Pos (16U)
4633#define CAN_F3R2_FB16_Msk (0x1UL << CAN_F3R2_FB16_Pos)
4634#define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk
4635#define CAN_F3R2_FB17_Pos (17U)
4636#define CAN_F3R2_FB17_Msk (0x1UL << CAN_F3R2_FB17_Pos)
4637#define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk
4638#define CAN_F3R2_FB18_Pos (18U)
4639#define CAN_F3R2_FB18_Msk (0x1UL << CAN_F3R2_FB18_Pos)
4640#define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk
4641#define CAN_F3R2_FB19_Pos (19U)
4642#define CAN_F3R2_FB19_Msk (0x1UL << CAN_F3R2_FB19_Pos)
4643#define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk
4644#define CAN_F3R2_FB20_Pos (20U)
4645#define CAN_F3R2_FB20_Msk (0x1UL << CAN_F3R2_FB20_Pos)
4646#define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk
4647#define CAN_F3R2_FB21_Pos (21U)
4648#define CAN_F3R2_FB21_Msk (0x1UL << CAN_F3R2_FB21_Pos)
4649#define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk
4650#define CAN_F3R2_FB22_Pos (22U)
4651#define CAN_F3R2_FB22_Msk (0x1UL << CAN_F3R2_FB22_Pos)
4652#define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk
4653#define CAN_F3R2_FB23_Pos (23U)
4654#define CAN_F3R2_FB23_Msk (0x1UL << CAN_F3R2_FB23_Pos)
4655#define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk
4656#define CAN_F3R2_FB24_Pos (24U)
4657#define CAN_F3R2_FB24_Msk (0x1UL << CAN_F3R2_FB24_Pos)
4658#define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk
4659#define CAN_F3R2_FB25_Pos (25U)
4660#define CAN_F3R2_FB25_Msk (0x1UL << CAN_F3R2_FB25_Pos)
4661#define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk
4662#define CAN_F3R2_FB26_Pos (26U)
4663#define CAN_F3R2_FB26_Msk (0x1UL << CAN_F3R2_FB26_Pos)
4664#define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk
4665#define CAN_F3R2_FB27_Pos (27U)
4666#define CAN_F3R2_FB27_Msk (0x1UL << CAN_F3R2_FB27_Pos)
4667#define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk
4668#define CAN_F3R2_FB28_Pos (28U)
4669#define CAN_F3R2_FB28_Msk (0x1UL << CAN_F3R2_FB28_Pos)
4670#define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk
4671#define CAN_F3R2_FB29_Pos (29U)
4672#define CAN_F3R2_FB29_Msk (0x1UL << CAN_F3R2_FB29_Pos)
4673#define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk
4674#define CAN_F3R2_FB30_Pos (30U)
4675#define CAN_F3R2_FB30_Msk (0x1UL << CAN_F3R2_FB30_Pos)
4676#define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk
4677#define CAN_F3R2_FB31_Pos (31U)
4678#define CAN_F3R2_FB31_Msk (0x1UL << CAN_F3R2_FB31_Pos)
4679#define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk
4681/******************* Bit definition for CAN_F4R2 register *******************/
4682#define CAN_F4R2_FB0_Pos (0U)
4683#define CAN_F4R2_FB0_Msk (0x1UL << CAN_F4R2_FB0_Pos)
4684#define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk
4685#define CAN_F4R2_FB1_Pos (1U)
4686#define CAN_F4R2_FB1_Msk (0x1UL << CAN_F4R2_FB1_Pos)
4687#define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk
4688#define CAN_F4R2_FB2_Pos (2U)
4689#define CAN_F4R2_FB2_Msk (0x1UL << CAN_F4R2_FB2_Pos)
4690#define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk
4691#define CAN_F4R2_FB3_Pos (3U)
4692#define CAN_F4R2_FB3_Msk (0x1UL << CAN_F4R2_FB3_Pos)
4693#define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk
4694#define CAN_F4R2_FB4_Pos (4U)
4695#define CAN_F4R2_FB4_Msk (0x1UL << CAN_F4R2_FB4_Pos)
4696#define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk
4697#define CAN_F4R2_FB5_Pos (5U)
4698#define CAN_F4R2_FB5_Msk (0x1UL << CAN_F4R2_FB5_Pos)
4699#define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk
4700#define CAN_F4R2_FB6_Pos (6U)
4701#define CAN_F4R2_FB6_Msk (0x1UL << CAN_F4R2_FB6_Pos)
4702#define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk
4703#define CAN_F4R2_FB7_Pos (7U)
4704#define CAN_F4R2_FB7_Msk (0x1UL << CAN_F4R2_FB7_Pos)
4705#define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk
4706#define CAN_F4R2_FB8_Pos (8U)
4707#define CAN_F4R2_FB8_Msk (0x1UL << CAN_F4R2_FB8_Pos)
4708#define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk
4709#define CAN_F4R2_FB9_Pos (9U)
4710#define CAN_F4R2_FB9_Msk (0x1UL << CAN_F4R2_FB9_Pos)
4711#define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk
4712#define CAN_F4R2_FB10_Pos (10U)
4713#define CAN_F4R2_FB10_Msk (0x1UL << CAN_F4R2_FB10_Pos)
4714#define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk
4715#define CAN_F4R2_FB11_Pos (11U)
4716#define CAN_F4R2_FB11_Msk (0x1UL << CAN_F4R2_FB11_Pos)
4717#define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk
4718#define CAN_F4R2_FB12_Pos (12U)
4719#define CAN_F4R2_FB12_Msk (0x1UL << CAN_F4R2_FB12_Pos)
4720#define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk
4721#define CAN_F4R2_FB13_Pos (13U)
4722#define CAN_F4R2_FB13_Msk (0x1UL << CAN_F4R2_FB13_Pos)
4723#define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk
4724#define CAN_F4R2_FB14_Pos (14U)
4725#define CAN_F4R2_FB14_Msk (0x1UL << CAN_F4R2_FB14_Pos)
4726#define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk
4727#define CAN_F4R2_FB15_Pos (15U)
4728#define CAN_F4R2_FB15_Msk (0x1UL << CAN_F4R2_FB15_Pos)
4729#define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk
4730#define CAN_F4R2_FB16_Pos (16U)
4731#define CAN_F4R2_FB16_Msk (0x1UL << CAN_F4R2_FB16_Pos)
4732#define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk
4733#define CAN_F4R2_FB17_Pos (17U)
4734#define CAN_F4R2_FB17_Msk (0x1UL << CAN_F4R2_FB17_Pos)
4735#define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk
4736#define CAN_F4R2_FB18_Pos (18U)
4737#define CAN_F4R2_FB18_Msk (0x1UL << CAN_F4R2_FB18_Pos)
4738#define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk
4739#define CAN_F4R2_FB19_Pos (19U)
4740#define CAN_F4R2_FB19_Msk (0x1UL << CAN_F4R2_FB19_Pos)
4741#define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk
4742#define CAN_F4R2_FB20_Pos (20U)
4743#define CAN_F4R2_FB20_Msk (0x1UL << CAN_F4R2_FB20_Pos)
4744#define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk
4745#define CAN_F4R2_FB21_Pos (21U)
4746#define CAN_F4R2_FB21_Msk (0x1UL << CAN_F4R2_FB21_Pos)
4747#define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk
4748#define CAN_F4R2_FB22_Pos (22U)
4749#define CAN_F4R2_FB22_Msk (0x1UL << CAN_F4R2_FB22_Pos)
4750#define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk
4751#define CAN_F4R2_FB23_Pos (23U)
4752#define CAN_F4R2_FB23_Msk (0x1UL << CAN_F4R2_FB23_Pos)
4753#define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk
4754#define CAN_F4R2_FB24_Pos (24U)
4755#define CAN_F4R2_FB24_Msk (0x1UL << CAN_F4R2_FB24_Pos)
4756#define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk
4757#define CAN_F4R2_FB25_Pos (25U)
4758#define CAN_F4R2_FB25_Msk (0x1UL << CAN_F4R2_FB25_Pos)
4759#define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk
4760#define CAN_F4R2_FB26_Pos (26U)
4761#define CAN_F4R2_FB26_Msk (0x1UL << CAN_F4R2_FB26_Pos)
4762#define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk
4763#define CAN_F4R2_FB27_Pos (27U)
4764#define CAN_F4R2_FB27_Msk (0x1UL << CAN_F4R2_FB27_Pos)
4765#define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk
4766#define CAN_F4R2_FB28_Pos (28U)
4767#define CAN_F4R2_FB28_Msk (0x1UL << CAN_F4R2_FB28_Pos)
4768#define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk
4769#define CAN_F4R2_FB29_Pos (29U)
4770#define CAN_F4R2_FB29_Msk (0x1UL << CAN_F4R2_FB29_Pos)
4771#define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk
4772#define CAN_F4R2_FB30_Pos (30U)
4773#define CAN_F4R2_FB30_Msk (0x1UL << CAN_F4R2_FB30_Pos)
4774#define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk
4775#define CAN_F4R2_FB31_Pos (31U)
4776#define CAN_F4R2_FB31_Msk (0x1UL << CAN_F4R2_FB31_Pos)
4777#define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk
4779/******************* Bit definition for CAN_F5R2 register *******************/
4780#define CAN_F5R2_FB0_Pos (0U)
4781#define CAN_F5R2_FB0_Msk (0x1UL << CAN_F5R2_FB0_Pos)
4782#define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk
4783#define CAN_F5R2_FB1_Pos (1U)
4784#define CAN_F5R2_FB1_Msk (0x1UL << CAN_F5R2_FB1_Pos)
4785#define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk
4786#define CAN_F5R2_FB2_Pos (2U)
4787#define CAN_F5R2_FB2_Msk (0x1UL << CAN_F5R2_FB2_Pos)
4788#define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk
4789#define CAN_F5R2_FB3_Pos (3U)
4790#define CAN_F5R2_FB3_Msk (0x1UL << CAN_F5R2_FB3_Pos)
4791#define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk
4792#define CAN_F5R2_FB4_Pos (4U)
4793#define CAN_F5R2_FB4_Msk (0x1UL << CAN_F5R2_FB4_Pos)
4794#define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk
4795#define CAN_F5R2_FB5_Pos (5U)
4796#define CAN_F5R2_FB5_Msk (0x1UL << CAN_F5R2_FB5_Pos)
4797#define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk
4798#define CAN_F5R2_FB6_Pos (6U)
4799#define CAN_F5R2_FB6_Msk (0x1UL << CAN_F5R2_FB6_Pos)
4800#define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk
4801#define CAN_F5R2_FB7_Pos (7U)
4802#define CAN_F5R2_FB7_Msk (0x1UL << CAN_F5R2_FB7_Pos)
4803#define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk
4804#define CAN_F5R2_FB8_Pos (8U)
4805#define CAN_F5R2_FB8_Msk (0x1UL << CAN_F5R2_FB8_Pos)
4806#define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk
4807#define CAN_F5R2_FB9_Pos (9U)
4808#define CAN_F5R2_FB9_Msk (0x1UL << CAN_F5R2_FB9_Pos)
4809#define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk
4810#define CAN_F5R2_FB10_Pos (10U)
4811#define CAN_F5R2_FB10_Msk (0x1UL << CAN_F5R2_FB10_Pos)
4812#define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk
4813#define CAN_F5R2_FB11_Pos (11U)
4814#define CAN_F5R2_FB11_Msk (0x1UL << CAN_F5R2_FB11_Pos)
4815#define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk
4816#define CAN_F5R2_FB12_Pos (12U)
4817#define CAN_F5R2_FB12_Msk (0x1UL << CAN_F5R2_FB12_Pos)
4818#define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk
4819#define CAN_F5R2_FB13_Pos (13U)
4820#define CAN_F5R2_FB13_Msk (0x1UL << CAN_F5R2_FB13_Pos)
4821#define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk
4822#define CAN_F5R2_FB14_Pos (14U)
4823#define CAN_F5R2_FB14_Msk (0x1UL << CAN_F5R2_FB14_Pos)
4824#define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk
4825#define CAN_F5R2_FB15_Pos (15U)
4826#define CAN_F5R2_FB15_Msk (0x1UL << CAN_F5R2_FB15_Pos)
4827#define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk
4828#define CAN_F5R2_FB16_Pos (16U)
4829#define CAN_F5R2_FB16_Msk (0x1UL << CAN_F5R2_FB16_Pos)
4830#define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk
4831#define CAN_F5R2_FB17_Pos (17U)
4832#define CAN_F5R2_FB17_Msk (0x1UL << CAN_F5R2_FB17_Pos)
4833#define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk
4834#define CAN_F5R2_FB18_Pos (18U)
4835#define CAN_F5R2_FB18_Msk (0x1UL << CAN_F5R2_FB18_Pos)
4836#define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk
4837#define CAN_F5R2_FB19_Pos (19U)
4838#define CAN_F5R2_FB19_Msk (0x1UL << CAN_F5R2_FB19_Pos)
4839#define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk
4840#define CAN_F5R2_FB20_Pos (20U)
4841#define CAN_F5R2_FB20_Msk (0x1UL << CAN_F5R2_FB20_Pos)
4842#define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk
4843#define CAN_F5R2_FB21_Pos (21U)
4844#define CAN_F5R2_FB21_Msk (0x1UL << CAN_F5R2_FB21_Pos)
4845#define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk
4846#define CAN_F5R2_FB22_Pos (22U)
4847#define CAN_F5R2_FB22_Msk (0x1UL << CAN_F5R2_FB22_Pos)
4848#define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk
4849#define CAN_F5R2_FB23_Pos (23U)
4850#define CAN_F5R2_FB23_Msk (0x1UL << CAN_F5R2_FB23_Pos)
4851#define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk
4852#define CAN_F5R2_FB24_Pos (24U)
4853#define CAN_F5R2_FB24_Msk (0x1UL << CAN_F5R2_FB24_Pos)
4854#define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk
4855#define CAN_F5R2_FB25_Pos (25U)
4856#define CAN_F5R2_FB25_Msk (0x1UL << CAN_F5R2_FB25_Pos)
4857#define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk
4858#define CAN_F5R2_FB26_Pos (26U)
4859#define CAN_F5R2_FB26_Msk (0x1UL << CAN_F5R2_FB26_Pos)
4860#define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk
4861#define CAN_F5R2_FB27_Pos (27U)
4862#define CAN_F5R2_FB27_Msk (0x1UL << CAN_F5R2_FB27_Pos)
4863#define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk
4864#define CAN_F5R2_FB28_Pos (28U)
4865#define CAN_F5R2_FB28_Msk (0x1UL << CAN_F5R2_FB28_Pos)
4866#define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk
4867#define CAN_F5R2_FB29_Pos (29U)
4868#define CAN_F5R2_FB29_Msk (0x1UL << CAN_F5R2_FB29_Pos)
4869#define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk
4870#define CAN_F5R2_FB30_Pos (30U)
4871#define CAN_F5R2_FB30_Msk (0x1UL << CAN_F5R2_FB30_Pos)
4872#define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk
4873#define CAN_F5R2_FB31_Pos (31U)
4874#define CAN_F5R2_FB31_Msk (0x1UL << CAN_F5R2_FB31_Pos)
4875#define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk
4877/******************* Bit definition for CAN_F6R2 register *******************/
4878#define CAN_F6R2_FB0_Pos (0U)
4879#define CAN_F6R2_FB0_Msk (0x1UL << CAN_F6R2_FB0_Pos)
4880#define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk
4881#define CAN_F6R2_FB1_Pos (1U)
4882#define CAN_F6R2_FB1_Msk (0x1UL << CAN_F6R2_FB1_Pos)
4883#define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk
4884#define CAN_F6R2_FB2_Pos (2U)
4885#define CAN_F6R2_FB2_Msk (0x1UL << CAN_F6R2_FB2_Pos)
4886#define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk
4887#define CAN_F6R2_FB3_Pos (3U)
4888#define CAN_F6R2_FB3_Msk (0x1UL << CAN_F6R2_FB3_Pos)
4889#define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk
4890#define CAN_F6R2_FB4_Pos (4U)
4891#define CAN_F6R2_FB4_Msk (0x1UL << CAN_F6R2_FB4_Pos)
4892#define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk
4893#define CAN_F6R2_FB5_Pos (5U)
4894#define CAN_F6R2_FB5_Msk (0x1UL << CAN_F6R2_FB5_Pos)
4895#define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk
4896#define CAN_F6R2_FB6_Pos (6U)
4897#define CAN_F6R2_FB6_Msk (0x1UL << CAN_F6R2_FB6_Pos)
4898#define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk
4899#define CAN_F6R2_FB7_Pos (7U)
4900#define CAN_F6R2_FB7_Msk (0x1UL << CAN_F6R2_FB7_Pos)
4901#define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk
4902#define CAN_F6R2_FB8_Pos (8U)
4903#define CAN_F6R2_FB8_Msk (0x1UL << CAN_F6R2_FB8_Pos)
4904#define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk
4905#define CAN_F6R2_FB9_Pos (9U)
4906#define CAN_F6R2_FB9_Msk (0x1UL << CAN_F6R2_FB9_Pos)
4907#define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk
4908#define CAN_F6R2_FB10_Pos (10U)
4909#define CAN_F6R2_FB10_Msk (0x1UL << CAN_F6R2_FB10_Pos)
4910#define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk
4911#define CAN_F6R2_FB11_Pos (11U)
4912#define CAN_F6R2_FB11_Msk (0x1UL << CAN_F6R2_FB11_Pos)
4913#define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk
4914#define CAN_F6R2_FB12_Pos (12U)
4915#define CAN_F6R2_FB12_Msk (0x1UL << CAN_F6R2_FB12_Pos)
4916#define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk
4917#define CAN_F6R2_FB13_Pos (13U)
4918#define CAN_F6R2_FB13_Msk (0x1UL << CAN_F6R2_FB13_Pos)
4919#define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk
4920#define CAN_F6R2_FB14_Pos (14U)
4921#define CAN_F6R2_FB14_Msk (0x1UL << CAN_F6R2_FB14_Pos)
4922#define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk
4923#define CAN_F6R2_FB15_Pos (15U)
4924#define CAN_F6R2_FB15_Msk (0x1UL << CAN_F6R2_FB15_Pos)
4925#define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk
4926#define CAN_F6R2_FB16_Pos (16U)
4927#define CAN_F6R2_FB16_Msk (0x1UL << CAN_F6R2_FB16_Pos)
4928#define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk
4929#define CAN_F6R2_FB17_Pos (17U)
4930#define CAN_F6R2_FB17_Msk (0x1UL << CAN_F6R2_FB17_Pos)
4931#define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk
4932#define CAN_F6R2_FB18_Pos (18U)
4933#define CAN_F6R2_FB18_Msk (0x1UL << CAN_F6R2_FB18_Pos)
4934#define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk
4935#define CAN_F6R2_FB19_Pos (19U)
4936#define CAN_F6R2_FB19_Msk (0x1UL << CAN_F6R2_FB19_Pos)
4937#define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk
4938#define CAN_F6R2_FB20_Pos (20U)
4939#define CAN_F6R2_FB20_Msk (0x1UL << CAN_F6R2_FB20_Pos)
4940#define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk
4941#define CAN_F6R2_FB21_Pos (21U)
4942#define CAN_F6R2_FB21_Msk (0x1UL << CAN_F6R2_FB21_Pos)
4943#define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk
4944#define CAN_F6R2_FB22_Pos (22U)
4945#define CAN_F6R2_FB22_Msk (0x1UL << CAN_F6R2_FB22_Pos)
4946#define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk
4947#define CAN_F6R2_FB23_Pos (23U)
4948#define CAN_F6R2_FB23_Msk (0x1UL << CAN_F6R2_FB23_Pos)
4949#define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk
4950#define CAN_F6R2_FB24_Pos (24U)
4951#define CAN_F6R2_FB24_Msk (0x1UL << CAN_F6R2_FB24_Pos)
4952#define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk
4953#define CAN_F6R2_FB25_Pos (25U)
4954#define CAN_F6R2_FB25_Msk (0x1UL << CAN_F6R2_FB25_Pos)
4955#define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk
4956#define CAN_F6R2_FB26_Pos (26U)
4957#define CAN_F6R2_FB26_Msk (0x1UL << CAN_F6R2_FB26_Pos)
4958#define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk
4959#define CAN_F6R2_FB27_Pos (27U)
4960#define CAN_F6R2_FB27_Msk (0x1UL << CAN_F6R2_FB27_Pos)
4961#define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk
4962#define CAN_F6R2_FB28_Pos (28U)
4963#define CAN_F6R2_FB28_Msk (0x1UL << CAN_F6R2_FB28_Pos)
4964#define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk
4965#define CAN_F6R2_FB29_Pos (29U)
4966#define CAN_F6R2_FB29_Msk (0x1UL << CAN_F6R2_FB29_Pos)
4967#define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk
4968#define CAN_F6R2_FB30_Pos (30U)
4969#define CAN_F6R2_FB30_Msk (0x1UL << CAN_F6R2_FB30_Pos)
4970#define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk
4971#define CAN_F6R2_FB31_Pos (31U)
4972#define CAN_F6R2_FB31_Msk (0x1UL << CAN_F6R2_FB31_Pos)
4973#define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk
4975/******************* Bit definition for CAN_F7R2 register *******************/
4976#define CAN_F7R2_FB0_Pos (0U)
4977#define CAN_F7R2_FB0_Msk (0x1UL << CAN_F7R2_FB0_Pos)
4978#define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk
4979#define CAN_F7R2_FB1_Pos (1U)
4980#define CAN_F7R2_FB1_Msk (0x1UL << CAN_F7R2_FB1_Pos)
4981#define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk
4982#define CAN_F7R2_FB2_Pos (2U)
4983#define CAN_F7R2_FB2_Msk (0x1UL << CAN_F7R2_FB2_Pos)
4984#define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk
4985#define CAN_F7R2_FB3_Pos (3U)
4986#define CAN_F7R2_FB3_Msk (0x1UL << CAN_F7R2_FB3_Pos)
4987#define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk
4988#define CAN_F7R2_FB4_Pos (4U)
4989#define CAN_F7R2_FB4_Msk (0x1UL << CAN_F7R2_FB4_Pos)
4990#define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk
4991#define CAN_F7R2_FB5_Pos (5U)
4992#define CAN_F7R2_FB5_Msk (0x1UL << CAN_F7R2_FB5_Pos)
4993#define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk
4994#define CAN_F7R2_FB6_Pos (6U)
4995#define CAN_F7R2_FB6_Msk (0x1UL << CAN_F7R2_FB6_Pos)
4996#define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk
4997#define CAN_F7R2_FB7_Pos (7U)
4998#define CAN_F7R2_FB7_Msk (0x1UL << CAN_F7R2_FB7_Pos)
4999#define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk
5000#define CAN_F7R2_FB8_Pos (8U)
5001#define CAN_F7R2_FB8_Msk (0x1UL << CAN_F7R2_FB8_Pos)
5002#define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk
5003#define CAN_F7R2_FB9_Pos (9U)
5004#define CAN_F7R2_FB9_Msk (0x1UL << CAN_F7R2_FB9_Pos)
5005#define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk
5006#define CAN_F7R2_FB10_Pos (10U)
5007#define CAN_F7R2_FB10_Msk (0x1UL << CAN_F7R2_FB10_Pos)
5008#define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk
5009#define CAN_F7R2_FB11_Pos (11U)
5010#define CAN_F7R2_FB11_Msk (0x1UL << CAN_F7R2_FB11_Pos)
5011#define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk
5012#define CAN_F7R2_FB12_Pos (12U)
5013#define CAN_F7R2_FB12_Msk (0x1UL << CAN_F7R2_FB12_Pos)
5014#define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk
5015#define CAN_F7R2_FB13_Pos (13U)
5016#define CAN_F7R2_FB13_Msk (0x1UL << CAN_F7R2_FB13_Pos)
5017#define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk
5018#define CAN_F7R2_FB14_Pos (14U)
5019#define CAN_F7R2_FB14_Msk (0x1UL << CAN_F7R2_FB14_Pos)
5020#define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk
5021#define CAN_F7R2_FB15_Pos (15U)
5022#define CAN_F7R2_FB15_Msk (0x1UL << CAN_F7R2_FB15_Pos)
5023#define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk
5024#define CAN_F7R2_FB16_Pos (16U)
5025#define CAN_F7R2_FB16_Msk (0x1UL << CAN_F7R2_FB16_Pos)
5026#define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk
5027#define CAN_F7R2_FB17_Pos (17U)
5028#define CAN_F7R2_FB17_Msk (0x1UL << CAN_F7R2_FB17_Pos)
5029#define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk
5030#define CAN_F7R2_FB18_Pos (18U)
5031#define CAN_F7R2_FB18_Msk (0x1UL << CAN_F7R2_FB18_Pos)
5032#define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk
5033#define CAN_F7R2_FB19_Pos (19U)
5034#define CAN_F7R2_FB19_Msk (0x1UL << CAN_F7R2_FB19_Pos)
5035#define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk
5036#define CAN_F7R2_FB20_Pos (20U)
5037#define CAN_F7R2_FB20_Msk (0x1UL << CAN_F7R2_FB20_Pos)
5038#define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk
5039#define CAN_F7R2_FB21_Pos (21U)
5040#define CAN_F7R2_FB21_Msk (0x1UL << CAN_F7R2_FB21_Pos)
5041#define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk
5042#define CAN_F7R2_FB22_Pos (22U)
5043#define CAN_F7R2_FB22_Msk (0x1UL << CAN_F7R2_FB22_Pos)
5044#define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk
5045#define CAN_F7R2_FB23_Pos (23U)
5046#define CAN_F7R2_FB23_Msk (0x1UL << CAN_F7R2_FB23_Pos)
5047#define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk
5048#define CAN_F7R2_FB24_Pos (24U)
5049#define CAN_F7R2_FB24_Msk (0x1UL << CAN_F7R2_FB24_Pos)
5050#define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk
5051#define CAN_F7R2_FB25_Pos (25U)
5052#define CAN_F7R2_FB25_Msk (0x1UL << CAN_F7R2_FB25_Pos)
5053#define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk
5054#define CAN_F7R2_FB26_Pos (26U)
5055#define CAN_F7R2_FB26_Msk (0x1UL << CAN_F7R2_FB26_Pos)
5056#define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk
5057#define CAN_F7R2_FB27_Pos (27U)
5058#define CAN_F7R2_FB27_Msk (0x1UL << CAN_F7R2_FB27_Pos)
5059#define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk
5060#define CAN_F7R2_FB28_Pos (28U)
5061#define CAN_F7R2_FB28_Msk (0x1UL << CAN_F7R2_FB28_Pos)
5062#define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk
5063#define CAN_F7R2_FB29_Pos (29U)
5064#define CAN_F7R2_FB29_Msk (0x1UL << CAN_F7R2_FB29_Pos)
5065#define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk
5066#define CAN_F7R2_FB30_Pos (30U)
5067#define CAN_F7R2_FB30_Msk (0x1UL << CAN_F7R2_FB30_Pos)
5068#define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk
5069#define CAN_F7R2_FB31_Pos (31U)
5070#define CAN_F7R2_FB31_Msk (0x1UL << CAN_F7R2_FB31_Pos)
5071#define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk
5073/******************* Bit definition for CAN_F8R2 register *******************/
5074#define CAN_F8R2_FB0_Pos (0U)
5075#define CAN_F8R2_FB0_Msk (0x1UL << CAN_F8R2_FB0_Pos)
5076#define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk
5077#define CAN_F8R2_FB1_Pos (1U)
5078#define CAN_F8R2_FB1_Msk (0x1UL << CAN_F8R2_FB1_Pos)
5079#define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk
5080#define CAN_F8R2_FB2_Pos (2U)
5081#define CAN_F8R2_FB2_Msk (0x1UL << CAN_F8R2_FB2_Pos)
5082#define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk
5083#define CAN_F8R2_FB3_Pos (3U)
5084#define CAN_F8R2_FB3_Msk (0x1UL << CAN_F8R2_FB3_Pos)
5085#define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk
5086#define CAN_F8R2_FB4_Pos (4U)
5087#define CAN_F8R2_FB4_Msk (0x1UL << CAN_F8R2_FB4_Pos)
5088#define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk
5089#define CAN_F8R2_FB5_Pos (5U)
5090#define CAN_F8R2_FB5_Msk (0x1UL << CAN_F8R2_FB5_Pos)
5091#define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk
5092#define CAN_F8R2_FB6_Pos (6U)
5093#define CAN_F8R2_FB6_Msk (0x1UL << CAN_F8R2_FB6_Pos)
5094#define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk
5095#define CAN_F8R2_FB7_Pos (7U)
5096#define CAN_F8R2_FB7_Msk (0x1UL << CAN_F8R2_FB7_Pos)
5097#define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk
5098#define CAN_F8R2_FB8_Pos (8U)
5099#define CAN_F8R2_FB8_Msk (0x1UL << CAN_F8R2_FB8_Pos)
5100#define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk
5101#define CAN_F8R2_FB9_Pos (9U)
5102#define CAN_F8R2_FB9_Msk (0x1UL << CAN_F8R2_FB9_Pos)
5103#define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk
5104#define CAN_F8R2_FB10_Pos (10U)
5105#define CAN_F8R2_FB10_Msk (0x1UL << CAN_F8R2_FB10_Pos)
5106#define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk
5107#define CAN_F8R2_FB11_Pos (11U)
5108#define CAN_F8R2_FB11_Msk (0x1UL << CAN_F8R2_FB11_Pos)
5109#define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk
5110#define CAN_F8R2_FB12_Pos (12U)
5111#define CAN_F8R2_FB12_Msk (0x1UL << CAN_F8R2_FB12_Pos)
5112#define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk
5113#define CAN_F8R2_FB13_Pos (13U)
5114#define CAN_F8R2_FB13_Msk (0x1UL << CAN_F8R2_FB13_Pos)
5115#define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk
5116#define CAN_F8R2_FB14_Pos (14U)
5117#define CAN_F8R2_FB14_Msk (0x1UL << CAN_F8R2_FB14_Pos)
5118#define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk
5119#define CAN_F8R2_FB15_Pos (15U)
5120#define CAN_F8R2_FB15_Msk (0x1UL << CAN_F8R2_FB15_Pos)
5121#define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk
5122#define CAN_F8R2_FB16_Pos (16U)
5123#define CAN_F8R2_FB16_Msk (0x1UL << CAN_F8R2_FB16_Pos)
5124#define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk
5125#define CAN_F8R2_FB17_Pos (17U)
5126#define CAN_F8R2_FB17_Msk (0x1UL << CAN_F8R2_FB17_Pos)
5127#define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk
5128#define CAN_F8R2_FB18_Pos (18U)
5129#define CAN_F8R2_FB18_Msk (0x1UL << CAN_F8R2_FB18_Pos)
5130#define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk
5131#define CAN_F8R2_FB19_Pos (19U)
5132#define CAN_F8R2_FB19_Msk (0x1UL << CAN_F8R2_FB19_Pos)
5133#define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk
5134#define CAN_F8R2_FB20_Pos (20U)
5135#define CAN_F8R2_FB20_Msk (0x1UL << CAN_F8R2_FB20_Pos)
5136#define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk
5137#define CAN_F8R2_FB21_Pos (21U)
5138#define CAN_F8R2_FB21_Msk (0x1UL << CAN_F8R2_FB21_Pos)
5139#define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk
5140#define CAN_F8R2_FB22_Pos (22U)
5141#define CAN_F8R2_FB22_Msk (0x1UL << CAN_F8R2_FB22_Pos)
5142#define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk
5143#define CAN_F8R2_FB23_Pos (23U)
5144#define CAN_F8R2_FB23_Msk (0x1UL << CAN_F8R2_FB23_Pos)
5145#define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk
5146#define CAN_F8R2_FB24_Pos (24U)
5147#define CAN_F8R2_FB24_Msk (0x1UL << CAN_F8R2_FB24_Pos)
5148#define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk
5149#define CAN_F8R2_FB25_Pos (25U)
5150#define CAN_F8R2_FB25_Msk (0x1UL << CAN_F8R2_FB25_Pos)
5151#define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk
5152#define CAN_F8R2_FB26_Pos (26U)
5153#define CAN_F8R2_FB26_Msk (0x1UL << CAN_F8R2_FB26_Pos)
5154#define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk
5155#define CAN_F8R2_FB27_Pos (27U)
5156#define CAN_F8R2_FB27_Msk (0x1UL << CAN_F8R2_FB27_Pos)
5157#define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk
5158#define CAN_F8R2_FB28_Pos (28U)
5159#define CAN_F8R2_FB28_Msk (0x1UL << CAN_F8R2_FB28_Pos)
5160#define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk
5161#define CAN_F8R2_FB29_Pos (29U)
5162#define CAN_F8R2_FB29_Msk (0x1UL << CAN_F8R2_FB29_Pos)
5163#define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk
5164#define CAN_F8R2_FB30_Pos (30U)
5165#define CAN_F8R2_FB30_Msk (0x1UL << CAN_F8R2_FB30_Pos)
5166#define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk
5167#define CAN_F8R2_FB31_Pos (31U)
5168#define CAN_F8R2_FB31_Msk (0x1UL << CAN_F8R2_FB31_Pos)
5169#define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk
5171/******************* Bit definition for CAN_F9R2 register *******************/
5172#define CAN_F9R2_FB0_Pos (0U)
5173#define CAN_F9R2_FB0_Msk (0x1UL << CAN_F9R2_FB0_Pos)
5174#define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk
5175#define CAN_F9R2_FB1_Pos (1U)
5176#define CAN_F9R2_FB1_Msk (0x1UL << CAN_F9R2_FB1_Pos)
5177#define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk
5178#define CAN_F9R2_FB2_Pos (2U)
5179#define CAN_F9R2_FB2_Msk (0x1UL << CAN_F9R2_FB2_Pos)
5180#define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk
5181#define CAN_F9R2_FB3_Pos (3U)
5182#define CAN_F9R2_FB3_Msk (0x1UL << CAN_F9R2_FB3_Pos)
5183#define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk
5184#define CAN_F9R2_FB4_Pos (4U)
5185#define CAN_F9R2_FB4_Msk (0x1UL << CAN_F9R2_FB4_Pos)
5186#define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk
5187#define CAN_F9R2_FB5_Pos (5U)
5188#define CAN_F9R2_FB5_Msk (0x1UL << CAN_F9R2_FB5_Pos)
5189#define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk
5190#define CAN_F9R2_FB6_Pos (6U)
5191#define CAN_F9R2_FB6_Msk (0x1UL << CAN_F9R2_FB6_Pos)
5192#define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk
5193#define CAN_F9R2_FB7_Pos (7U)
5194#define CAN_F9R2_FB7_Msk (0x1UL << CAN_F9R2_FB7_Pos)
5195#define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk
5196#define CAN_F9R2_FB8_Pos (8U)
5197#define CAN_F9R2_FB8_Msk (0x1UL << CAN_F9R2_FB8_Pos)
5198#define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk
5199#define CAN_F9R2_FB9_Pos (9U)
5200#define CAN_F9R2_FB9_Msk (0x1UL << CAN_F9R2_FB9_Pos)
5201#define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk
5202#define CAN_F9R2_FB10_Pos (10U)
5203#define CAN_F9R2_FB10_Msk (0x1UL << CAN_F9R2_FB10_Pos)
5204#define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk
5205#define CAN_F9R2_FB11_Pos (11U)
5206#define CAN_F9R2_FB11_Msk (0x1UL << CAN_F9R2_FB11_Pos)
5207#define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk
5208#define CAN_F9R2_FB12_Pos (12U)
5209#define CAN_F9R2_FB12_Msk (0x1UL << CAN_F9R2_FB12_Pos)
5210#define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk
5211#define CAN_F9R2_FB13_Pos (13U)
5212#define CAN_F9R2_FB13_Msk (0x1UL << CAN_F9R2_FB13_Pos)
5213#define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk
5214#define CAN_F9R2_FB14_Pos (14U)
5215#define CAN_F9R2_FB14_Msk (0x1UL << CAN_F9R2_FB14_Pos)
5216#define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk
5217#define CAN_F9R2_FB15_Pos (15U)
5218#define CAN_F9R2_FB15_Msk (0x1UL << CAN_F9R2_FB15_Pos)
5219#define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk
5220#define CAN_F9R2_FB16_Pos (16U)
5221#define CAN_F9R2_FB16_Msk (0x1UL << CAN_F9R2_FB16_Pos)
5222#define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk
5223#define CAN_F9R2_FB17_Pos (17U)
5224#define CAN_F9R2_FB17_Msk (0x1UL << CAN_F9R2_FB17_Pos)
5225#define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk
5226#define CAN_F9R2_FB18_Pos (18U)
5227#define CAN_F9R2_FB18_Msk (0x1UL << CAN_F9R2_FB18_Pos)
5228#define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk
5229#define CAN_F9R2_FB19_Pos (19U)
5230#define CAN_F9R2_FB19_Msk (0x1UL << CAN_F9R2_FB19_Pos)
5231#define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk
5232#define CAN_F9R2_FB20_Pos (20U)
5233#define CAN_F9R2_FB20_Msk (0x1UL << CAN_F9R2_FB20_Pos)
5234#define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk
5235#define CAN_F9R2_FB21_Pos (21U)
5236#define CAN_F9R2_FB21_Msk (0x1UL << CAN_F9R2_FB21_Pos)
5237#define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk
5238#define CAN_F9R2_FB22_Pos (22U)
5239#define CAN_F9R2_FB22_Msk (0x1UL << CAN_F9R2_FB22_Pos)
5240#define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk
5241#define CAN_F9R2_FB23_Pos (23U)
5242#define CAN_F9R2_FB23_Msk (0x1UL << CAN_F9R2_FB23_Pos)
5243#define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk
5244#define CAN_F9R2_FB24_Pos (24U)
5245#define CAN_F9R2_FB24_Msk (0x1UL << CAN_F9R2_FB24_Pos)
5246#define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk
5247#define CAN_F9R2_FB25_Pos (25U)
5248#define CAN_F9R2_FB25_Msk (0x1UL << CAN_F9R2_FB25_Pos)
5249#define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk
5250#define CAN_F9R2_FB26_Pos (26U)
5251#define CAN_F9R2_FB26_Msk (0x1UL << CAN_F9R2_FB26_Pos)
5252#define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk
5253#define CAN_F9R2_FB27_Pos (27U)
5254#define CAN_F9R2_FB27_Msk (0x1UL << CAN_F9R2_FB27_Pos)
5255#define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk
5256#define CAN_F9R2_FB28_Pos (28U)
5257#define CAN_F9R2_FB28_Msk (0x1UL << CAN_F9R2_FB28_Pos)
5258#define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk
5259#define CAN_F9R2_FB29_Pos (29U)
5260#define CAN_F9R2_FB29_Msk (0x1UL << CAN_F9R2_FB29_Pos)
5261#define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk
5262#define CAN_F9R2_FB30_Pos (30U)
5263#define CAN_F9R2_FB30_Msk (0x1UL << CAN_F9R2_FB30_Pos)
5264#define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk
5265#define CAN_F9R2_FB31_Pos (31U)
5266#define CAN_F9R2_FB31_Msk (0x1UL << CAN_F9R2_FB31_Pos)
5267#define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk
5269/******************* Bit definition for CAN_F10R2 register ******************/
5270#define CAN_F10R2_FB0_Pos (0U)
5271#define CAN_F10R2_FB0_Msk (0x1UL << CAN_F10R2_FB0_Pos)
5272#define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk
5273#define CAN_F10R2_FB1_Pos (1U)
5274#define CAN_F10R2_FB1_Msk (0x1UL << CAN_F10R2_FB1_Pos)
5275#define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk
5276#define CAN_F10R2_FB2_Pos (2U)
5277#define CAN_F10R2_FB2_Msk (0x1UL << CAN_F10R2_FB2_Pos)
5278#define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk
5279#define CAN_F10R2_FB3_Pos (3U)
5280#define CAN_F10R2_FB3_Msk (0x1UL << CAN_F10R2_FB3_Pos)
5281#define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk
5282#define CAN_F10R2_FB4_Pos (4U)
5283#define CAN_F10R2_FB4_Msk (0x1UL << CAN_F10R2_FB4_Pos)
5284#define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk
5285#define CAN_F10R2_FB5_Pos (5U)
5286#define CAN_F10R2_FB5_Msk (0x1UL << CAN_F10R2_FB5_Pos)
5287#define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk
5288#define CAN_F10R2_FB6_Pos (6U)
5289#define CAN_F10R2_FB6_Msk (0x1UL << CAN_F10R2_FB6_Pos)
5290#define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk
5291#define CAN_F10R2_FB7_Pos (7U)
5292#define CAN_F10R2_FB7_Msk (0x1UL << CAN_F10R2_FB7_Pos)
5293#define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk
5294#define CAN_F10R2_FB8_Pos (8U)
5295#define CAN_F10R2_FB8_Msk (0x1UL << CAN_F10R2_FB8_Pos)
5296#define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk
5297#define CAN_F10R2_FB9_Pos (9U)
5298#define CAN_F10R2_FB9_Msk (0x1UL << CAN_F10R2_FB9_Pos)
5299#define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk
5300#define CAN_F10R2_FB10_Pos (10U)
5301#define CAN_F10R2_FB10_Msk (0x1UL << CAN_F10R2_FB10_Pos)
5302#define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk
5303#define CAN_F10R2_FB11_Pos (11U)
5304#define CAN_F10R2_FB11_Msk (0x1UL << CAN_F10R2_FB11_Pos)
5305#define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk
5306#define CAN_F10R2_FB12_Pos (12U)
5307#define CAN_F10R2_FB12_Msk (0x1UL << CAN_F10R2_FB12_Pos)
5308#define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk
5309#define CAN_F10R2_FB13_Pos (13U)
5310#define CAN_F10R2_FB13_Msk (0x1UL << CAN_F10R2_FB13_Pos)
5311#define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk
5312#define CAN_F10R2_FB14_Pos (14U)
5313#define CAN_F10R2_FB14_Msk (0x1UL << CAN_F10R2_FB14_Pos)
5314#define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk
5315#define CAN_F10R2_FB15_Pos (15U)
5316#define CAN_F10R2_FB15_Msk (0x1UL << CAN_F10R2_FB15_Pos)
5317#define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk
5318#define CAN_F10R2_FB16_Pos (16U)
5319#define CAN_F10R2_FB16_Msk (0x1UL << CAN_F10R2_FB16_Pos)
5320#define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk
5321#define CAN_F10R2_FB17_Pos (17U)
5322#define CAN_F10R2_FB17_Msk (0x1UL << CAN_F10R2_FB17_Pos)
5323#define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk
5324#define CAN_F10R2_FB18_Pos (18U)
5325#define CAN_F10R2_FB18_Msk (0x1UL << CAN_F10R2_FB18_Pos)
5326#define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk
5327#define CAN_F10R2_FB19_Pos (19U)
5328#define CAN_F10R2_FB19_Msk (0x1UL << CAN_F10R2_FB19_Pos)
5329#define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk
5330#define CAN_F10R2_FB20_Pos (20U)
5331#define CAN_F10R2_FB20_Msk (0x1UL << CAN_F10R2_FB20_Pos)
5332#define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk
5333#define CAN_F10R2_FB21_Pos (21U)
5334#define CAN_F10R2_FB21_Msk (0x1UL << CAN_F10R2_FB21_Pos)
5335#define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk
5336#define CAN_F10R2_FB22_Pos (22U)
5337#define CAN_F10R2_FB22_Msk (0x1UL << CAN_F10R2_FB22_Pos)
5338#define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk
5339#define CAN_F10R2_FB23_Pos (23U)
5340#define CAN_F10R2_FB23_Msk (0x1UL << CAN_F10R2_FB23_Pos)
5341#define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk
5342#define CAN_F10R2_FB24_Pos (24U)
5343#define CAN_F10R2_FB24_Msk (0x1UL << CAN_F10R2_FB24_Pos)
5344#define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk
5345#define CAN_F10R2_FB25_Pos (25U)
5346#define CAN_F10R2_FB25_Msk (0x1UL << CAN_F10R2_FB25_Pos)
5347#define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk
5348#define CAN_F10R2_FB26_Pos (26U)
5349#define CAN_F10R2_FB26_Msk (0x1UL << CAN_F10R2_FB26_Pos)
5350#define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk
5351#define CAN_F10R2_FB27_Pos (27U)
5352#define CAN_F10R2_FB27_Msk (0x1UL << CAN_F10R2_FB27_Pos)
5353#define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk
5354#define CAN_F10R2_FB28_Pos (28U)
5355#define CAN_F10R2_FB28_Msk (0x1UL << CAN_F10R2_FB28_Pos)
5356#define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk
5357#define CAN_F10R2_FB29_Pos (29U)
5358#define CAN_F10R2_FB29_Msk (0x1UL << CAN_F10R2_FB29_Pos)
5359#define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk
5360#define CAN_F10R2_FB30_Pos (30U)
5361#define CAN_F10R2_FB30_Msk (0x1UL << CAN_F10R2_FB30_Pos)
5362#define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk
5363#define CAN_F10R2_FB31_Pos (31U)
5364#define CAN_F10R2_FB31_Msk (0x1UL << CAN_F10R2_FB31_Pos)
5365#define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk
5367/******************* Bit definition for CAN_F11R2 register ******************/
5368#define CAN_F11R2_FB0_Pos (0U)
5369#define CAN_F11R2_FB0_Msk (0x1UL << CAN_F11R2_FB0_Pos)
5370#define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk
5371#define CAN_F11R2_FB1_Pos (1U)
5372#define CAN_F11R2_FB1_Msk (0x1UL << CAN_F11R2_FB1_Pos)
5373#define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk
5374#define CAN_F11R2_FB2_Pos (2U)
5375#define CAN_F11R2_FB2_Msk (0x1UL << CAN_F11R2_FB2_Pos)
5376#define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk
5377#define CAN_F11R2_FB3_Pos (3U)
5378#define CAN_F11R2_FB3_Msk (0x1UL << CAN_F11R2_FB3_Pos)
5379#define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk
5380#define CAN_F11R2_FB4_Pos (4U)
5381#define CAN_F11R2_FB4_Msk (0x1UL << CAN_F11R2_FB4_Pos)
5382#define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk
5383#define CAN_F11R2_FB5_Pos (5U)
5384#define CAN_F11R2_FB5_Msk (0x1UL << CAN_F11R2_FB5_Pos)
5385#define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk
5386#define CAN_F11R2_FB6_Pos (6U)
5387#define CAN_F11R2_FB6_Msk (0x1UL << CAN_F11R2_FB6_Pos)
5388#define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk
5389#define CAN_F11R2_FB7_Pos (7U)
5390#define CAN_F11R2_FB7_Msk (0x1UL << CAN_F11R2_FB7_Pos)
5391#define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk
5392#define CAN_F11R2_FB8_Pos (8U)
5393#define CAN_F11R2_FB8_Msk (0x1UL << CAN_F11R2_FB8_Pos)
5394#define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk
5395#define CAN_F11R2_FB9_Pos (9U)
5396#define CAN_F11R2_FB9_Msk (0x1UL << CAN_F11R2_FB9_Pos)
5397#define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk
5398#define CAN_F11R2_FB10_Pos (10U)
5399#define CAN_F11R2_FB10_Msk (0x1UL << CAN_F11R2_FB10_Pos)
5400#define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk
5401#define CAN_F11R2_FB11_Pos (11U)
5402#define CAN_F11R2_FB11_Msk (0x1UL << CAN_F11R2_FB11_Pos)
5403#define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk
5404#define CAN_F11R2_FB12_Pos (12U)
5405#define CAN_F11R2_FB12_Msk (0x1UL << CAN_F11R2_FB12_Pos)
5406#define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk
5407#define CAN_F11R2_FB13_Pos (13U)
5408#define CAN_F11R2_FB13_Msk (0x1UL << CAN_F11R2_FB13_Pos)
5409#define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk
5410#define CAN_F11R2_FB14_Pos (14U)
5411#define CAN_F11R2_FB14_Msk (0x1UL << CAN_F11R2_FB14_Pos)
5412#define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk
5413#define CAN_F11R2_FB15_Pos (15U)
5414#define CAN_F11R2_FB15_Msk (0x1UL << CAN_F11R2_FB15_Pos)
5415#define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk
5416#define CAN_F11R2_FB16_Pos (16U)
5417#define CAN_F11R2_FB16_Msk (0x1UL << CAN_F11R2_FB16_Pos)
5418#define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk
5419#define CAN_F11R2_FB17_Pos (17U)
5420#define CAN_F11R2_FB17_Msk (0x1UL << CAN_F11R2_FB17_Pos)
5421#define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk
5422#define CAN_F11R2_FB18_Pos (18U)
5423#define CAN_F11R2_FB18_Msk (0x1UL << CAN_F11R2_FB18_Pos)
5424#define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk
5425#define CAN_F11R2_FB19_Pos (19U)
5426#define CAN_F11R2_FB19_Msk (0x1UL << CAN_F11R2_FB19_Pos)
5427#define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk
5428#define CAN_F11R2_FB20_Pos (20U)
5429#define CAN_F11R2_FB20_Msk (0x1UL << CAN_F11R2_FB20_Pos)
5430#define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk
5431#define CAN_F11R2_FB21_Pos (21U)
5432#define CAN_F11R2_FB21_Msk (0x1UL << CAN_F11R2_FB21_Pos)
5433#define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk
5434#define CAN_F11R2_FB22_Pos (22U)
5435#define CAN_F11R2_FB22_Msk (0x1UL << CAN_F11R2_FB22_Pos)
5436#define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk
5437#define CAN_F11R2_FB23_Pos (23U)
5438#define CAN_F11R2_FB23_Msk (0x1UL << CAN_F11R2_FB23_Pos)
5439#define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk
5440#define CAN_F11R2_FB24_Pos (24U)
5441#define CAN_F11R2_FB24_Msk (0x1UL << CAN_F11R2_FB24_Pos)
5442#define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk
5443#define CAN_F11R2_FB25_Pos (25U)
5444#define CAN_F11R2_FB25_Msk (0x1UL << CAN_F11R2_FB25_Pos)
5445#define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk
5446#define CAN_F11R2_FB26_Pos (26U)
5447#define CAN_F11R2_FB26_Msk (0x1UL << CAN_F11R2_FB26_Pos)
5448#define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk
5449#define CAN_F11R2_FB27_Pos (27U)
5450#define CAN_F11R2_FB27_Msk (0x1UL << CAN_F11R2_FB27_Pos)
5451#define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk
5452#define CAN_F11R2_FB28_Pos (28U)
5453#define CAN_F11R2_FB28_Msk (0x1UL << CAN_F11R2_FB28_Pos)
5454#define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk
5455#define CAN_F11R2_FB29_Pos (29U)
5456#define CAN_F11R2_FB29_Msk (0x1UL << CAN_F11R2_FB29_Pos)
5457#define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk
5458#define CAN_F11R2_FB30_Pos (30U)
5459#define CAN_F11R2_FB30_Msk (0x1UL << CAN_F11R2_FB30_Pos)
5460#define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk
5461#define CAN_F11R2_FB31_Pos (31U)
5462#define CAN_F11R2_FB31_Msk (0x1UL << CAN_F11R2_FB31_Pos)
5463#define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk
5465/******************* Bit definition for CAN_F12R2 register ******************/
5466#define CAN_F12R2_FB0_Pos (0U)
5467#define CAN_F12R2_FB0_Msk (0x1UL << CAN_F12R2_FB0_Pos)
5468#define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk
5469#define CAN_F12R2_FB1_Pos (1U)
5470#define CAN_F12R2_FB1_Msk (0x1UL << CAN_F12R2_FB1_Pos)
5471#define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk
5472#define CAN_F12R2_FB2_Pos (2U)
5473#define CAN_F12R2_FB2_Msk (0x1UL << CAN_F12R2_FB2_Pos)
5474#define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk
5475#define CAN_F12R2_FB3_Pos (3U)
5476#define CAN_F12R2_FB3_Msk (0x1UL << CAN_F12R2_FB3_Pos)
5477#define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk
5478#define CAN_F12R2_FB4_Pos (4U)
5479#define CAN_F12R2_FB4_Msk (0x1UL << CAN_F12R2_FB4_Pos)
5480#define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk
5481#define CAN_F12R2_FB5_Pos (5U)
5482#define CAN_F12R2_FB5_Msk (0x1UL << CAN_F12R2_FB5_Pos)
5483#define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk
5484#define CAN_F12R2_FB6_Pos (6U)
5485#define CAN_F12R2_FB6_Msk (0x1UL << CAN_F12R2_FB6_Pos)
5486#define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk
5487#define CAN_F12R2_FB7_Pos (7U)
5488#define CAN_F12R2_FB7_Msk (0x1UL << CAN_F12R2_FB7_Pos)
5489#define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk
5490#define CAN_F12R2_FB8_Pos (8U)
5491#define CAN_F12R2_FB8_Msk (0x1UL << CAN_F12R2_FB8_Pos)
5492#define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk
5493#define CAN_F12R2_FB9_Pos (9U)
5494#define CAN_F12R2_FB9_Msk (0x1UL << CAN_F12R2_FB9_Pos)
5495#define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk
5496#define CAN_F12R2_FB10_Pos (10U)
5497#define CAN_F12R2_FB10_Msk (0x1UL << CAN_F12R2_FB10_Pos)
5498#define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk
5499#define CAN_F12R2_FB11_Pos (11U)
5500#define CAN_F12R2_FB11_Msk (0x1UL << CAN_F12R2_FB11_Pos)
5501#define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk
5502#define CAN_F12R2_FB12_Pos (12U)
5503#define CAN_F12R2_FB12_Msk (0x1UL << CAN_F12R2_FB12_Pos)
5504#define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk
5505#define CAN_F12R2_FB13_Pos (13U)
5506#define CAN_F12R2_FB13_Msk (0x1UL << CAN_F12R2_FB13_Pos)
5507#define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk
5508#define CAN_F12R2_FB14_Pos (14U)
5509#define CAN_F12R2_FB14_Msk (0x1UL << CAN_F12R2_FB14_Pos)
5510#define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk
5511#define CAN_F12R2_FB15_Pos (15U)
5512#define CAN_F12R2_FB15_Msk (0x1UL << CAN_F12R2_FB15_Pos)
5513#define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk
5514#define CAN_F12R2_FB16_Pos (16U)
5515#define CAN_F12R2_FB16_Msk (0x1UL << CAN_F12R2_FB16_Pos)
5516#define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk
5517#define CAN_F12R2_FB17_Pos (17U)
5518#define CAN_F12R2_FB17_Msk (0x1UL << CAN_F12R2_FB17_Pos)
5519#define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk
5520#define CAN_F12R2_FB18_Pos (18U)
5521#define CAN_F12R2_FB18_Msk (0x1UL << CAN_F12R2_FB18_Pos)
5522#define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk
5523#define CAN_F12R2_FB19_Pos (19U)
5524#define CAN_F12R2_FB19_Msk (0x1UL << CAN_F12R2_FB19_Pos)
5525#define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk
5526#define CAN_F12R2_FB20_Pos (20U)
5527#define CAN_F12R2_FB20_Msk (0x1UL << CAN_F12R2_FB20_Pos)
5528#define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk
5529#define CAN_F12R2_FB21_Pos (21U)
5530#define CAN_F12R2_FB21_Msk (0x1UL << CAN_F12R2_FB21_Pos)
5531#define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk
5532#define CAN_F12R2_FB22_Pos (22U)
5533#define CAN_F12R2_FB22_Msk (0x1UL << CAN_F12R2_FB22_Pos)
5534#define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk
5535#define CAN_F12R2_FB23_Pos (23U)
5536#define CAN_F12R2_FB23_Msk (0x1UL << CAN_F12R2_FB23_Pos)
5537#define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk
5538#define CAN_F12R2_FB24_Pos (24U)
5539#define CAN_F12R2_FB24_Msk (0x1UL << CAN_F12R2_FB24_Pos)
5540#define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk
5541#define CAN_F12R2_FB25_Pos (25U)
5542#define CAN_F12R2_FB25_Msk (0x1UL << CAN_F12R2_FB25_Pos)
5543#define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk
5544#define CAN_F12R2_FB26_Pos (26U)
5545#define CAN_F12R2_FB26_Msk (0x1UL << CAN_F12R2_FB26_Pos)
5546#define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk
5547#define CAN_F12R2_FB27_Pos (27U)
5548#define CAN_F12R2_FB27_Msk (0x1UL << CAN_F12R2_FB27_Pos)
5549#define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk
5550#define CAN_F12R2_FB28_Pos (28U)
5551#define CAN_F12R2_FB28_Msk (0x1UL << CAN_F12R2_FB28_Pos)
5552#define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk
5553#define CAN_F12R2_FB29_Pos (29U)
5554#define CAN_F12R2_FB29_Msk (0x1UL << CAN_F12R2_FB29_Pos)
5555#define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk
5556#define CAN_F12R2_FB30_Pos (30U)
5557#define CAN_F12R2_FB30_Msk (0x1UL << CAN_F12R2_FB30_Pos)
5558#define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk
5559#define CAN_F12R2_FB31_Pos (31U)
5560#define CAN_F12R2_FB31_Msk (0x1UL << CAN_F12R2_FB31_Pos)
5561#define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk
5563/******************* Bit definition for CAN_F13R2 register ******************/
5564#define CAN_F13R2_FB0_Pos (0U)
5565#define CAN_F13R2_FB0_Msk (0x1UL << CAN_F13R2_FB0_Pos)
5566#define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk
5567#define CAN_F13R2_FB1_Pos (1U)
5568#define CAN_F13R2_FB1_Msk (0x1UL << CAN_F13R2_FB1_Pos)
5569#define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk
5570#define CAN_F13R2_FB2_Pos (2U)
5571#define CAN_F13R2_FB2_Msk (0x1UL << CAN_F13R2_FB2_Pos)
5572#define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk
5573#define CAN_F13R2_FB3_Pos (3U)
5574#define CAN_F13R2_FB3_Msk (0x1UL << CAN_F13R2_FB3_Pos)
5575#define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk
5576#define CAN_F13R2_FB4_Pos (4U)
5577#define CAN_F13R2_FB4_Msk (0x1UL << CAN_F13R2_FB4_Pos)
5578#define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk
5579#define CAN_F13R2_FB5_Pos (5U)
5580#define CAN_F13R2_FB5_Msk (0x1UL << CAN_F13R2_FB5_Pos)
5581#define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk
5582#define CAN_F13R2_FB6_Pos (6U)
5583#define CAN_F13R2_FB6_Msk (0x1UL << CAN_F13R2_FB6_Pos)
5584#define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk
5585#define CAN_F13R2_FB7_Pos (7U)
5586#define CAN_F13R2_FB7_Msk (0x1UL << CAN_F13R2_FB7_Pos)
5587#define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk
5588#define CAN_F13R2_FB8_Pos (8U)
5589#define CAN_F13R2_FB8_Msk (0x1UL << CAN_F13R2_FB8_Pos)
5590#define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk
5591#define CAN_F13R2_FB9_Pos (9U)
5592#define CAN_F13R2_FB9_Msk (0x1UL << CAN_F13R2_FB9_Pos)
5593#define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk
5594#define CAN_F13R2_FB10_Pos (10U)
5595#define CAN_F13R2_FB10_Msk (0x1UL << CAN_F13R2_FB10_Pos)
5596#define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk
5597#define CAN_F13R2_FB11_Pos (11U)
5598#define CAN_F13R2_FB11_Msk (0x1UL << CAN_F13R2_FB11_Pos)
5599#define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk
5600#define CAN_F13R2_FB12_Pos (12U)
5601#define CAN_F13R2_FB12_Msk (0x1UL << CAN_F13R2_FB12_Pos)
5602#define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk
5603#define CAN_F13R2_FB13_Pos (13U)
5604#define CAN_F13R2_FB13_Msk (0x1UL << CAN_F13R2_FB13_Pos)
5605#define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk
5606#define CAN_F13R2_FB14_Pos (14U)
5607#define CAN_F13R2_FB14_Msk (0x1UL << CAN_F13R2_FB14_Pos)
5608#define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk
5609#define CAN_F13R2_FB15_Pos (15U)
5610#define CAN_F13R2_FB15_Msk (0x1UL << CAN_F13R2_FB15_Pos)
5611#define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk
5612#define CAN_F13R2_FB16_Pos (16U)
5613#define CAN_F13R2_FB16_Msk (0x1UL << CAN_F13R2_FB16_Pos)
5614#define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk
5615#define CAN_F13R2_FB17_Pos (17U)
5616#define CAN_F13R2_FB17_Msk (0x1UL << CAN_F13R2_FB17_Pos)
5617#define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk
5618#define CAN_F13R2_FB18_Pos (18U)
5619#define CAN_F13R2_FB18_Msk (0x1UL << CAN_F13R2_FB18_Pos)
5620#define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk
5621#define CAN_F13R2_FB19_Pos (19U)
5622#define CAN_F13R2_FB19_Msk (0x1UL << CAN_F13R2_FB19_Pos)
5623#define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk
5624#define CAN_F13R2_FB20_Pos (20U)
5625#define CAN_F13R2_FB20_Msk (0x1UL << CAN_F13R2_FB20_Pos)
5626#define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk
5627#define CAN_F13R2_FB21_Pos (21U)
5628#define CAN_F13R2_FB21_Msk (0x1UL << CAN_F13R2_FB21_Pos)
5629#define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk
5630#define CAN_F13R2_FB22_Pos (22U)
5631#define CAN_F13R2_FB22_Msk (0x1UL << CAN_F13R2_FB22_Pos)
5632#define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk
5633#define CAN_F13R2_FB23_Pos (23U)
5634#define CAN_F13R2_FB23_Msk (0x1UL << CAN_F13R2_FB23_Pos)
5635#define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk
5636#define CAN_F13R2_FB24_Pos (24U)
5637#define CAN_F13R2_FB24_Msk (0x1UL << CAN_F13R2_FB24_Pos)
5638#define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk
5639#define CAN_F13R2_FB25_Pos (25U)
5640#define CAN_F13R2_FB25_Msk (0x1UL << CAN_F13R2_FB25_Pos)
5641#define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk
5642#define CAN_F13R2_FB26_Pos (26U)
5643#define CAN_F13R2_FB26_Msk (0x1UL << CAN_F13R2_FB26_Pos)
5644#define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk
5645#define CAN_F13R2_FB27_Pos (27U)
5646#define CAN_F13R2_FB27_Msk (0x1UL << CAN_F13R2_FB27_Pos)
5647#define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk
5648#define CAN_F13R2_FB28_Pos (28U)
5649#define CAN_F13R2_FB28_Msk (0x1UL << CAN_F13R2_FB28_Pos)
5650#define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk
5651#define CAN_F13R2_FB29_Pos (29U)
5652#define CAN_F13R2_FB29_Msk (0x1UL << CAN_F13R2_FB29_Pos)
5653#define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk
5654#define CAN_F13R2_FB30_Pos (30U)
5655#define CAN_F13R2_FB30_Msk (0x1UL << CAN_F13R2_FB30_Pos)
5656#define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk
5657#define CAN_F13R2_FB31_Pos (31U)
5658#define CAN_F13R2_FB31_Msk (0x1UL << CAN_F13R2_FB31_Pos)
5659#define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk
5661/******************************************************************************/
5662/* */
5663/* CRC calculation unit */
5664/* */
5665/******************************************************************************/
5666/******************* Bit definition for CRC_DR register *********************/
5667#define CRC_DR_DR_Pos (0U)
5668#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos)
5669#define CRC_DR_DR CRC_DR_DR_Msk
5671/******************* Bit definition for CRC_IDR register ********************/
5672#define CRC_IDR_IDR_Pos (0U)
5673#define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos)
5674#define CRC_IDR_IDR CRC_IDR_IDR_Msk
5676/******************** Bit definition for CRC_CR register ********************/
5677#define CRC_CR_RESET_Pos (0U)
5678#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos)
5679#define CRC_CR_RESET CRC_CR_RESET_Msk
5680#define CRC_CR_POLYSIZE_Pos (3U)
5681#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos)
5682#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk
5683#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos)
5684#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos)
5685#define CRC_CR_REV_IN_Pos (5U)
5686#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos)
5687#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk
5688#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos)
5689#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos)
5690#define CRC_CR_REV_OUT_Pos (7U)
5691#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos)
5692#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk
5694/******************* Bit definition for CRC_INIT register *******************/
5695#define CRC_INIT_INIT_Pos (0U)
5696#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)
5697#define CRC_INIT_INIT CRC_INIT_INIT_Msk
5699/******************* Bit definition for CRC_POL register ********************/
5700#define CRC_POL_POL_Pos (0U)
5701#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos)
5702#define CRC_POL_POL CRC_POL_POL_Msk
5704/******************************************************************************/
5705/* */
5706/* CRS Clock Recovery System */
5707/******************************************************************************/
5708
5709/******************* Bit definition for CRS_CR register *********************/
5710#define CRS_CR_SYNCOKIE_Pos (0U)
5711#define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos)
5712#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk
5713#define CRS_CR_SYNCWARNIE_Pos (1U)
5714#define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos)
5715#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk
5716#define CRS_CR_ERRIE_Pos (2U)
5717#define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos)
5718#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk
5719#define CRS_CR_ESYNCIE_Pos (3U)
5720#define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos)
5721#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk
5722#define CRS_CR_CEN_Pos (5U)
5723#define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos)
5724#define CRS_CR_CEN CRS_CR_CEN_Msk
5725#define CRS_CR_AUTOTRIMEN_Pos (6U)
5726#define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos)
5727#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk
5728#define CRS_CR_SWSYNC_Pos (7U)
5729#define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos)
5730#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk
5731#define CRS_CR_TRIM_Pos (8U)
5732#define CRS_CR_TRIM_Msk (0x3FUL << CRS_CR_TRIM_Pos)
5733#define CRS_CR_TRIM CRS_CR_TRIM_Msk
5734#define CRS_CR_TRIM_0 (0x01UL << CRS_CR_TRIM_Pos)
5735#define CRS_CR_TRIM_1 (0x02UL << CRS_CR_TRIM_Pos)
5736#define CRS_CR_TRIM_2 (0x04UL << CRS_CR_TRIM_Pos)
5737#define CRS_CR_TRIM_3 (0x08UL << CRS_CR_TRIM_Pos)
5738#define CRS_CR_TRIM_4 (0x10UL << CRS_CR_TRIM_Pos)
5739#define CRS_CR_TRIM_5 (0x20UL << CRS_CR_TRIM_Pos)
5741/******************* Bit definition for CRS_CFGR register *********************/
5742#define CRS_CFGR_RELOAD_Pos (0U)
5743#define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos)
5744#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk
5745#define CRS_CFGR_FELIM_Pos (16U)
5746#define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos)
5747#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk
5749#define CRS_CFGR_SYNCDIV_Pos (24U)
5750#define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos)
5751#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk
5752#define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos)
5753#define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos)
5754#define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos)
5756#define CRS_CFGR_SYNCSRC_Pos (28U)
5757#define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos)
5758#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk
5759#define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos)
5760#define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos)
5762#define CRS_CFGR_SYNCPOL_Pos (31U)
5763#define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos)
5764#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk
5766/******************* Bit definition for CRS_ISR register *********************/
5767#define CRS_ISR_SYNCOKF_Pos (0U)
5768#define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos)
5769#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk
5770#define CRS_ISR_SYNCWARNF_Pos (1U)
5771#define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos)
5772#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk
5773#define CRS_ISR_ERRF_Pos (2U)
5774#define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos)
5775#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk
5776#define CRS_ISR_ESYNCF_Pos (3U)
5777#define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos)
5778#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk
5779#define CRS_ISR_SYNCERR_Pos (8U)
5780#define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos)
5781#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk
5782#define CRS_ISR_SYNCMISS_Pos (9U)
5783#define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos)
5784#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk
5785#define CRS_ISR_TRIMOVF_Pos (10U)
5786#define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos)
5787#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk
5788#define CRS_ISR_FEDIR_Pos (15U)
5789#define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos)
5790#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk
5791#define CRS_ISR_FECAP_Pos (16U)
5792#define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos)
5793#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk
5795/******************* Bit definition for CRS_ICR register *********************/
5796#define CRS_ICR_SYNCOKC_Pos (0U)
5797#define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos)
5798#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk
5799#define CRS_ICR_SYNCWARNC_Pos (1U)
5800#define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos)
5801#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk
5802#define CRS_ICR_ERRC_Pos (2U)
5803#define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos)
5804#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk
5805#define CRS_ICR_ESYNCC_Pos (3U)
5806#define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos)
5807#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk
5809/******************************************************************************/
5810/* */
5811/* Digital to Analog Converter */
5812/* */
5813/******************************************************************************/
5814/*
5815 * @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)
5816 */
5817#define DAC_CHANNEL2_SUPPORT
5819/******************** Bit definition for DAC_CR register ********************/
5820#define DAC_CR_EN1_Pos (0U)
5821#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos)
5822#define DAC_CR_EN1 DAC_CR_EN1_Msk
5823#define DAC_CR_TEN1_Pos (2U)
5824#define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos)
5825#define DAC_CR_TEN1 DAC_CR_TEN1_Msk
5827#define DAC_CR_TSEL1_Pos (3U)
5828#define DAC_CR_TSEL1_Msk (0x7UL << DAC_CR_TSEL1_Pos)
5829#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk
5830#define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos)
5831#define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos)
5832#define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos)
5834#define DAC_CR_WAVE1_Pos (6U)
5835#define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos)
5836#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk
5837#define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos)
5838#define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos)
5840#define DAC_CR_MAMP1_Pos (8U)
5841#define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos)
5842#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk
5843#define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos)
5844#define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos)
5845#define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos)
5846#define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos)
5848#define DAC_CR_DMAEN1_Pos (12U)
5849#define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos)
5850#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk
5851#define DAC_CR_DMAUDRIE1_Pos (13U)
5852#define DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos)
5853#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk
5854#define DAC_CR_CEN1_Pos (14U)
5855#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos)
5856#define DAC_CR_CEN1 DAC_CR_CEN1_Msk
5858#define DAC_CR_EN2_Pos (16U)
5859#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos)
5860#define DAC_CR_EN2 DAC_CR_EN2_Msk
5861#define DAC_CR_TEN2_Pos (18U)
5862#define DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos)
5863#define DAC_CR_TEN2 DAC_CR_TEN2_Msk
5865#define DAC_CR_TSEL2_Pos (19U)
5866#define DAC_CR_TSEL2_Msk (0x7UL << DAC_CR_TSEL2_Pos)
5867#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk
5868#define DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos)
5869#define DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos)
5870#define DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos)
5872#define DAC_CR_WAVE2_Pos (22U)
5873#define DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos)
5874#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk
5875#define DAC_CR_WAVE2_0 (0x1UL << DAC_CR_WAVE2_Pos)
5876#define DAC_CR_WAVE2_1 (0x2UL << DAC_CR_WAVE2_Pos)
5878#define DAC_CR_MAMP2_Pos (24U)
5879#define DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos)
5880#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk
5881#define DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos)
5882#define DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos)
5883#define DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos)
5884#define DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos)
5886#define DAC_CR_DMAEN2_Pos (28U)
5887#define DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos)
5888#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk
5889#define DAC_CR_DMAUDRIE2_Pos (29U)
5890#define DAC_CR_DMAUDRIE2_Msk (0x1UL << DAC_CR_DMAUDRIE2_Pos)
5891#define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk
5892#define DAC_CR_CEN2_Pos (30U)
5893#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos)
5894#define DAC_CR_CEN2 DAC_CR_CEN2_Msk
5896/***************** Bit definition for DAC_SWTRIGR register ******************/
5897#define DAC_SWTRIGR_SWTRIG1_Pos (0U)
5898#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)
5899#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk
5900#define DAC_SWTRIGR_SWTRIG2_Pos (1U)
5901#define DAC_SWTRIGR_SWTRIG2_Msk (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)
5902#define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk
5904/***************** Bit definition for DAC_DHR12R1 register ******************/
5905#define DAC_DHR12R1_DACC1DHR_Pos (0U)
5906#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)
5907#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk
5909/***************** Bit definition for DAC_DHR12L1 register ******************/
5910#define DAC_DHR12L1_DACC1DHR_Pos (4U)
5911#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)
5912#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk
5914/****************** Bit definition for DAC_DHR8R1 register ******************/
5915#define DAC_DHR8R1_DACC1DHR_Pos (0U)
5916#define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)
5917#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk
5919/***************** Bit definition for DAC_DHR12R2 register ******************/
5920#define DAC_DHR12R2_DACC2DHR_Pos (0U)
5921#define DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)
5922#define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk
5924/***************** Bit definition for DAC_DHR12L2 register ******************/
5925#define DAC_DHR12L2_DACC2DHR_Pos (4U)
5926#define DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)
5927#define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk
5929/****************** Bit definition for DAC_DHR8R2 register ******************/
5930#define DAC_DHR8R2_DACC2DHR_Pos (0U)
5931#define DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)
5932#define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk
5934/***************** Bit definition for DAC_DHR12RD register ******************/
5935#define DAC_DHR12RD_DACC1DHR_Pos (0U)
5936#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)
5937#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk
5938#define DAC_DHR12RD_DACC2DHR_Pos (16U)
5939#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)
5940#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk
5942/***************** Bit definition for DAC_DHR12LD register ******************/
5943#define DAC_DHR12LD_DACC1DHR_Pos (4U)
5944#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)
5945#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk
5946#define DAC_DHR12LD_DACC2DHR_Pos (20U)
5947#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)
5948#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk
5950/****************** Bit definition for DAC_DHR8RD register ******************/
5951#define DAC_DHR8RD_DACC1DHR_Pos (0U)
5952#define DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)
5953#define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk
5954#define DAC_DHR8RD_DACC2DHR_Pos (8U)
5955#define DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)
5956#define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk
5958/******************* Bit definition for DAC_DOR1 register *******************/
5959#define DAC_DOR1_DACC1DOR_Pos (0U)
5960#define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)
5961#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk
5963/******************* Bit definition for DAC_DOR2 register *******************/
5964#define DAC_DOR2_DACC2DOR_Pos (0U)
5965#define DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)
5966#define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk
5968/******************** Bit definition for DAC_SR register ********************/
5969#define DAC_SR_DMAUDR1_Pos (13U)
5970#define DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos)
5971#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk
5972#define DAC_SR_CAL_FLAG1_Pos (14U)
5973#define DAC_SR_CAL_FLAG1_Msk (0x1UL << DAC_SR_CAL_FLAG1_Pos)
5974#define DAC_SR_CAL_FLAG1 DAC_SR_CAL_FLAG1_Msk
5975#define DAC_SR_BWST1_Pos (15U)
5976#define DAC_SR_BWST1_Msk (0x1UL << DAC_SR_BWST1_Pos)
5977#define DAC_SR_BWST1 DAC_SR_BWST1_Msk
5979#define DAC_SR_DMAUDR2_Pos (29U)
5980#define DAC_SR_DMAUDR2_Msk (0x1UL << DAC_SR_DMAUDR2_Pos)
5981#define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk
5982#define DAC_SR_CAL_FLAG2_Pos (30U)
5983#define DAC_SR_CAL_FLAG2_Msk (0x1UL << DAC_SR_CAL_FLAG2_Pos)
5984#define DAC_SR_CAL_FLAG2 DAC_SR_CAL_FLAG2_Msk
5985#define DAC_SR_BWST2_Pos (31U)
5986#define DAC_SR_BWST2_Msk (0x1UL << DAC_SR_BWST2_Pos)
5987#define DAC_SR_BWST2 DAC_SR_BWST2_Msk
5989/******************* Bit definition for DAC_CCR register ********************/
5990#define DAC_CCR_OTRIM1_Pos (0U)
5991#define DAC_CCR_OTRIM1_Msk (0x1FUL << DAC_CCR_OTRIM1_Pos)
5992#define DAC_CCR_OTRIM1 DAC_CCR_OTRIM1_Msk
5993#define DAC_CCR_OTRIM2_Pos (16U)
5994#define DAC_CCR_OTRIM2_Msk (0x1FUL << DAC_CCR_OTRIM2_Pos)
5995#define DAC_CCR_OTRIM2 DAC_CCR_OTRIM2_Msk
5997/******************* Bit definition for DAC_MCR register *******************/
5998#define DAC_MCR_MODE1_Pos (0U)
5999#define DAC_MCR_MODE1_Msk (0x7UL << DAC_MCR_MODE1_Pos)
6000#define DAC_MCR_MODE1 DAC_MCR_MODE1_Msk
6001#define DAC_MCR_MODE1_0 (0x1UL << DAC_MCR_MODE1_Pos)
6002#define DAC_MCR_MODE1_1 (0x2UL << DAC_MCR_MODE1_Pos)
6003#define DAC_MCR_MODE1_2 (0x4UL << DAC_MCR_MODE1_Pos)
6005#define DAC_MCR_MODE2_Pos (16U)
6006#define DAC_MCR_MODE2_Msk (0x7UL << DAC_MCR_MODE2_Pos)
6007#define DAC_MCR_MODE2 DAC_MCR_MODE2_Msk
6008#define DAC_MCR_MODE2_0 (0x1UL << DAC_MCR_MODE2_Pos)
6009#define DAC_MCR_MODE2_1 (0x2UL << DAC_MCR_MODE2_Pos)
6010#define DAC_MCR_MODE2_2 (0x4UL << DAC_MCR_MODE2_Pos)
6012/****************** Bit definition for DAC_SHSR1 register ******************/
6013#define DAC_SHSR1_TSAMPLE1_Pos (0U)
6014#define DAC_SHSR1_TSAMPLE1_Msk (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos)
6015#define DAC_SHSR1_TSAMPLE1 DAC_SHSR1_TSAMPLE1_Msk
6017/****************** Bit definition for DAC_SHSR2 register ******************/
6018#define DAC_SHSR2_TSAMPLE2_Pos (0U)
6019#define DAC_SHSR2_TSAMPLE2_Msk (0x3FFUL << DAC_SHSR2_TSAMPLE2_Pos)
6020#define DAC_SHSR2_TSAMPLE2 DAC_SHSR2_TSAMPLE2_Msk
6022/****************** Bit definition for DAC_SHHR register ******************/
6023#define DAC_SHHR_THOLD1_Pos (0U)
6024#define DAC_SHHR_THOLD1_Msk (0x3FFUL << DAC_SHHR_THOLD1_Pos)
6025#define DAC_SHHR_THOLD1 DAC_SHHR_THOLD1_Msk
6026#define DAC_SHHR_THOLD2_Pos (16U)
6027#define DAC_SHHR_THOLD2_Msk (0x3FFUL << DAC_SHHR_THOLD2_Pos)
6028#define DAC_SHHR_THOLD2 DAC_SHHR_THOLD2_Msk
6030/****************** Bit definition for DAC_SHRR register ******************/
6031#define DAC_SHRR_TREFRESH1_Pos (0U)
6032#define DAC_SHRR_TREFRESH1_Msk (0xFFUL << DAC_SHRR_TREFRESH1_Pos)
6033#define DAC_SHRR_TREFRESH1 DAC_SHRR_TREFRESH1_Msk
6034#define DAC_SHRR_TREFRESH2_Pos (16U)
6035#define DAC_SHRR_TREFRESH2_Msk (0xFFUL << DAC_SHRR_TREFRESH2_Pos)
6036#define DAC_SHRR_TREFRESH2 DAC_SHRR_TREFRESH2_Msk
6038/******************************************************************************/
6039/* */
6040/* DMA Controller (DMA) */
6041/* */
6042/******************************************************************************/
6043
6044/******************* Bit definition for DMA_ISR register ********************/
6045#define DMA_ISR_GIF1_Pos (0U)
6046#define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos)
6047#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk
6048#define DMA_ISR_TCIF1_Pos (1U)
6049#define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos)
6050#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk
6051#define DMA_ISR_HTIF1_Pos (2U)
6052#define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos)
6053#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk
6054#define DMA_ISR_TEIF1_Pos (3U)
6055#define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos)
6056#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk
6057#define DMA_ISR_GIF2_Pos (4U)
6058#define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos)
6059#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk
6060#define DMA_ISR_TCIF2_Pos (5U)
6061#define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos)
6062#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk
6063#define DMA_ISR_HTIF2_Pos (6U)
6064#define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos)
6065#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk
6066#define DMA_ISR_TEIF2_Pos (7U)
6067#define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos)
6068#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk
6069#define DMA_ISR_GIF3_Pos (8U)
6070#define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos)
6071#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk
6072#define DMA_ISR_TCIF3_Pos (9U)
6073#define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos)
6074#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk
6075#define DMA_ISR_HTIF3_Pos (10U)
6076#define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos)
6077#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk
6078#define DMA_ISR_TEIF3_Pos (11U)
6079#define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos)
6080#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk
6081#define DMA_ISR_GIF4_Pos (12U)
6082#define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos)
6083#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk
6084#define DMA_ISR_TCIF4_Pos (13U)
6085#define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos)
6086#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk
6087#define DMA_ISR_HTIF4_Pos (14U)
6088#define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos)
6089#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk
6090#define DMA_ISR_TEIF4_Pos (15U)
6091#define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos)
6092#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk
6093#define DMA_ISR_GIF5_Pos (16U)
6094#define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos)
6095#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk
6096#define DMA_ISR_TCIF5_Pos (17U)
6097#define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos)
6098#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk
6099#define DMA_ISR_HTIF5_Pos (18U)
6100#define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos)
6101#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk
6102#define DMA_ISR_TEIF5_Pos (19U)
6103#define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos)
6104#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk
6105#define DMA_ISR_GIF6_Pos (20U)
6106#define DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos)
6107#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk
6108#define DMA_ISR_TCIF6_Pos (21U)
6109#define DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos)
6110#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk
6111#define DMA_ISR_HTIF6_Pos (22U)
6112#define DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos)
6113#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk
6114#define DMA_ISR_TEIF6_Pos (23U)
6115#define DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos)
6116#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk
6117#define DMA_ISR_GIF7_Pos (24U)
6118#define DMA_ISR_GIF7_Msk (0x1UL << DMA_ISR_GIF7_Pos)
6119#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk
6120#define DMA_ISR_TCIF7_Pos (25U)
6121#define DMA_ISR_TCIF7_Msk (0x1UL << DMA_ISR_TCIF7_Pos)
6122#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk
6123#define DMA_ISR_HTIF7_Pos (26U)
6124#define DMA_ISR_HTIF7_Msk (0x1UL << DMA_ISR_HTIF7_Pos)
6125#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk
6126#define DMA_ISR_TEIF7_Pos (27U)
6127#define DMA_ISR_TEIF7_Msk (0x1UL << DMA_ISR_TEIF7_Pos)
6128#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk
6130/******************* Bit definition for DMA_IFCR register *******************/
6131#define DMA_IFCR_CGIF1_Pos (0U)
6132#define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos)
6133#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk
6134#define DMA_IFCR_CTCIF1_Pos (1U)
6135#define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos)
6136#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk
6137#define DMA_IFCR_CHTIF1_Pos (2U)
6138#define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos)
6139#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk
6140#define DMA_IFCR_CTEIF1_Pos (3U)
6141#define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos)
6142#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk
6143#define DMA_IFCR_CGIF2_Pos (4U)
6144#define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos)
6145#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk
6146#define DMA_IFCR_CTCIF2_Pos (5U)
6147#define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos)
6148#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk
6149#define DMA_IFCR_CHTIF2_Pos (6U)
6150#define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos)
6151#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk
6152#define DMA_IFCR_CTEIF2_Pos (7U)
6153#define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos)
6154#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk
6155#define DMA_IFCR_CGIF3_Pos (8U)
6156#define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos)
6157#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk
6158#define DMA_IFCR_CTCIF3_Pos (9U)
6159#define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos)
6160#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk
6161#define DMA_IFCR_CHTIF3_Pos (10U)
6162#define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos)
6163#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk
6164#define DMA_IFCR_CTEIF3_Pos (11U)
6165#define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos)
6166#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk
6167#define DMA_IFCR_CGIF4_Pos (12U)
6168#define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos)
6169#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk
6170#define DMA_IFCR_CTCIF4_Pos (13U)
6171#define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos)
6172#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk
6173#define DMA_IFCR_CHTIF4_Pos (14U)
6174#define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos)
6175#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk
6176#define DMA_IFCR_CTEIF4_Pos (15U)
6177#define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos)
6178#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk
6179#define DMA_IFCR_CGIF5_Pos (16U)
6180#define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos)
6181#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk
6182#define DMA_IFCR_CTCIF5_Pos (17U)
6183#define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos)
6184#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk
6185#define DMA_IFCR_CHTIF5_Pos (18U)
6186#define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos)
6187#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk
6188#define DMA_IFCR_CTEIF5_Pos (19U)
6189#define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos)
6190#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk
6191#define DMA_IFCR_CGIF6_Pos (20U)
6192#define DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos)
6193#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk
6194#define DMA_IFCR_CTCIF6_Pos (21U)
6195#define DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos)
6196#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk
6197#define DMA_IFCR_CHTIF6_Pos (22U)
6198#define DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos)
6199#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk
6200#define DMA_IFCR_CTEIF6_Pos (23U)
6201#define DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos)
6202#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk
6203#define DMA_IFCR_CGIF7_Pos (24U)
6204#define DMA_IFCR_CGIF7_Msk (0x1UL << DMA_IFCR_CGIF7_Pos)
6205#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk
6206#define DMA_IFCR_CTCIF7_Pos (25U)
6207#define DMA_IFCR_CTCIF7_Msk (0x1UL << DMA_IFCR_CTCIF7_Pos)
6208#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk
6209#define DMA_IFCR_CHTIF7_Pos (26U)
6210#define DMA_IFCR_CHTIF7_Msk (0x1UL << DMA_IFCR_CHTIF7_Pos)
6211#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk
6212#define DMA_IFCR_CTEIF7_Pos (27U)
6213#define DMA_IFCR_CTEIF7_Msk (0x1UL << DMA_IFCR_CTEIF7_Pos)
6214#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk
6216/******************* Bit definition for DMA_CCR register ********************/
6217#define DMA_CCR_EN_Pos (0U)
6218#define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos)
6219#define DMA_CCR_EN DMA_CCR_EN_Msk
6220#define DMA_CCR_TCIE_Pos (1U)
6221#define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos)
6222#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk
6223#define DMA_CCR_HTIE_Pos (2U)
6224#define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos)
6225#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk
6226#define DMA_CCR_TEIE_Pos (3U)
6227#define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos)
6228#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk
6229#define DMA_CCR_DIR_Pos (4U)
6230#define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos)
6231#define DMA_CCR_DIR DMA_CCR_DIR_Msk
6232#define DMA_CCR_CIRC_Pos (5U)
6233#define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos)
6234#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk
6235#define DMA_CCR_PINC_Pos (6U)
6236#define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos)
6237#define DMA_CCR_PINC DMA_CCR_PINC_Msk
6238#define DMA_CCR_MINC_Pos (7U)
6239#define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos)
6240#define DMA_CCR_MINC DMA_CCR_MINC_Msk
6242#define DMA_CCR_PSIZE_Pos (8U)
6243#define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos)
6244#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk
6245#define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos)
6246#define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos)
6248#define DMA_CCR_MSIZE_Pos (10U)
6249#define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos)
6250#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk
6251#define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos)
6252#define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos)
6254#define DMA_CCR_PL_Pos (12U)
6255#define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos)
6256#define DMA_CCR_PL DMA_CCR_PL_Msk
6257#define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos)
6258#define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos)
6260#define DMA_CCR_MEM2MEM_Pos (14U)
6261#define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos)
6262#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk
6264/****************** Bit definition for DMA_CNDTR register *******************/
6265#define DMA_CNDTR_NDT_Pos (0U)
6266#define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos)
6267#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk
6269/****************** Bit definition for DMA_CPAR register ********************/
6270#define DMA_CPAR_PA_Pos (0U)
6271#define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos)
6272#define DMA_CPAR_PA DMA_CPAR_PA_Msk
6274/****************** Bit definition for DMA_CMAR register ********************/
6275#define DMA_CMAR_MA_Pos (0U)
6276#define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos)
6277#define DMA_CMAR_MA DMA_CMAR_MA_Msk
6280/******************* Bit definition for DMA_CSELR register *******************/
6281#define DMA_CSELR_C1S_Pos (0U)
6282#define DMA_CSELR_C1S_Msk (0xFUL << DMA_CSELR_C1S_Pos)
6283#define DMA_CSELR_C1S DMA_CSELR_C1S_Msk
6284#define DMA_CSELR_C2S_Pos (4U)
6285#define DMA_CSELR_C2S_Msk (0xFUL << DMA_CSELR_C2S_Pos)
6286#define DMA_CSELR_C2S DMA_CSELR_C2S_Msk
6287#define DMA_CSELR_C3S_Pos (8U)
6288#define DMA_CSELR_C3S_Msk (0xFUL << DMA_CSELR_C3S_Pos)
6289#define DMA_CSELR_C3S DMA_CSELR_C3S_Msk
6290#define DMA_CSELR_C4S_Pos (12U)
6291#define DMA_CSELR_C4S_Msk (0xFUL << DMA_CSELR_C4S_Pos)
6292#define DMA_CSELR_C4S DMA_CSELR_C4S_Msk
6293#define DMA_CSELR_C5S_Pos (16U)
6294#define DMA_CSELR_C5S_Msk (0xFUL << DMA_CSELR_C5S_Pos)
6295#define DMA_CSELR_C5S DMA_CSELR_C5S_Msk
6296#define DMA_CSELR_C6S_Pos (20U)
6297#define DMA_CSELR_C6S_Msk (0xFUL << DMA_CSELR_C6S_Pos)
6298#define DMA_CSELR_C6S DMA_CSELR_C6S_Msk
6299#define DMA_CSELR_C7S_Pos (24U)
6300#define DMA_CSELR_C7S_Msk (0xFUL << DMA_CSELR_C7S_Pos)
6301#define DMA_CSELR_C7S DMA_CSELR_C7S_Msk
6303/******************************************************************************/
6304/* */
6305/* External Interrupt/Event Controller */
6306/* */
6307/******************************************************************************/
6308/******************* Bit definition for EXTI_IMR1 register ******************/
6309#define EXTI_IMR1_IM0_Pos (0U)
6310#define EXTI_IMR1_IM0_Msk (0x1UL << EXTI_IMR1_IM0_Pos)
6311#define EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk
6312#define EXTI_IMR1_IM1_Pos (1U)
6313#define EXTI_IMR1_IM1_Msk (0x1UL << EXTI_IMR1_IM1_Pos)
6314#define EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk
6315#define EXTI_IMR1_IM2_Pos (2U)
6316#define EXTI_IMR1_IM2_Msk (0x1UL << EXTI_IMR1_IM2_Pos)
6317#define EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk
6318#define EXTI_IMR1_IM3_Pos (3U)
6319#define EXTI_IMR1_IM3_Msk (0x1UL << EXTI_IMR1_IM3_Pos)
6320#define EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk
6321#define EXTI_IMR1_IM4_Pos (4U)
6322#define EXTI_IMR1_IM4_Msk (0x1UL << EXTI_IMR1_IM4_Pos)
6323#define EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk
6324#define EXTI_IMR1_IM5_Pos (5U)
6325#define EXTI_IMR1_IM5_Msk (0x1UL << EXTI_IMR1_IM5_Pos)
6326#define EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk
6327#define EXTI_IMR1_IM6_Pos (6U)
6328#define EXTI_IMR1_IM6_Msk (0x1UL << EXTI_IMR1_IM6_Pos)
6329#define EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk
6330#define EXTI_IMR1_IM7_Pos (7U)
6331#define EXTI_IMR1_IM7_Msk (0x1UL << EXTI_IMR1_IM7_Pos)
6332#define EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk
6333#define EXTI_IMR1_IM8_Pos (8U)
6334#define EXTI_IMR1_IM8_Msk (0x1UL << EXTI_IMR1_IM8_Pos)
6335#define EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk
6336#define EXTI_IMR1_IM9_Pos (9U)
6337#define EXTI_IMR1_IM9_Msk (0x1UL << EXTI_IMR1_IM9_Pos)
6338#define EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk
6339#define EXTI_IMR1_IM10_Pos (10U)
6340#define EXTI_IMR1_IM10_Msk (0x1UL << EXTI_IMR1_IM10_Pos)
6341#define EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk
6342#define EXTI_IMR1_IM11_Pos (11U)
6343#define EXTI_IMR1_IM11_Msk (0x1UL << EXTI_IMR1_IM11_Pos)
6344#define EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk
6345#define EXTI_IMR1_IM12_Pos (12U)
6346#define EXTI_IMR1_IM12_Msk (0x1UL << EXTI_IMR1_IM12_Pos)
6347#define EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk
6348#define EXTI_IMR1_IM13_Pos (13U)
6349#define EXTI_IMR1_IM13_Msk (0x1UL << EXTI_IMR1_IM13_Pos)
6350#define EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk
6351#define EXTI_IMR1_IM14_Pos (14U)
6352#define EXTI_IMR1_IM14_Msk (0x1UL << EXTI_IMR1_IM14_Pos)
6353#define EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk
6354#define EXTI_IMR1_IM15_Pos (15U)
6355#define EXTI_IMR1_IM15_Msk (0x1UL << EXTI_IMR1_IM15_Pos)
6356#define EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk
6357#define EXTI_IMR1_IM16_Pos (16U)
6358#define EXTI_IMR1_IM16_Msk (0x1UL << EXTI_IMR1_IM16_Pos)
6359#define EXTI_IMR1_IM16 EXTI_IMR1_IM16_Msk
6360#define EXTI_IMR1_IM17_Pos (17U)
6361#define EXTI_IMR1_IM17_Msk (0x1UL << EXTI_IMR1_IM17_Pos)
6362#define EXTI_IMR1_IM17 EXTI_IMR1_IM17_Msk
6363#define EXTI_IMR1_IM18_Pos (18U)
6364#define EXTI_IMR1_IM18_Msk (0x1UL << EXTI_IMR1_IM18_Pos)
6365#define EXTI_IMR1_IM18 EXTI_IMR1_IM18_Msk
6366#define EXTI_IMR1_IM19_Pos (19U)
6367#define EXTI_IMR1_IM19_Msk (0x1UL << EXTI_IMR1_IM19_Pos)
6368#define EXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk
6369#define EXTI_IMR1_IM20_Pos (20U)
6370#define EXTI_IMR1_IM20_Msk (0x1UL << EXTI_IMR1_IM20_Pos)
6371#define EXTI_IMR1_IM20 EXTI_IMR1_IM20_Msk
6372#define EXTI_IMR1_IM21_Pos (21U)
6373#define EXTI_IMR1_IM21_Msk (0x1UL << EXTI_IMR1_IM21_Pos)
6374#define EXTI_IMR1_IM21 EXTI_IMR1_IM21_Msk
6375#define EXTI_IMR1_IM22_Pos (22U)
6376#define EXTI_IMR1_IM22_Msk (0x1UL << EXTI_IMR1_IM22_Pos)
6377#define EXTI_IMR1_IM22 EXTI_IMR1_IM22_Msk
6378#define EXTI_IMR1_IM23_Pos (23U)
6379#define EXTI_IMR1_IM23_Msk (0x1UL << EXTI_IMR1_IM23_Pos)
6380#define EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk
6381#define EXTI_IMR1_IM24_Pos (24U)
6382#define EXTI_IMR1_IM24_Msk (0x1UL << EXTI_IMR1_IM24_Pos)
6383#define EXTI_IMR1_IM24 EXTI_IMR1_IM24_Msk
6384#define EXTI_IMR1_IM25_Pos (25U)
6385#define EXTI_IMR1_IM25_Msk (0x1UL << EXTI_IMR1_IM25_Pos)
6386#define EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk
6387#define EXTI_IMR1_IM26_Pos (26U)
6388#define EXTI_IMR1_IM26_Msk (0x1UL << EXTI_IMR1_IM26_Pos)
6389#define EXTI_IMR1_IM26 EXTI_IMR1_IM26_Msk
6390#define EXTI_IMR1_IM27_Pos (27U)
6391#define EXTI_IMR1_IM27_Msk (0x1UL << EXTI_IMR1_IM27_Pos)
6392#define EXTI_IMR1_IM27 EXTI_IMR1_IM27_Msk
6393#define EXTI_IMR1_IM28_Pos (28U)
6394#define EXTI_IMR1_IM28_Msk (0x1UL << EXTI_IMR1_IM28_Pos)
6395#define EXTI_IMR1_IM28 EXTI_IMR1_IM28_Msk
6396#define EXTI_IMR1_IM31_Pos (31U)
6397#define EXTI_IMR1_IM31_Msk (0x1UL << EXTI_IMR1_IM31_Pos)
6398#define EXTI_IMR1_IM31 EXTI_IMR1_IM31_Msk
6399#define EXTI_IMR1_IM_Pos (0U)
6400#define EXTI_IMR1_IM_Msk (0x9FFFFFFFUL << EXTI_IMR1_IM_Pos)
6401#define EXTI_IMR1_IM EXTI_IMR1_IM_Msk
6403/******************* Bit definition for EXTI_EMR1 register ******************/
6404#define EXTI_EMR1_EM0_Pos (0U)
6405#define EXTI_EMR1_EM0_Msk (0x1UL << EXTI_EMR1_EM0_Pos)
6406#define EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk
6407#define EXTI_EMR1_EM1_Pos (1U)
6408#define EXTI_EMR1_EM1_Msk (0x1UL << EXTI_EMR1_EM1_Pos)
6409#define EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk
6410#define EXTI_EMR1_EM2_Pos (2U)
6411#define EXTI_EMR1_EM2_Msk (0x1UL << EXTI_EMR1_EM2_Pos)
6412#define EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk
6413#define EXTI_EMR1_EM3_Pos (3U)
6414#define EXTI_EMR1_EM3_Msk (0x1UL << EXTI_EMR1_EM3_Pos)
6415#define EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk
6416#define EXTI_EMR1_EM4_Pos (4U)
6417#define EXTI_EMR1_EM4_Msk (0x1UL << EXTI_EMR1_EM4_Pos)
6418#define EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk
6419#define EXTI_EMR1_EM5_Pos (5U)
6420#define EXTI_EMR1_EM5_Msk (0x1UL << EXTI_EMR1_EM5_Pos)
6421#define EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk
6422#define EXTI_EMR1_EM6_Pos (6U)
6423#define EXTI_EMR1_EM6_Msk (0x1UL << EXTI_EMR1_EM6_Pos)
6424#define EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk
6425#define EXTI_EMR1_EM7_Pos (7U)
6426#define EXTI_EMR1_EM7_Msk (0x1UL << EXTI_EMR1_EM7_Pos)
6427#define EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk
6428#define EXTI_EMR1_EM8_Pos (8U)
6429#define EXTI_EMR1_EM8_Msk (0x1UL << EXTI_EMR1_EM8_Pos)
6430#define EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk
6431#define EXTI_EMR1_EM9_Pos (9U)
6432#define EXTI_EMR1_EM9_Msk (0x1UL << EXTI_EMR1_EM9_Pos)
6433#define EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk
6434#define EXTI_EMR1_EM10_Pos (10U)
6435#define EXTI_EMR1_EM10_Msk (0x1UL << EXTI_EMR1_EM10_Pos)
6436#define EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk
6437#define EXTI_EMR1_EM11_Pos (11U)
6438#define EXTI_EMR1_EM11_Msk (0x1UL << EXTI_EMR1_EM11_Pos)
6439#define EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk
6440#define EXTI_EMR1_EM12_Pos (12U)
6441#define EXTI_EMR1_EM12_Msk (0x1UL << EXTI_EMR1_EM12_Pos)
6442#define EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk
6443#define EXTI_EMR1_EM13_Pos (13U)
6444#define EXTI_EMR1_EM13_Msk (0x1UL << EXTI_EMR1_EM13_Pos)
6445#define EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk
6446#define EXTI_EMR1_EM14_Pos (14U)
6447#define EXTI_EMR1_EM14_Msk (0x1UL << EXTI_EMR1_EM14_Pos)
6448#define EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk
6449#define EXTI_EMR1_EM15_Pos (15U)
6450#define EXTI_EMR1_EM15_Msk (0x1UL << EXTI_EMR1_EM15_Pos)
6451#define EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk
6452#define EXTI_EMR1_EM16_Pos (16U)
6453#define EXTI_EMR1_EM16_Msk (0x1UL << EXTI_EMR1_EM16_Pos)
6454#define EXTI_EMR1_EM16 EXTI_EMR1_EM16_Msk
6455#define EXTI_EMR1_EM17_Pos (17U)
6456#define EXTI_EMR1_EM17_Msk (0x1UL << EXTI_EMR1_EM17_Pos)
6457#define EXTI_EMR1_EM17 EXTI_EMR1_EM17_Msk
6458#define EXTI_EMR1_EM18_Pos (18U)
6459#define EXTI_EMR1_EM18_Msk (0x1UL << EXTI_EMR1_EM18_Pos)
6460#define EXTI_EMR1_EM18 EXTI_EMR1_EM18_Msk
6461#define EXTI_EMR1_EM19_Pos (19U)
6462#define EXTI_EMR1_EM19_Msk (0x1UL << EXTI_EMR1_EM19_Pos)
6463#define EXTI_EMR1_EM19 EXTI_EMR1_EM19_Msk
6464#define EXTI_EMR1_EM20_Pos (20U)
6465#define EXTI_EMR1_EM20_Msk (0x1UL << EXTI_EMR1_EM20_Pos)
6466#define EXTI_EMR1_EM20 EXTI_EMR1_EM20_Msk
6467#define EXTI_EMR1_EM21_Pos (21U)
6468#define EXTI_EMR1_EM21_Msk (0x1UL << EXTI_EMR1_EM21_Pos)
6469#define EXTI_EMR1_EM21 EXTI_EMR1_EM21_Msk
6470#define EXTI_EMR1_EM22_Pos (22U)
6471#define EXTI_EMR1_EM22_Msk (0x1UL << EXTI_EMR1_EM22_Pos)
6472#define EXTI_EMR1_EM22 EXTI_EMR1_EM22_Msk
6473#define EXTI_EMR1_EM23_Pos (23U)
6474#define EXTI_EMR1_EM23_Msk (0x1UL << EXTI_EMR1_EM23_Pos)
6475#define EXTI_EMR1_EM23 EXTI_EMR1_EM23_Msk
6476#define EXTI_EMR1_EM24_Pos (24U)
6477#define EXTI_EMR1_EM24_Msk (0x1UL << EXTI_EMR1_EM24_Pos)
6478#define EXTI_EMR1_EM24 EXTI_EMR1_EM24_Msk
6479#define EXTI_EMR1_EM25_Pos (25U)
6480#define EXTI_EMR1_EM25_Msk (0x1UL << EXTI_EMR1_EM25_Pos)
6481#define EXTI_EMR1_EM25 EXTI_EMR1_EM25_Msk
6482#define EXTI_EMR1_EM26_Pos (26U)
6483#define EXTI_EMR1_EM26_Msk (0x1UL << EXTI_EMR1_EM26_Pos)
6484#define EXTI_EMR1_EM26 EXTI_EMR1_EM26_Msk
6485#define EXTI_EMR1_EM27_Pos (27U)
6486#define EXTI_EMR1_EM27_Msk (0x1UL << EXTI_EMR1_EM27_Pos)
6487#define EXTI_EMR1_EM27 EXTI_EMR1_EM27_Msk
6488#define EXTI_EMR1_EM28_Pos (28U)
6489#define EXTI_EMR1_EM28_Msk (0x1UL << EXTI_EMR1_EM28_Pos)
6490#define EXTI_EMR1_EM28 EXTI_EMR1_EM28_Msk
6491#define EXTI_EMR1_EM31_Pos (31U)
6492#define EXTI_EMR1_EM31_Msk (0x1UL << EXTI_EMR1_EM31_Pos)
6493#define EXTI_EMR1_EM31 EXTI_EMR1_EM31_Msk
6495/****************** Bit definition for EXTI_RTSR1 register ******************/
6496#define EXTI_RTSR1_RT0_Pos (0U)
6497#define EXTI_RTSR1_RT0_Msk (0x1UL << EXTI_RTSR1_RT0_Pos)
6498#define EXTI_RTSR1_RT0 EXTI_RTSR1_RT0_Msk
6499#define EXTI_RTSR1_RT1_Pos (1U)
6500#define EXTI_RTSR1_RT1_Msk (0x1UL << EXTI_RTSR1_RT1_Pos)
6501#define EXTI_RTSR1_RT1 EXTI_RTSR1_RT1_Msk
6502#define EXTI_RTSR1_RT2_Pos (2U)
6503#define EXTI_RTSR1_RT2_Msk (0x1UL << EXTI_RTSR1_RT2_Pos)
6504#define EXTI_RTSR1_RT2 EXTI_RTSR1_RT2_Msk
6505#define EXTI_RTSR1_RT3_Pos (3U)
6506#define EXTI_RTSR1_RT3_Msk (0x1UL << EXTI_RTSR1_RT3_Pos)
6507#define EXTI_RTSR1_RT3 EXTI_RTSR1_RT3_Msk
6508#define EXTI_RTSR1_RT4_Pos (4U)
6509#define EXTI_RTSR1_RT4_Msk (0x1UL << EXTI_RTSR1_RT4_Pos)
6510#define EXTI_RTSR1_RT4 EXTI_RTSR1_RT4_Msk
6511#define EXTI_RTSR1_RT5_Pos (5U)
6512#define EXTI_RTSR1_RT5_Msk (0x1UL << EXTI_RTSR1_RT5_Pos)
6513#define EXTI_RTSR1_RT5 EXTI_RTSR1_RT5_Msk
6514#define EXTI_RTSR1_RT6_Pos (6U)
6515#define EXTI_RTSR1_RT6_Msk (0x1UL << EXTI_RTSR1_RT6_Pos)
6516#define EXTI_RTSR1_RT6 EXTI_RTSR1_RT6_Msk
6517#define EXTI_RTSR1_RT7_Pos (7U)
6518#define EXTI_RTSR1_RT7_Msk (0x1UL << EXTI_RTSR1_RT7_Pos)
6519#define EXTI_RTSR1_RT7 EXTI_RTSR1_RT7_Msk
6520#define EXTI_RTSR1_RT8_Pos (8U)
6521#define EXTI_RTSR1_RT8_Msk (0x1UL << EXTI_RTSR1_RT8_Pos)
6522#define EXTI_RTSR1_RT8 EXTI_RTSR1_RT8_Msk
6523#define EXTI_RTSR1_RT9_Pos (9U)
6524#define EXTI_RTSR1_RT9_Msk (0x1UL << EXTI_RTSR1_RT9_Pos)
6525#define EXTI_RTSR1_RT9 EXTI_RTSR1_RT9_Msk
6526#define EXTI_RTSR1_RT10_Pos (10U)
6527#define EXTI_RTSR1_RT10_Msk (0x1UL << EXTI_RTSR1_RT10_Pos)
6528#define EXTI_RTSR1_RT10 EXTI_RTSR1_RT10_Msk
6529#define EXTI_RTSR1_RT11_Pos (11U)
6530#define EXTI_RTSR1_RT11_Msk (0x1UL << EXTI_RTSR1_RT11_Pos)
6531#define EXTI_RTSR1_RT11 EXTI_RTSR1_RT11_Msk
6532#define EXTI_RTSR1_RT12_Pos (12U)
6533#define EXTI_RTSR1_RT12_Msk (0x1UL << EXTI_RTSR1_RT12_Pos)
6534#define EXTI_RTSR1_RT12 EXTI_RTSR1_RT12_Msk
6535#define EXTI_RTSR1_RT13_Pos (13U)
6536#define EXTI_RTSR1_RT13_Msk (0x1UL << EXTI_RTSR1_RT13_Pos)
6537#define EXTI_RTSR1_RT13 EXTI_RTSR1_RT13_Msk
6538#define EXTI_RTSR1_RT14_Pos (14U)
6539#define EXTI_RTSR1_RT14_Msk (0x1UL << EXTI_RTSR1_RT14_Pos)
6540#define EXTI_RTSR1_RT14 EXTI_RTSR1_RT14_Msk
6541#define EXTI_RTSR1_RT15_Pos (15U)
6542#define EXTI_RTSR1_RT15_Msk (0x1UL << EXTI_RTSR1_RT15_Pos)
6543#define EXTI_RTSR1_RT15 EXTI_RTSR1_RT15_Msk
6544#define EXTI_RTSR1_RT16_Pos (16U)
6545#define EXTI_RTSR1_RT16_Msk (0x1UL << EXTI_RTSR1_RT16_Pos)
6546#define EXTI_RTSR1_RT16 EXTI_RTSR1_RT16_Msk
6547#define EXTI_RTSR1_RT18_Pos (18U)
6548#define EXTI_RTSR1_RT18_Msk (0x1UL << EXTI_RTSR1_RT18_Pos)
6549#define EXTI_RTSR1_RT18 EXTI_RTSR1_RT18_Msk
6550#define EXTI_RTSR1_RT19_Pos (19U)
6551#define EXTI_RTSR1_RT19_Msk (0x1UL << EXTI_RTSR1_RT19_Pos)
6552#define EXTI_RTSR1_RT19 EXTI_RTSR1_RT19_Msk
6553#define EXTI_RTSR1_RT20_Pos (20U)
6554#define EXTI_RTSR1_RT20_Msk (0x1UL << EXTI_RTSR1_RT20_Pos)
6555#define EXTI_RTSR1_RT20 EXTI_RTSR1_RT20_Msk
6556#define EXTI_RTSR1_RT21_Pos (21U)
6557#define EXTI_RTSR1_RT21_Msk (0x1UL << EXTI_RTSR1_RT21_Pos)
6558#define EXTI_RTSR1_RT21 EXTI_RTSR1_RT21_Msk
6559#define EXTI_RTSR1_RT22_Pos (22U)
6560#define EXTI_RTSR1_RT22_Msk (0x1UL << EXTI_RTSR1_RT22_Pos)
6561#define EXTI_RTSR1_RT22 EXTI_RTSR1_RT22_Msk
6563/****************** Bit definition for EXTI_FTSR1 register ******************/
6564#define EXTI_FTSR1_FT0_Pos (0U)
6565#define EXTI_FTSR1_FT0_Msk (0x1UL << EXTI_FTSR1_FT0_Pos)
6566#define EXTI_FTSR1_FT0 EXTI_FTSR1_FT0_Msk
6567#define EXTI_FTSR1_FT1_Pos (1U)
6568#define EXTI_FTSR1_FT1_Msk (0x1UL << EXTI_FTSR1_FT1_Pos)
6569#define EXTI_FTSR1_FT1 EXTI_FTSR1_FT1_Msk
6570#define EXTI_FTSR1_FT2_Pos (2U)
6571#define EXTI_FTSR1_FT2_Msk (0x1UL << EXTI_FTSR1_FT2_Pos)
6572#define EXTI_FTSR1_FT2 EXTI_FTSR1_FT2_Msk
6573#define EXTI_FTSR1_FT3_Pos (3U)
6574#define EXTI_FTSR1_FT3_Msk (0x1UL << EXTI_FTSR1_FT3_Pos)
6575#define EXTI_FTSR1_FT3 EXTI_FTSR1_FT3_Msk
6576#define EXTI_FTSR1_FT4_Pos (4U)
6577#define EXTI_FTSR1_FT4_Msk (0x1UL << EXTI_FTSR1_FT4_Pos)
6578#define EXTI_FTSR1_FT4 EXTI_FTSR1_FT4_Msk
6579#define EXTI_FTSR1_FT5_Pos (5U)
6580#define EXTI_FTSR1_FT5_Msk (0x1UL << EXTI_FTSR1_FT5_Pos)
6581#define EXTI_FTSR1_FT5 EXTI_FTSR1_FT5_Msk
6582#define EXTI_FTSR1_FT6_Pos (6U)
6583#define EXTI_FTSR1_FT6_Msk (0x1UL << EXTI_FTSR1_FT6_Pos)
6584#define EXTI_FTSR1_FT6 EXTI_FTSR1_FT6_Msk
6585#define EXTI_FTSR1_FT7_Pos (7U)
6586#define EXTI_FTSR1_FT7_Msk (0x1UL << EXTI_FTSR1_FT7_Pos)
6587#define EXTI_FTSR1_FT7 EXTI_FTSR1_FT7_Msk
6588#define EXTI_FTSR1_FT8_Pos (8U)
6589#define EXTI_FTSR1_FT8_Msk (0x1UL << EXTI_FTSR1_FT8_Pos)
6590#define EXTI_FTSR1_FT8 EXTI_FTSR1_FT8_Msk
6591#define EXTI_FTSR1_FT9_Pos (9U)
6592#define EXTI_FTSR1_FT9_Msk (0x1UL << EXTI_FTSR1_FT9_Pos)
6593#define EXTI_FTSR1_FT9 EXTI_FTSR1_FT9_Msk
6594#define EXTI_FTSR1_FT10_Pos (10U)
6595#define EXTI_FTSR1_FT10_Msk (0x1UL << EXTI_FTSR1_FT10_Pos)
6596#define EXTI_FTSR1_FT10 EXTI_FTSR1_FT10_Msk
6597#define EXTI_FTSR1_FT11_Pos (11U)
6598#define EXTI_FTSR1_FT11_Msk (0x1UL << EXTI_FTSR1_FT11_Pos)
6599#define EXTI_FTSR1_FT11 EXTI_FTSR1_FT11_Msk
6600#define EXTI_FTSR1_FT12_Pos (12U)
6601#define EXTI_FTSR1_FT12_Msk (0x1UL << EXTI_FTSR1_FT12_Pos)
6602#define EXTI_FTSR1_FT12 EXTI_FTSR1_FT12_Msk
6603#define EXTI_FTSR1_FT13_Pos (13U)
6604#define EXTI_FTSR1_FT13_Msk (0x1UL << EXTI_FTSR1_FT13_Pos)
6605#define EXTI_FTSR1_FT13 EXTI_FTSR1_FT13_Msk
6606#define EXTI_FTSR1_FT14_Pos (14U)
6607#define EXTI_FTSR1_FT14_Msk (0x1UL << EXTI_FTSR1_FT14_Pos)
6608#define EXTI_FTSR1_FT14 EXTI_FTSR1_FT14_Msk
6609#define EXTI_FTSR1_FT15_Pos (15U)
6610#define EXTI_FTSR1_FT15_Msk (0x1UL << EXTI_FTSR1_FT15_Pos)
6611#define EXTI_FTSR1_FT15 EXTI_FTSR1_FT15_Msk
6612#define EXTI_FTSR1_FT16_Pos (16U)
6613#define EXTI_FTSR1_FT16_Msk (0x1UL << EXTI_FTSR1_FT16_Pos)
6614#define EXTI_FTSR1_FT16 EXTI_FTSR1_FT16_Msk
6615#define EXTI_FTSR1_FT18_Pos (18U)
6616#define EXTI_FTSR1_FT18_Msk (0x1UL << EXTI_FTSR1_FT18_Pos)
6617#define EXTI_FTSR1_FT18 EXTI_FTSR1_FT18_Msk
6618#define EXTI_FTSR1_FT19_Pos (19U)
6619#define EXTI_FTSR1_FT19_Msk (0x1UL << EXTI_FTSR1_FT19_Pos)
6620#define EXTI_FTSR1_FT19 EXTI_FTSR1_FT19_Msk
6621#define EXTI_FTSR1_FT20_Pos (20U)
6622#define EXTI_FTSR1_FT20_Msk (0x1UL << EXTI_FTSR1_FT20_Pos)
6623#define EXTI_FTSR1_FT20 EXTI_FTSR1_FT20_Msk
6624#define EXTI_FTSR1_FT21_Pos (21U)
6625#define EXTI_FTSR1_FT21_Msk (0x1UL << EXTI_FTSR1_FT21_Pos)
6626#define EXTI_FTSR1_FT21 EXTI_FTSR1_FT21_Msk
6627#define EXTI_FTSR1_FT22_Pos (22U)
6628#define EXTI_FTSR1_FT22_Msk (0x1UL << EXTI_FTSR1_FT22_Pos)
6629#define EXTI_FTSR1_FT22 EXTI_FTSR1_FT22_Msk
6631/****************** Bit definition for EXTI_SWIER1 register *****************/
6632#define EXTI_SWIER1_SWI0_Pos (0U)
6633#define EXTI_SWIER1_SWI0_Msk (0x1UL << EXTI_SWIER1_SWI0_Pos)
6634#define EXTI_SWIER1_SWI0 EXTI_SWIER1_SWI0_Msk
6635#define EXTI_SWIER1_SWI1_Pos (1U)
6636#define EXTI_SWIER1_SWI1_Msk (0x1UL << EXTI_SWIER1_SWI1_Pos)
6637#define EXTI_SWIER1_SWI1 EXTI_SWIER1_SWI1_Msk
6638#define EXTI_SWIER1_SWI2_Pos (2U)
6639#define EXTI_SWIER1_SWI2_Msk (0x1UL << EXTI_SWIER1_SWI2_Pos)
6640#define EXTI_SWIER1_SWI2 EXTI_SWIER1_SWI2_Msk
6641#define EXTI_SWIER1_SWI3_Pos (3U)
6642#define EXTI_SWIER1_SWI3_Msk (0x1UL << EXTI_SWIER1_SWI3_Pos)
6643#define EXTI_SWIER1_SWI3 EXTI_SWIER1_SWI3_Msk
6644#define EXTI_SWIER1_SWI4_Pos (4U)
6645#define EXTI_SWIER1_SWI4_Msk (0x1UL << EXTI_SWIER1_SWI4_Pos)
6646#define EXTI_SWIER1_SWI4 EXTI_SWIER1_SWI4_Msk
6647#define EXTI_SWIER1_SWI5_Pos (5U)
6648#define EXTI_SWIER1_SWI5_Msk (0x1UL << EXTI_SWIER1_SWI5_Pos)
6649#define EXTI_SWIER1_SWI5 EXTI_SWIER1_SWI5_Msk
6650#define EXTI_SWIER1_SWI6_Pos (6U)
6651#define EXTI_SWIER1_SWI6_Msk (0x1UL << EXTI_SWIER1_SWI6_Pos)
6652#define EXTI_SWIER1_SWI6 EXTI_SWIER1_SWI6_Msk
6653#define EXTI_SWIER1_SWI7_Pos (7U)
6654#define EXTI_SWIER1_SWI7_Msk (0x1UL << EXTI_SWIER1_SWI7_Pos)
6655#define EXTI_SWIER1_SWI7 EXTI_SWIER1_SWI7_Msk
6656#define EXTI_SWIER1_SWI8_Pos (8U)
6657#define EXTI_SWIER1_SWI8_Msk (0x1UL << EXTI_SWIER1_SWI8_Pos)
6658#define EXTI_SWIER1_SWI8 EXTI_SWIER1_SWI8_Msk
6659#define EXTI_SWIER1_SWI9_Pos (9U)
6660#define EXTI_SWIER1_SWI9_Msk (0x1UL << EXTI_SWIER1_SWI9_Pos)
6661#define EXTI_SWIER1_SWI9 EXTI_SWIER1_SWI9_Msk
6662#define EXTI_SWIER1_SWI10_Pos (10U)
6663#define EXTI_SWIER1_SWI10_Msk (0x1UL << EXTI_SWIER1_SWI10_Pos)
6664#define EXTI_SWIER1_SWI10 EXTI_SWIER1_SWI10_Msk
6665#define EXTI_SWIER1_SWI11_Pos (11U)
6666#define EXTI_SWIER1_SWI11_Msk (0x1UL << EXTI_SWIER1_SWI11_Pos)
6667#define EXTI_SWIER1_SWI11 EXTI_SWIER1_SWI11_Msk
6668#define EXTI_SWIER1_SWI12_Pos (12U)
6669#define EXTI_SWIER1_SWI12_Msk (0x1UL << EXTI_SWIER1_SWI12_Pos)
6670#define EXTI_SWIER1_SWI12 EXTI_SWIER1_SWI12_Msk
6671#define EXTI_SWIER1_SWI13_Pos (13U)
6672#define EXTI_SWIER1_SWI13_Msk (0x1UL << EXTI_SWIER1_SWI13_Pos)
6673#define EXTI_SWIER1_SWI13 EXTI_SWIER1_SWI13_Msk
6674#define EXTI_SWIER1_SWI14_Pos (14U)
6675#define EXTI_SWIER1_SWI14_Msk (0x1UL << EXTI_SWIER1_SWI14_Pos)
6676#define EXTI_SWIER1_SWI14 EXTI_SWIER1_SWI14_Msk
6677#define EXTI_SWIER1_SWI15_Pos (15U)
6678#define EXTI_SWIER1_SWI15_Msk (0x1UL << EXTI_SWIER1_SWI15_Pos)
6679#define EXTI_SWIER1_SWI15 EXTI_SWIER1_SWI15_Msk
6680#define EXTI_SWIER1_SWI16_Pos (16U)
6681#define EXTI_SWIER1_SWI16_Msk (0x1UL << EXTI_SWIER1_SWI16_Pos)
6682#define EXTI_SWIER1_SWI16 EXTI_SWIER1_SWI16_Msk
6683#define EXTI_SWIER1_SWI18_Pos (18U)
6684#define EXTI_SWIER1_SWI18_Msk (0x1UL << EXTI_SWIER1_SWI18_Pos)
6685#define EXTI_SWIER1_SWI18 EXTI_SWIER1_SWI18_Msk
6686#define EXTI_SWIER1_SWI19_Pos (19U)
6687#define EXTI_SWIER1_SWI19_Msk (0x1UL << EXTI_SWIER1_SWI19_Pos)
6688#define EXTI_SWIER1_SWI19 EXTI_SWIER1_SWI19_Msk
6689#define EXTI_SWIER1_SWI20_Pos (20U)
6690#define EXTI_SWIER1_SWI20_Msk (0x1UL << EXTI_SWIER1_SWI20_Pos)
6691#define EXTI_SWIER1_SWI20 EXTI_SWIER1_SWI20_Msk
6692#define EXTI_SWIER1_SWI21_Pos (21U)
6693#define EXTI_SWIER1_SWI21_Msk (0x1UL << EXTI_SWIER1_SWI21_Pos)
6694#define EXTI_SWIER1_SWI21 EXTI_SWIER1_SWI21_Msk
6695#define EXTI_SWIER1_SWI22_Pos (22U)
6696#define EXTI_SWIER1_SWI22_Msk (0x1UL << EXTI_SWIER1_SWI22_Pos)
6697#define EXTI_SWIER1_SWI22 EXTI_SWIER1_SWI22_Msk
6699/******************* Bit definition for EXTI_PR1 register *******************/
6700#define EXTI_PR1_PIF0_Pos (0U)
6701#define EXTI_PR1_PIF0_Msk (0x1UL << EXTI_PR1_PIF0_Pos)
6702#define EXTI_PR1_PIF0 EXTI_PR1_PIF0_Msk
6703#define EXTI_PR1_PIF1_Pos (1U)
6704#define EXTI_PR1_PIF1_Msk (0x1UL << EXTI_PR1_PIF1_Pos)
6705#define EXTI_PR1_PIF1 EXTI_PR1_PIF1_Msk
6706#define EXTI_PR1_PIF2_Pos (2U)
6707#define EXTI_PR1_PIF2_Msk (0x1UL << EXTI_PR1_PIF2_Pos)
6708#define EXTI_PR1_PIF2 EXTI_PR1_PIF2_Msk
6709#define EXTI_PR1_PIF3_Pos (3U)
6710#define EXTI_PR1_PIF3_Msk (0x1UL << EXTI_PR1_PIF3_Pos)
6711#define EXTI_PR1_PIF3 EXTI_PR1_PIF3_Msk
6712#define EXTI_PR1_PIF4_Pos (4U)
6713#define EXTI_PR1_PIF4_Msk (0x1UL << EXTI_PR1_PIF4_Pos)
6714#define EXTI_PR1_PIF4 EXTI_PR1_PIF4_Msk
6715#define EXTI_PR1_PIF5_Pos (5U)
6716#define EXTI_PR1_PIF5_Msk (0x1UL << EXTI_PR1_PIF5_Pos)
6717#define EXTI_PR1_PIF5 EXTI_PR1_PIF5_Msk
6718#define EXTI_PR1_PIF6_Pos (6U)
6719#define EXTI_PR1_PIF6_Msk (0x1UL << EXTI_PR1_PIF6_Pos)
6720#define EXTI_PR1_PIF6 EXTI_PR1_PIF6_Msk
6721#define EXTI_PR1_PIF7_Pos (7U)
6722#define EXTI_PR1_PIF7_Msk (0x1UL << EXTI_PR1_PIF7_Pos)
6723#define EXTI_PR1_PIF7 EXTI_PR1_PIF7_Msk
6724#define EXTI_PR1_PIF8_Pos (8U)
6725#define EXTI_PR1_PIF8_Msk (0x1UL << EXTI_PR1_PIF8_Pos)
6726#define EXTI_PR1_PIF8 EXTI_PR1_PIF8_Msk
6727#define EXTI_PR1_PIF9_Pos (9U)
6728#define EXTI_PR1_PIF9_Msk (0x1UL << EXTI_PR1_PIF9_Pos)
6729#define EXTI_PR1_PIF9 EXTI_PR1_PIF9_Msk
6730#define EXTI_PR1_PIF10_Pos (10U)
6731#define EXTI_PR1_PIF10_Msk (0x1UL << EXTI_PR1_PIF10_Pos)
6732#define EXTI_PR1_PIF10 EXTI_PR1_PIF10_Msk
6733#define EXTI_PR1_PIF11_Pos (11U)
6734#define EXTI_PR1_PIF11_Msk (0x1UL << EXTI_PR1_PIF11_Pos)
6735#define EXTI_PR1_PIF11 EXTI_PR1_PIF11_Msk
6736#define EXTI_PR1_PIF12_Pos (12U)
6737#define EXTI_PR1_PIF12_Msk (0x1UL << EXTI_PR1_PIF12_Pos)
6738#define EXTI_PR1_PIF12 EXTI_PR1_PIF12_Msk
6739#define EXTI_PR1_PIF13_Pos (13U)
6740#define EXTI_PR1_PIF13_Msk (0x1UL << EXTI_PR1_PIF13_Pos)
6741#define EXTI_PR1_PIF13 EXTI_PR1_PIF13_Msk
6742#define EXTI_PR1_PIF14_Pos (14U)
6743#define EXTI_PR1_PIF14_Msk (0x1UL << EXTI_PR1_PIF14_Pos)
6744#define EXTI_PR1_PIF14 EXTI_PR1_PIF14_Msk
6745#define EXTI_PR1_PIF15_Pos (15U)
6746#define EXTI_PR1_PIF15_Msk (0x1UL << EXTI_PR1_PIF15_Pos)
6747#define EXTI_PR1_PIF15 EXTI_PR1_PIF15_Msk
6748#define EXTI_PR1_PIF16_Pos (16U)
6749#define EXTI_PR1_PIF16_Msk (0x1UL << EXTI_PR1_PIF16_Pos)
6750#define EXTI_PR1_PIF16 EXTI_PR1_PIF16_Msk
6751#define EXTI_PR1_PIF18_Pos (18U)
6752#define EXTI_PR1_PIF18_Msk (0x1UL << EXTI_PR1_PIF18_Pos)
6753#define EXTI_PR1_PIF18 EXTI_PR1_PIF18_Msk
6754#define EXTI_PR1_PIF19_Pos (19U)
6755#define EXTI_PR1_PIF19_Msk (0x1UL << EXTI_PR1_PIF19_Pos)
6756#define EXTI_PR1_PIF19 EXTI_PR1_PIF19_Msk
6757#define EXTI_PR1_PIF20_Pos (20U)
6758#define EXTI_PR1_PIF20_Msk (0x1UL << EXTI_PR1_PIF20_Pos)
6759#define EXTI_PR1_PIF20 EXTI_PR1_PIF20_Msk
6760#define EXTI_PR1_PIF21_Pos (21U)
6761#define EXTI_PR1_PIF21_Msk (0x1UL << EXTI_PR1_PIF21_Pos)
6762#define EXTI_PR1_PIF21 EXTI_PR1_PIF21_Msk
6763#define EXTI_PR1_PIF22_Pos (22U)
6764#define EXTI_PR1_PIF22_Msk (0x1UL << EXTI_PR1_PIF22_Pos)
6765#define EXTI_PR1_PIF22 EXTI_PR1_PIF22_Msk
6767/******************* Bit definition for EXTI_IMR2 register ******************/
6768#define EXTI_IMR2_IM32_Pos (0U)
6769#define EXTI_IMR2_IM32_Msk (0x1UL << EXTI_IMR2_IM32_Pos)
6770#define EXTI_IMR2_IM32 EXTI_IMR2_IM32_Msk
6771#define EXTI_IMR2_IM33_Pos (1U)
6772#define EXTI_IMR2_IM33_Msk (0x1UL << EXTI_IMR2_IM33_Pos)
6773#define EXTI_IMR2_IM33 EXTI_IMR2_IM33_Msk
6774#define EXTI_IMR2_IM34_Pos (2U)
6775#define EXTI_IMR2_IM34_Msk (0x1UL << EXTI_IMR2_IM34_Pos)
6776#define EXTI_IMR2_IM34 EXTI_IMR2_IM34_Msk
6777#define EXTI_IMR2_IM37_Pos (5U)
6778#define EXTI_IMR2_IM37_Msk (0x1UL << EXTI_IMR2_IM37_Pos)
6779#define EXTI_IMR2_IM37 EXTI_IMR2_IM37_Msk
6780#define EXTI_IMR2_IM38_Pos (6U)
6781#define EXTI_IMR2_IM38_Msk (0x1UL << EXTI_IMR2_IM38_Pos)
6782#define EXTI_IMR2_IM38 EXTI_IMR2_IM38_Msk
6783#define EXTI_IMR2_IM_Pos (0U)
6784#define EXTI_IMR2_IM_Msk (0x67UL << EXTI_IMR2_IM_Pos)
6785#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk
6787/******************* Bit definition for EXTI_EMR2 register ******************/
6788#define EXTI_EMR2_EM32_Pos (0U)
6789#define EXTI_EMR2_EM32_Msk (0x1UL << EXTI_EMR2_EM32_Pos)
6790#define EXTI_EMR2_EM32 EXTI_EMR2_EM32_Msk
6791#define EXTI_EMR2_EM33_Pos (1U)
6792#define EXTI_EMR2_EM33_Msk (0x1UL << EXTI_EMR2_EM33_Pos)
6793#define EXTI_EMR2_EM33 EXTI_EMR2_EM33_Msk
6794#define EXTI_EMR2_EM34_Pos (2U)
6795#define EXTI_EMR2_EM34_Msk (0x1UL << EXTI_EMR2_EM34_Pos)
6796#define EXTI_EMR2_EM34 EXTI_EMR2_EM34_Msk
6797#define EXTI_EMR2_EM37_Pos (5U)
6798#define EXTI_EMR2_EM37_Msk (0x1UL << EXTI_EMR2_EM37_Pos)
6799#define EXTI_EMR2_EM37 EXTI_EMR2_EM37_Msk
6800#define EXTI_EMR2_EM38_Pos (6U)
6801#define EXTI_EMR2_EM38_Msk (0x1UL << EXTI_EMR2_EM38_Pos)
6802#define EXTI_EMR2_EM38 EXTI_EMR2_EM38_Msk
6803#define EXTI_EMR2_EM_Pos (0U)
6804#define EXTI_EMR2_EM_Msk (0x67UL << EXTI_EMR2_EM_Pos)
6805#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk
6807/****************** Bit definition for EXTI_RTSR2 register ******************/
6808#define EXTI_RTSR2_RT37_Pos (5U)
6809#define EXTI_RTSR2_RT37_Msk (0x1UL << EXTI_RTSR2_RT37_Pos)
6810#define EXTI_RTSR2_RT37 EXTI_RTSR2_RT37_Msk
6811#define EXTI_RTSR2_RT38_Pos (6U)
6812#define EXTI_RTSR2_RT38_Msk (0x1UL << EXTI_RTSR2_RT38_Pos)
6813#define EXTI_RTSR2_RT38 EXTI_RTSR2_RT38_Msk
6815/****************** Bit definition for EXTI_FTSR2 register ******************/
6816#define EXTI_FTSR2_FT37_Pos (5U)
6817#define EXTI_FTSR2_FT37_Msk (0x1UL << EXTI_FTSR2_FT37_Pos)
6818#define EXTI_FTSR2_FT37 EXTI_FTSR2_FT37_Msk
6819#define EXTI_FTSR2_FT38_Pos (6U)
6820#define EXTI_FTSR2_FT38_Msk (0x1UL << EXTI_FTSR2_FT38_Pos)
6821#define EXTI_FTSR2_FT38 EXTI_FTSR2_FT38_Msk
6823/****************** Bit definition for EXTI_SWIER2 register *****************/
6824#define EXTI_SWIER2_SWI37_Pos (5U)
6825#define EXTI_SWIER2_SWI37_Msk (0x1UL << EXTI_SWIER2_SWI37_Pos)
6826#define EXTI_SWIER2_SWI37 EXTI_SWIER2_SWI37_Msk
6827#define EXTI_SWIER2_SWI38_Pos (6U)
6828#define EXTI_SWIER2_SWI38_Msk (0x1UL << EXTI_SWIER2_SWI38_Pos)
6829#define EXTI_SWIER2_SWI38 EXTI_SWIER2_SWI38_Msk
6831/******************* Bit definition for EXTI_PR2 register *******************/
6832#define EXTI_PR2_PIF37_Pos (5U)
6833#define EXTI_PR2_PIF37_Msk (0x1UL << EXTI_PR2_PIF37_Pos)
6834#define EXTI_PR2_PIF37 EXTI_PR2_PIF37_Msk
6835#define EXTI_PR2_PIF38_Pos (6U)
6836#define EXTI_PR2_PIF38_Msk (0x1UL << EXTI_PR2_PIF38_Pos)
6837#define EXTI_PR2_PIF38 EXTI_PR2_PIF38_Msk
6840/******************************************************************************/
6841/* */
6842/* FLASH */
6843/* */
6844/******************************************************************************/
6845/******************* Bits definition for FLASH_ACR register *****************/
6846#define FLASH_ACR_LATENCY_Pos (0U)
6847#define FLASH_ACR_LATENCY_Msk (0x7UL << FLASH_ACR_LATENCY_Pos)
6848#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
6849#define FLASH_ACR_LATENCY_0WS (0x00000000UL)
6850#define FLASH_ACR_LATENCY_1WS (0x00000001UL)
6851#define FLASH_ACR_LATENCY_2WS (0x00000002UL)
6852#define FLASH_ACR_LATENCY_3WS (0x00000003UL)
6853#define FLASH_ACR_LATENCY_4WS (0x00000004UL)
6854#define FLASH_ACR_PRFTEN_Pos (8U)
6855#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos)
6856#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
6857#define FLASH_ACR_ICEN_Pos (9U)
6858#define FLASH_ACR_ICEN_Msk (0x1UL << FLASH_ACR_ICEN_Pos)
6859#define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk
6860#define FLASH_ACR_DCEN_Pos (10U)
6861#define FLASH_ACR_DCEN_Msk (0x1UL << FLASH_ACR_DCEN_Pos)
6862#define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk
6863#define FLASH_ACR_ICRST_Pos (11U)
6864#define FLASH_ACR_ICRST_Msk (0x1UL << FLASH_ACR_ICRST_Pos)
6865#define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk
6866#define FLASH_ACR_DCRST_Pos (12U)
6867#define FLASH_ACR_DCRST_Msk (0x1UL << FLASH_ACR_DCRST_Pos)
6868#define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk
6869#define FLASH_ACR_RUN_PD_Pos (13U)
6870#define FLASH_ACR_RUN_PD_Msk (0x1UL << FLASH_ACR_RUN_PD_Pos)
6871#define FLASH_ACR_RUN_PD FLASH_ACR_RUN_PD_Msk
6872#define FLASH_ACR_SLEEP_PD_Pos (14U)
6873#define FLASH_ACR_SLEEP_PD_Msk (0x1UL << FLASH_ACR_SLEEP_PD_Pos)
6874#define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk
6876/******************* Bits definition for FLASH_SR register ******************/
6877#define FLASH_SR_EOP_Pos (0U)
6878#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos)
6879#define FLASH_SR_EOP FLASH_SR_EOP_Msk
6880#define FLASH_SR_OPERR_Pos (1U)
6881#define FLASH_SR_OPERR_Msk (0x1UL << FLASH_SR_OPERR_Pos)
6882#define FLASH_SR_OPERR FLASH_SR_OPERR_Msk
6883#define FLASH_SR_PROGERR_Pos (3U)
6884#define FLASH_SR_PROGERR_Msk (0x1UL << FLASH_SR_PROGERR_Pos)
6885#define FLASH_SR_PROGERR FLASH_SR_PROGERR_Msk
6886#define FLASH_SR_WRPERR_Pos (4U)
6887#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos)
6888#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
6889#define FLASH_SR_PGAERR_Pos (5U)
6890#define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos)
6891#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
6892#define FLASH_SR_SIZERR_Pos (6U)
6893#define FLASH_SR_SIZERR_Msk (0x1UL << FLASH_SR_SIZERR_Pos)
6894#define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk
6895#define FLASH_SR_PGSERR_Pos (7U)
6896#define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos)
6897#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
6898#define FLASH_SR_MISERR_Pos (8U)
6899#define FLASH_SR_MISERR_Msk (0x1UL << FLASH_SR_MISERR_Pos)
6900#define FLASH_SR_MISERR FLASH_SR_MISERR_Msk
6901#define FLASH_SR_FASTERR_Pos (9U)
6902#define FLASH_SR_FASTERR_Msk (0x1UL << FLASH_SR_FASTERR_Pos)
6903#define FLASH_SR_FASTERR FLASH_SR_FASTERR_Msk
6904#define FLASH_SR_RDERR_Pos (14U)
6905#define FLASH_SR_RDERR_Msk (0x1UL << FLASH_SR_RDERR_Pos)
6906#define FLASH_SR_RDERR FLASH_SR_RDERR_Msk
6907#define FLASH_SR_OPTVERR_Pos (15U)
6908#define FLASH_SR_OPTVERR_Msk (0x1UL << FLASH_SR_OPTVERR_Pos)
6909#define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk
6910#define FLASH_SR_BSY_Pos (16U)
6911#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos)
6912#define FLASH_SR_BSY FLASH_SR_BSY_Msk
6913#define FLASH_SR_PEMPTY_Pos (17U)
6914#define FLASH_SR_PEMPTY_Msk (0x1UL << FLASH_SR_PEMPTY_Pos)
6915#define FLASH_SR_PEMPTY FLASH_SR_PEMPTY_Msk
6916
6917/******************* Bits definition for FLASH_CR register ******************/
6918#define FLASH_CR_PG_Pos (0U)
6919#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos)
6920#define FLASH_CR_PG FLASH_CR_PG_Msk
6921#define FLASH_CR_PER_Pos (1U)
6922#define FLASH_CR_PER_Msk (0x1UL << FLASH_CR_PER_Pos)
6923#define FLASH_CR_PER FLASH_CR_PER_Msk
6924#define FLASH_CR_MER1_Pos (2U)
6925#define FLASH_CR_MER1_Msk (0x1UL << FLASH_CR_MER1_Pos)
6926#define FLASH_CR_MER1 FLASH_CR_MER1_Msk
6927#define FLASH_CR_PNB_Pos (3U)
6928#define FLASH_CR_PNB_Msk (0x7FUL << FLASH_CR_PNB_Pos)
6929#define FLASH_CR_PNB FLASH_CR_PNB_Msk
6930#define FLASH_CR_STRT_Pos (16U)
6931#define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos)
6932#define FLASH_CR_STRT FLASH_CR_STRT_Msk
6933#define FLASH_CR_OPTSTRT_Pos (17U)
6934#define FLASH_CR_OPTSTRT_Msk (0x1UL << FLASH_CR_OPTSTRT_Pos)
6935#define FLASH_CR_OPTSTRT FLASH_CR_OPTSTRT_Msk
6936#define FLASH_CR_FSTPG_Pos (18U)
6937#define FLASH_CR_FSTPG_Msk (0x1UL << FLASH_CR_FSTPG_Pos)
6938#define FLASH_CR_FSTPG FLASH_CR_FSTPG_Msk
6939#define FLASH_CR_EOPIE_Pos (24U)
6940#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos)
6941#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
6942#define FLASH_CR_ERRIE_Pos (25U)
6943#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos)
6944#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk
6945#define FLASH_CR_RDERRIE_Pos (26U)
6946#define FLASH_CR_RDERRIE_Msk (0x1UL << FLASH_CR_RDERRIE_Pos)
6947#define FLASH_CR_RDERRIE FLASH_CR_RDERRIE_Msk
6948#define FLASH_CR_OBL_LAUNCH_Pos (27U)
6949#define FLASH_CR_OBL_LAUNCH_Msk (0x1UL << FLASH_CR_OBL_LAUNCH_Pos)
6950#define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk
6951#define FLASH_CR_OPTLOCK_Pos (30U)
6952#define FLASH_CR_OPTLOCK_Msk (0x1UL << FLASH_CR_OPTLOCK_Pos)
6953#define FLASH_CR_OPTLOCK FLASH_CR_OPTLOCK_Msk
6954#define FLASH_CR_LOCK_Pos (31U)
6955#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos)
6956#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
6957
6958/******************* Bits definition for FLASH_ECCR register ***************/
6959#define FLASH_ECCR_ADDR_ECC_Pos (0U)
6960#define FLASH_ECCR_ADDR_ECC_Msk (0x7FFFFUL << FLASH_ECCR_ADDR_ECC_Pos)
6961#define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk
6962#define FLASH_ECCR_SYSF_ECC_Pos (20U)
6963#define FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos)
6964#define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk
6965#define FLASH_ECCR_ECCIE_Pos (24U)
6966#define FLASH_ECCR_ECCIE_Msk (0x1UL << FLASH_ECCR_ECCIE_Pos)
6967#define FLASH_ECCR_ECCIE FLASH_ECCR_ECCIE_Msk
6968#define FLASH_ECCR_ECCC_Pos (30U)
6969#define FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos)
6970#define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk
6971#define FLASH_ECCR_ECCD_Pos (31U)
6972#define FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos)
6973#define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk
6974
6975/******************* Bits definition for FLASH_OPTR register ***************/
6976#define FLASH_OPTR_RDP_Pos (0U)
6977#define FLASH_OPTR_RDP_Msk (0xFFUL << FLASH_OPTR_RDP_Pos)
6978#define FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk
6979#define FLASH_OPTR_BOR_LEV_Pos (8U)
6980#define FLASH_OPTR_BOR_LEV_Msk (0x7UL << FLASH_OPTR_BOR_LEV_Pos)
6981#define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk
6982#define FLASH_OPTR_BOR_LEV_0 (0x0UL << FLASH_OPTR_BOR_LEV_Pos)
6983#define FLASH_OPTR_BOR_LEV_1 (0x1UL << FLASH_OPTR_BOR_LEV_Pos)
6984#define FLASH_OPTR_BOR_LEV_2 (0x2UL << FLASH_OPTR_BOR_LEV_Pos)
6985#define FLASH_OPTR_BOR_LEV_3 (0x3UL << FLASH_OPTR_BOR_LEV_Pos)
6986#define FLASH_OPTR_BOR_LEV_4 (0x4UL << FLASH_OPTR_BOR_LEV_Pos)
6987#define FLASH_OPTR_nRST_STOP_Pos (12U)
6988#define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos)
6989#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk
6990#define FLASH_OPTR_nRST_STDBY_Pos (13U)
6991#define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos)
6992#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk
6993#define FLASH_OPTR_nRST_SHDW_Pos (14U)
6994#define FLASH_OPTR_nRST_SHDW_Msk (0x1UL << FLASH_OPTR_nRST_SHDW_Pos)
6995#define FLASH_OPTR_nRST_SHDW FLASH_OPTR_nRST_SHDW_Msk
6996#define FLASH_OPTR_IWDG_SW_Pos (16U)
6997#define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos)
6998#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk
6999#define FLASH_OPTR_IWDG_STOP_Pos (17U)
7000#define FLASH_OPTR_IWDG_STOP_Msk (0x1UL << FLASH_OPTR_IWDG_STOP_Pos)
7001#define FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk
7002#define FLASH_OPTR_IWDG_STDBY_Pos (18U)
7003#define FLASH_OPTR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos)
7004#define FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk
7005#define FLASH_OPTR_WWDG_SW_Pos (19U)
7006#define FLASH_OPTR_WWDG_SW_Msk (0x1UL << FLASH_OPTR_WWDG_SW_Pos)
7007#define FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk
7008#define FLASH_OPTR_nBOOT1_Pos (23U)
7009#define FLASH_OPTR_nBOOT1_Msk (0x1UL << FLASH_OPTR_nBOOT1_Pos)
7010#define FLASH_OPTR_nBOOT1 FLASH_OPTR_nBOOT1_Msk
7011#define FLASH_OPTR_SRAM2_PE_Pos (24U)
7012#define FLASH_OPTR_SRAM2_PE_Msk (0x1UL << FLASH_OPTR_SRAM2_PE_Pos)
7013#define FLASH_OPTR_SRAM2_PE FLASH_OPTR_SRAM2_PE_Msk
7014#define FLASH_OPTR_SRAM2_RST_Pos (25U)
7015#define FLASH_OPTR_SRAM2_RST_Msk (0x1UL << FLASH_OPTR_SRAM2_RST_Pos)
7016#define FLASH_OPTR_SRAM2_RST FLASH_OPTR_SRAM2_RST_Msk
7017#define FLASH_OPTR_nSWBOOT0_Pos (26U)
7018#define FLASH_OPTR_nSWBOOT0_Msk (0x1UL << FLASH_OPTR_nSWBOOT0_Pos)
7019#define FLASH_OPTR_nSWBOOT0 FLASH_OPTR_nSWBOOT0_Msk
7020#define FLASH_OPTR_nBOOT0_Pos (27U)
7021#define FLASH_OPTR_nBOOT0_Msk (0x1UL << FLASH_OPTR_nBOOT0_Pos)
7022#define FLASH_OPTR_nBOOT0 FLASH_OPTR_nBOOT0_Msk
7023
7024/****************** Bits definition for FLASH_PCROP1SR register **********/
7025#define FLASH_PCROP1SR_PCROP1_STRT_Pos (0U)
7026#define FLASH_PCROP1SR_PCROP1_STRT_Msk (0x7FFFUL << FLASH_PCROP1SR_PCROP1_STRT_Pos)
7027#define FLASH_PCROP1SR_PCROP1_STRT FLASH_PCROP1SR_PCROP1_STRT_Msk
7028
7029/****************** Bits definition for FLASH_PCROP1ER register ***********/
7030#define FLASH_PCROP1ER_PCROP1_END_Pos (0U)
7031#define FLASH_PCROP1ER_PCROP1_END_Msk (0x7FFFUL << FLASH_PCROP1ER_PCROP1_END_Pos)
7032#define FLASH_PCROP1ER_PCROP1_END FLASH_PCROP1ER_PCROP1_END_Msk
7033#define FLASH_PCROP1ER_PCROP_RDP_Pos (31U)
7034#define FLASH_PCROP1ER_PCROP_RDP_Msk (0x1UL << FLASH_PCROP1ER_PCROP_RDP_Pos)
7035#define FLASH_PCROP1ER_PCROP_RDP FLASH_PCROP1ER_PCROP_RDP_Msk
7036
7037/****************** Bits definition for FLASH_WRP1AR register ***************/
7038#define FLASH_WRP1AR_WRP1A_STRT_Pos (0U)
7039#define FLASH_WRP1AR_WRP1A_STRT_Msk (0x7FUL << FLASH_WRP1AR_WRP1A_STRT_Pos)
7040#define FLASH_WRP1AR_WRP1A_STRT FLASH_WRP1AR_WRP1A_STRT_Msk
7041#define FLASH_WRP1AR_WRP1A_END_Pos (16U)
7042#define FLASH_WRP1AR_WRP1A_END_Msk (0x7FUL << FLASH_WRP1AR_WRP1A_END_Pos)
7043#define FLASH_WRP1AR_WRP1A_END FLASH_WRP1AR_WRP1A_END_Msk
7044
7045/****************** Bits definition for FLASH_WRPB1R register ***************/
7046#define FLASH_WRP1BR_WRP1B_STRT_Pos (0U)
7047#define FLASH_WRP1BR_WRP1B_STRT_Msk (0x7FUL << FLASH_WRP1BR_WRP1B_STRT_Pos)
7048#define FLASH_WRP1BR_WRP1B_STRT FLASH_WRP1BR_WRP1B_STRT_Msk
7049#define FLASH_WRP1BR_WRP1B_END_Pos (16U)
7050#define FLASH_WRP1BR_WRP1B_END_Msk (0x7FUL << FLASH_WRP1BR_WRP1B_END_Pos)
7051#define FLASH_WRP1BR_WRP1B_END FLASH_WRP1BR_WRP1B_END_Msk
7052
7053
7054
7055
7056/******************************************************************************/
7057/* */
7058/* General Purpose IOs (GPIO) */
7059/* */
7060/******************************************************************************/
7061/****************** Bits definition for GPIO_MODER register *****************/
7062#define GPIO_MODER_MODE0_Pos (0U)
7063#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos)
7064#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
7065#define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos)
7066#define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos)
7067#define GPIO_MODER_MODE1_Pos (2U)
7068#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos)
7069#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
7070#define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos)
7071#define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos)
7072#define GPIO_MODER_MODE2_Pos (4U)
7073#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos)
7074#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
7075#define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos)
7076#define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos)
7077#define GPIO_MODER_MODE3_Pos (6U)
7078#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos)
7079#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
7080#define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos)
7081#define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos)
7082#define GPIO_MODER_MODE4_Pos (8U)
7083#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos)
7084#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
7085#define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos)
7086#define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos)
7087#define GPIO_MODER_MODE5_Pos (10U)
7088#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos)
7089#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
7090#define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos)
7091#define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos)
7092#define GPIO_MODER_MODE6_Pos (12U)
7093#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos)
7094#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
7095#define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos)
7096#define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos)
7097#define GPIO_MODER_MODE7_Pos (14U)
7098#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos)
7099#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
7100#define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos)
7101#define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos)
7102#define GPIO_MODER_MODE8_Pos (16U)
7103#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos)
7104#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
7105#define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos)
7106#define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos)
7107#define GPIO_MODER_MODE9_Pos (18U)
7108#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos)
7109#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
7110#define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos)
7111#define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos)
7112#define GPIO_MODER_MODE10_Pos (20U)
7113#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos)
7114#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
7115#define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos)
7116#define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos)
7117#define GPIO_MODER_MODE11_Pos (22U)
7118#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos)
7119#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
7120#define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos)
7121#define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos)
7122#define GPIO_MODER_MODE12_Pos (24U)
7123#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos)
7124#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
7125#define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos)
7126#define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos)
7127#define GPIO_MODER_MODE13_Pos (26U)
7128#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos)
7129#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
7130#define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos)
7131#define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos)
7132#define GPIO_MODER_MODE14_Pos (28U)
7133#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos)
7134#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
7135#define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos)
7136#define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos)
7137#define GPIO_MODER_MODE15_Pos (30U)
7138#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos)
7139#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
7140#define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos)
7141#define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos)
7143/* Legacy defines */
7144#define GPIO_MODER_MODER0 GPIO_MODER_MODE0
7145#define GPIO_MODER_MODER0_0 GPIO_MODER_MODE0_0
7146#define GPIO_MODER_MODER0_1 GPIO_MODER_MODE0_1
7147#define GPIO_MODER_MODER1 GPIO_MODER_MODE1
7148#define GPIO_MODER_MODER1_0 GPIO_MODER_MODE1_0
7149#define GPIO_MODER_MODER1_1 GPIO_MODER_MODE1_1
7150#define GPIO_MODER_MODER2 GPIO_MODER_MODE2
7151#define GPIO_MODER_MODER2_0 GPIO_MODER_MODE2_0
7152#define GPIO_MODER_MODER2_1 GPIO_MODER_MODE2_1
7153#define GPIO_MODER_MODER3 GPIO_MODER_MODE3
7154#define GPIO_MODER_MODER3_0 GPIO_MODER_MODE3_0
7155#define GPIO_MODER_MODER3_1 GPIO_MODER_MODE3_1
7156#define GPIO_MODER_MODER4 GPIO_MODER_MODE4
7157#define GPIO_MODER_MODER4_0 GPIO_MODER_MODE4_0
7158#define GPIO_MODER_MODER4_1 GPIO_MODER_MODE4_1
7159#define GPIO_MODER_MODER5 GPIO_MODER_MODE5
7160#define GPIO_MODER_MODER5_0 GPIO_MODER_MODE5_0
7161#define GPIO_MODER_MODER5_1 GPIO_MODER_MODE5_1
7162#define GPIO_MODER_MODER6 GPIO_MODER_MODE6
7163#define GPIO_MODER_MODER6_0 GPIO_MODER_MODE6_0
7164#define GPIO_MODER_MODER6_1 GPIO_MODER_MODE6_1
7165#define GPIO_MODER_MODER7 GPIO_MODER_MODE7
7166#define GPIO_MODER_MODER7_0 GPIO_MODER_MODE7_0
7167#define GPIO_MODER_MODER7_1 GPIO_MODER_MODE7_1
7168#define GPIO_MODER_MODER8 GPIO_MODER_MODE8
7169#define GPIO_MODER_MODER8_0 GPIO_MODER_MODE8_0
7170#define GPIO_MODER_MODER8_1 GPIO_MODER_MODE8_1
7171#define GPIO_MODER_MODER9 GPIO_MODER_MODE9
7172#define GPIO_MODER_MODER9_0 GPIO_MODER_MODE9_0
7173#define GPIO_MODER_MODER9_1 GPIO_MODER_MODE9_1
7174#define GPIO_MODER_MODER10 GPIO_MODER_MODE10
7175#define GPIO_MODER_MODER10_0 GPIO_MODER_MODE10_0
7176#define GPIO_MODER_MODER10_1 GPIO_MODER_MODE10_1
7177#define GPIO_MODER_MODER11 GPIO_MODER_MODE11
7178#define GPIO_MODER_MODER11_0 GPIO_MODER_MODE11_0
7179#define GPIO_MODER_MODER11_1 GPIO_MODER_MODE11_1
7180#define GPIO_MODER_MODER12 GPIO_MODER_MODE12
7181#define GPIO_MODER_MODER12_0 GPIO_MODER_MODE12_0
7182#define GPIO_MODER_MODER12_1 GPIO_MODER_MODE12_1
7183#define GPIO_MODER_MODER13 GPIO_MODER_MODE13
7184#define GPIO_MODER_MODER13_0 GPIO_MODER_MODE13_0
7185#define GPIO_MODER_MODER13_1 GPIO_MODER_MODE13_1
7186#define GPIO_MODER_MODER14 GPIO_MODER_MODE14
7187#define GPIO_MODER_MODER14_0 GPIO_MODER_MODE14_0
7188#define GPIO_MODER_MODER14_1 GPIO_MODER_MODE14_1
7189#define GPIO_MODER_MODER15 GPIO_MODER_MODE15
7190#define GPIO_MODER_MODER15_0 GPIO_MODER_MODE15_0
7191#define GPIO_MODER_MODER15_1 GPIO_MODER_MODE15_1
7192
7193/****************** Bits definition for GPIO_OTYPER register ****************/
7194#define GPIO_OTYPER_OT0_Pos (0U)
7195#define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos)
7196#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
7197#define GPIO_OTYPER_OT1_Pos (1U)
7198#define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos)
7199#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
7200#define GPIO_OTYPER_OT2_Pos (2U)
7201#define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos)
7202#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
7203#define GPIO_OTYPER_OT3_Pos (3U)
7204#define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos)
7205#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
7206#define GPIO_OTYPER_OT4_Pos (4U)
7207#define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos)
7208#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
7209#define GPIO_OTYPER_OT5_Pos (5U)
7210#define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos)
7211#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
7212#define GPIO_OTYPER_OT6_Pos (6U)
7213#define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos)
7214#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
7215#define GPIO_OTYPER_OT7_Pos (7U)
7216#define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos)
7217#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
7218#define GPIO_OTYPER_OT8_Pos (8U)
7219#define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos)
7220#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
7221#define GPIO_OTYPER_OT9_Pos (9U)
7222#define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos)
7223#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
7224#define GPIO_OTYPER_OT10_Pos (10U)
7225#define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos)
7226#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
7227#define GPIO_OTYPER_OT11_Pos (11U)
7228#define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos)
7229#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
7230#define GPIO_OTYPER_OT12_Pos (12U)
7231#define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos)
7232#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
7233#define GPIO_OTYPER_OT13_Pos (13U)
7234#define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos)
7235#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
7236#define GPIO_OTYPER_OT14_Pos (14U)
7237#define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos)
7238#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
7239#define GPIO_OTYPER_OT15_Pos (15U)
7240#define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos)
7241#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
7242
7243/* Legacy defines */
7244#define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
7245#define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
7246#define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
7247#define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
7248#define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
7249#define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
7250#define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
7251#define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
7252#define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
7253#define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
7254#define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
7255#define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
7256#define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
7257#define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
7258#define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
7259#define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
7260
7261/****************** Bits definition for GPIO_OSPEEDR register ***************/
7262#define GPIO_OSPEEDR_OSPEED0_Pos (0U)
7263#define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)
7264#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
7265#define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)
7266#define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)
7267#define GPIO_OSPEEDR_OSPEED1_Pos (2U)
7268#define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)
7269#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
7270#define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)
7271#define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)
7272#define GPIO_OSPEEDR_OSPEED2_Pos (4U)
7273#define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)
7274#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
7275#define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)
7276#define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)
7277#define GPIO_OSPEEDR_OSPEED3_Pos (6U)
7278#define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)
7279#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
7280#define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)
7281#define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)
7282#define GPIO_OSPEEDR_OSPEED4_Pos (8U)
7283#define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)
7284#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
7285#define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)
7286#define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)
7287#define GPIO_OSPEEDR_OSPEED5_Pos (10U)
7288#define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)
7289#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
7290#define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)
7291#define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)
7292#define GPIO_OSPEEDR_OSPEED6_Pos (12U)
7293#define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)
7294#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
7295#define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)
7296#define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)
7297#define GPIO_OSPEEDR_OSPEED7_Pos (14U)
7298#define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)
7299#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
7300#define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)
7301#define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)
7302#define GPIO_OSPEEDR_OSPEED8_Pos (16U)
7303#define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)
7304#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
7305#define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)
7306#define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)
7307#define GPIO_OSPEEDR_OSPEED9_Pos (18U)
7308#define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)
7309#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
7310#define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)
7311#define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)
7312#define GPIO_OSPEEDR_OSPEED10_Pos (20U)
7313#define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)
7314#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
7315#define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)
7316#define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)
7317#define GPIO_OSPEEDR_OSPEED11_Pos (22U)
7318#define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)
7319#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
7320#define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)
7321#define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)
7322#define GPIO_OSPEEDR_OSPEED12_Pos (24U)
7323#define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)
7324#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
7325#define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)
7326#define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)
7327#define GPIO_OSPEEDR_OSPEED13_Pos (26U)
7328#define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)
7329#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
7330#define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)
7331#define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)
7332#define GPIO_OSPEEDR_OSPEED14_Pos (28U)
7333#define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)
7334#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
7335#define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)
7336#define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)
7337#define GPIO_OSPEEDR_OSPEED15_Pos (30U)
7338#define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)
7339#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
7340#define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)
7341#define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)
7343/* Legacy defines */
7344#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0
7345#define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0
7346#define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1
7347#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1
7348#define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0
7349#define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1
7350#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2
7351#define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0
7352#define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1
7353#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3
7354#define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0
7355#define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1
7356#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4
7357#define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0
7358#define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1
7359#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5
7360#define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0
7361#define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1
7362#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6
7363#define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0
7364#define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1
7365#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7
7366#define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0
7367#define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1
7368#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8
7369#define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0
7370#define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1
7371#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9
7372#define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0
7373#define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1
7374#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10
7375#define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0
7376#define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1
7377#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11
7378#define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0
7379#define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1
7380#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12
7381#define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0
7382#define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1
7383#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13
7384#define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0
7385#define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1
7386#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14
7387#define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0
7388#define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1
7389#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15
7390#define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0
7391#define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1
7392
7393/****************** Bits definition for GPIO_PUPDR register *****************/
7394#define GPIO_PUPDR_PUPD0_Pos (0U)
7395#define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos)
7396#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
7397#define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos)
7398#define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos)
7399#define GPIO_PUPDR_PUPD1_Pos (2U)
7400#define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos)
7401#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
7402#define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos)
7403#define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos)
7404#define GPIO_PUPDR_PUPD2_Pos (4U)
7405#define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos)
7406#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
7407#define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos)
7408#define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos)
7409#define GPIO_PUPDR_PUPD3_Pos (6U)
7410#define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos)
7411#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
7412#define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos)
7413#define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos)
7414#define GPIO_PUPDR_PUPD4_Pos (8U)
7415#define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos)
7416#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
7417#define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos)
7418#define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos)
7419#define GPIO_PUPDR_PUPD5_Pos (10U)
7420#define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos)
7421#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
7422#define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos)
7423#define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos)
7424#define GPIO_PUPDR_PUPD6_Pos (12U)
7425#define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos)
7426#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
7427#define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos)
7428#define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos)
7429#define GPIO_PUPDR_PUPD7_Pos (14U)
7430#define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos)
7431#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
7432#define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos)
7433#define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos)
7434#define GPIO_PUPDR_PUPD8_Pos (16U)
7435#define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos)
7436#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
7437#define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos)
7438#define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos)
7439#define GPIO_PUPDR_PUPD9_Pos (18U)
7440#define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos)
7441#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
7442#define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos)
7443#define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos)
7444#define GPIO_PUPDR_PUPD10_Pos (20U)
7445#define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos)
7446#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
7447#define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos)
7448#define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos)
7449#define GPIO_PUPDR_PUPD11_Pos (22U)
7450#define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos)
7451#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
7452#define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos)
7453#define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos)
7454#define GPIO_PUPDR_PUPD12_Pos (24U)
7455#define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos)
7456#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
7457#define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos)
7458#define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos)
7459#define GPIO_PUPDR_PUPD13_Pos (26U)
7460#define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos)
7461#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
7462#define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos)
7463#define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos)
7464#define GPIO_PUPDR_PUPD14_Pos (28U)
7465#define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos)
7466#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
7467#define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos)
7468#define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos)
7469#define GPIO_PUPDR_PUPD15_Pos (30U)
7470#define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos)
7471#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
7472#define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos)
7473#define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos)
7475/* Legacy defines */
7476#define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0
7477#define GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0
7478#define GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1
7479#define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1
7480#define GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0
7481#define GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1
7482#define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2
7483#define GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0
7484#define GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1
7485#define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3
7486#define GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0
7487#define GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1
7488#define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4
7489#define GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0
7490#define GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1
7491#define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5
7492#define GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0
7493#define GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1
7494#define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6
7495#define GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0
7496#define GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1
7497#define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7
7498#define GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0
7499#define GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1
7500#define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8
7501#define GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0
7502#define GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1
7503#define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9
7504#define GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0
7505#define GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1
7506#define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10
7507#define GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0
7508#define GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1
7509#define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11
7510#define GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0
7511#define GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1
7512#define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12
7513#define GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0
7514#define GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1
7515#define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13
7516#define GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0
7517#define GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1
7518#define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14
7519#define GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0
7520#define GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1
7521#define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15
7522#define GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0
7523#define GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1
7524
7525/****************** Bits definition for GPIO_IDR register *******************/
7526#define GPIO_IDR_ID0_Pos (0U)
7527#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos)
7528#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
7529#define GPIO_IDR_ID1_Pos (1U)
7530#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos)
7531#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
7532#define GPIO_IDR_ID2_Pos (2U)
7533#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos)
7534#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
7535#define GPIO_IDR_ID3_Pos (3U)
7536#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos)
7537#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
7538#define GPIO_IDR_ID4_Pos (4U)
7539#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos)
7540#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
7541#define GPIO_IDR_ID5_Pos (5U)
7542#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos)
7543#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
7544#define GPIO_IDR_ID6_Pos (6U)
7545#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos)
7546#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
7547#define GPIO_IDR_ID7_Pos (7U)
7548#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos)
7549#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
7550#define GPIO_IDR_ID8_Pos (8U)
7551#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos)
7552#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
7553#define GPIO_IDR_ID9_Pos (9U)
7554#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos)
7555#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
7556#define GPIO_IDR_ID10_Pos (10U)
7557#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos)
7558#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
7559#define GPIO_IDR_ID11_Pos (11U)
7560#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos)
7561#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
7562#define GPIO_IDR_ID12_Pos (12U)
7563#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos)
7564#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
7565#define GPIO_IDR_ID13_Pos (13U)
7566#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos)
7567#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
7568#define GPIO_IDR_ID14_Pos (14U)
7569#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos)
7570#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
7571#define GPIO_IDR_ID15_Pos (15U)
7572#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos)
7573#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
7574
7575/* Legacy defines */
7576#define GPIO_IDR_IDR_0 GPIO_IDR_ID0
7577#define GPIO_IDR_IDR_1 GPIO_IDR_ID1
7578#define GPIO_IDR_IDR_2 GPIO_IDR_ID2
7579#define GPIO_IDR_IDR_3 GPIO_IDR_ID3
7580#define GPIO_IDR_IDR_4 GPIO_IDR_ID4
7581#define GPIO_IDR_IDR_5 GPIO_IDR_ID5
7582#define GPIO_IDR_IDR_6 GPIO_IDR_ID6
7583#define GPIO_IDR_IDR_7 GPIO_IDR_ID7
7584#define GPIO_IDR_IDR_8 GPIO_IDR_ID8
7585#define GPIO_IDR_IDR_9 GPIO_IDR_ID9
7586#define GPIO_IDR_IDR_10 GPIO_IDR_ID10
7587#define GPIO_IDR_IDR_11 GPIO_IDR_ID11
7588#define GPIO_IDR_IDR_12 GPIO_IDR_ID12
7589#define GPIO_IDR_IDR_13 GPIO_IDR_ID13
7590#define GPIO_IDR_IDR_14 GPIO_IDR_ID14
7591#define GPIO_IDR_IDR_15 GPIO_IDR_ID15
7592
7593/* Old GPIO_IDR register bits definition, maintained for legacy purpose */
7594#define GPIO_OTYPER_IDR_0 GPIO_IDR_ID0
7595#define GPIO_OTYPER_IDR_1 GPIO_IDR_ID1
7596#define GPIO_OTYPER_IDR_2 GPIO_IDR_ID2
7597#define GPIO_OTYPER_IDR_3 GPIO_IDR_ID3
7598#define GPIO_OTYPER_IDR_4 GPIO_IDR_ID4
7599#define GPIO_OTYPER_IDR_5 GPIO_IDR_ID5
7600#define GPIO_OTYPER_IDR_6 GPIO_IDR_ID6
7601#define GPIO_OTYPER_IDR_7 GPIO_IDR_ID7
7602#define GPIO_OTYPER_IDR_8 GPIO_IDR_ID8
7603#define GPIO_OTYPER_IDR_9 GPIO_IDR_ID9
7604#define GPIO_OTYPER_IDR_10 GPIO_IDR_ID10
7605#define GPIO_OTYPER_IDR_11 GPIO_IDR_ID11
7606#define GPIO_OTYPER_IDR_12 GPIO_IDR_ID12
7607#define GPIO_OTYPER_IDR_13 GPIO_IDR_ID13
7608#define GPIO_OTYPER_IDR_14 GPIO_IDR_ID14
7609#define GPIO_OTYPER_IDR_15 GPIO_IDR_ID15
7610
7611/****************** Bits definition for GPIO_ODR register *******************/
7612#define GPIO_ODR_OD0_Pos (0U)
7613#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos)
7614#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
7615#define GPIO_ODR_OD1_Pos (1U)
7616#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos)
7617#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
7618#define GPIO_ODR_OD2_Pos (2U)
7619#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos)
7620#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
7621#define GPIO_ODR_OD3_Pos (3U)
7622#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos)
7623#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
7624#define GPIO_ODR_OD4_Pos (4U)
7625#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos)
7626#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
7627#define GPIO_ODR_OD5_Pos (5U)
7628#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos)
7629#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
7630#define GPIO_ODR_OD6_Pos (6U)
7631#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos)
7632#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
7633#define GPIO_ODR_OD7_Pos (7U)
7634#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos)
7635#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
7636#define GPIO_ODR_OD8_Pos (8U)
7637#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos)
7638#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
7639#define GPIO_ODR_OD9_Pos (9U)
7640#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos)
7641#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
7642#define GPIO_ODR_OD10_Pos (10U)
7643#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos)
7644#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
7645#define GPIO_ODR_OD11_Pos (11U)
7646#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos)
7647#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
7648#define GPIO_ODR_OD12_Pos (12U)
7649#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos)
7650#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
7651#define GPIO_ODR_OD13_Pos (13U)
7652#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos)
7653#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
7654#define GPIO_ODR_OD14_Pos (14U)
7655#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos)
7656#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
7657#define GPIO_ODR_OD15_Pos (15U)
7658#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos)
7659#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
7660
7661/* Legacy defines */
7662#define GPIO_ODR_ODR_0 GPIO_ODR_OD0
7663#define GPIO_ODR_ODR_1 GPIO_ODR_OD1
7664#define GPIO_ODR_ODR_2 GPIO_ODR_OD2
7665#define GPIO_ODR_ODR_3 GPIO_ODR_OD3
7666#define GPIO_ODR_ODR_4 GPIO_ODR_OD4
7667#define GPIO_ODR_ODR_5 GPIO_ODR_OD5
7668#define GPIO_ODR_ODR_6 GPIO_ODR_OD6
7669#define GPIO_ODR_ODR_7 GPIO_ODR_OD7
7670#define GPIO_ODR_ODR_8 GPIO_ODR_OD8
7671#define GPIO_ODR_ODR_9 GPIO_ODR_OD9
7672#define GPIO_ODR_ODR_10 GPIO_ODR_OD10
7673#define GPIO_ODR_ODR_11 GPIO_ODR_OD11
7674#define GPIO_ODR_ODR_12 GPIO_ODR_OD12
7675#define GPIO_ODR_ODR_13 GPIO_ODR_OD13
7676#define GPIO_ODR_ODR_14 GPIO_ODR_OD14
7677#define GPIO_ODR_ODR_15 GPIO_ODR_OD15
7678
7679/* Old GPIO_ODR register bits definition, maintained for legacy purpose */
7680#define GPIO_OTYPER_ODR_0 GPIO_ODR_OD0
7681#define GPIO_OTYPER_ODR_1 GPIO_ODR_OD1
7682#define GPIO_OTYPER_ODR_2 GPIO_ODR_OD2
7683#define GPIO_OTYPER_ODR_3 GPIO_ODR_OD3
7684#define GPIO_OTYPER_ODR_4 GPIO_ODR_OD4
7685#define GPIO_OTYPER_ODR_5 GPIO_ODR_OD5
7686#define GPIO_OTYPER_ODR_6 GPIO_ODR_OD6
7687#define GPIO_OTYPER_ODR_7 GPIO_ODR_OD7
7688#define GPIO_OTYPER_ODR_8 GPIO_ODR_OD8
7689#define GPIO_OTYPER_ODR_9 GPIO_ODR_OD9
7690#define GPIO_OTYPER_ODR_10 GPIO_ODR_OD10
7691#define GPIO_OTYPER_ODR_11 GPIO_ODR_OD11
7692#define GPIO_OTYPER_ODR_12 GPIO_ODR_OD12
7693#define GPIO_OTYPER_ODR_13 GPIO_ODR_OD13
7694#define GPIO_OTYPER_ODR_14 GPIO_ODR_OD14
7695#define GPIO_OTYPER_ODR_15 GPIO_ODR_OD15
7696
7697/****************** Bits definition for GPIO_BSRR register ******************/
7698#define GPIO_BSRR_BS0_Pos (0U)
7699#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos)
7700#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
7701#define GPIO_BSRR_BS1_Pos (1U)
7702#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos)
7703#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
7704#define GPIO_BSRR_BS2_Pos (2U)
7705#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos)
7706#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
7707#define GPIO_BSRR_BS3_Pos (3U)
7708#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos)
7709#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
7710#define GPIO_BSRR_BS4_Pos (4U)
7711#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos)
7712#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
7713#define GPIO_BSRR_BS5_Pos (5U)
7714#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos)
7715#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
7716#define GPIO_BSRR_BS6_Pos (6U)
7717#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos)
7718#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
7719#define GPIO_BSRR_BS7_Pos (7U)
7720#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos)
7721#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
7722#define GPIO_BSRR_BS8_Pos (8U)
7723#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos)
7724#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
7725#define GPIO_BSRR_BS9_Pos (9U)
7726#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos)
7727#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
7728#define GPIO_BSRR_BS10_Pos (10U)
7729#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos)
7730#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
7731#define GPIO_BSRR_BS11_Pos (11U)
7732#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos)
7733#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
7734#define GPIO_BSRR_BS12_Pos (12U)
7735#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos)
7736#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
7737#define GPIO_BSRR_BS13_Pos (13U)
7738#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos)
7739#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
7740#define GPIO_BSRR_BS14_Pos (14U)
7741#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos)
7742#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
7743#define GPIO_BSRR_BS15_Pos (15U)
7744#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos)
7745#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
7746#define GPIO_BSRR_BR0_Pos (16U)
7747#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos)
7748#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
7749#define GPIO_BSRR_BR1_Pos (17U)
7750#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos)
7751#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
7752#define GPIO_BSRR_BR2_Pos (18U)
7753#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos)
7754#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
7755#define GPIO_BSRR_BR3_Pos (19U)
7756#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos)
7757#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
7758#define GPIO_BSRR_BR4_Pos (20U)
7759#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos)
7760#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
7761#define GPIO_BSRR_BR5_Pos (21U)
7762#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos)
7763#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
7764#define GPIO_BSRR_BR6_Pos (22U)
7765#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos)
7766#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
7767#define GPIO_BSRR_BR7_Pos (23U)
7768#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos)
7769#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
7770#define GPIO_BSRR_BR8_Pos (24U)
7771#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos)
7772#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
7773#define GPIO_BSRR_BR9_Pos (25U)
7774#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos)
7775#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
7776#define GPIO_BSRR_BR10_Pos (26U)
7777#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos)
7778#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
7779#define GPIO_BSRR_BR11_Pos (27U)
7780#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos)
7781#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
7782#define GPIO_BSRR_BR12_Pos (28U)
7783#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos)
7784#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
7785#define GPIO_BSRR_BR13_Pos (29U)
7786#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos)
7787#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
7788#define GPIO_BSRR_BR14_Pos (30U)
7789#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos)
7790#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
7791#define GPIO_BSRR_BR15_Pos (31U)
7792#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos)
7793#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
7794
7795/* Legacy defines */
7796#define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
7797#define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
7798#define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
7799#define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
7800#define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
7801#define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
7802#define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
7803#define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
7804#define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
7805#define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
7806#define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
7807#define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
7808#define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
7809#define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
7810#define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
7811#define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
7812#define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
7813#define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
7814#define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
7815#define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
7816#define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
7817#define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
7818#define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
7819#define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
7820#define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
7821#define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
7822#define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
7823#define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
7824#define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
7825#define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
7826#define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
7827#define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
7828
7829/****************** Bit definition for GPIO_LCKR register *********************/
7830#define GPIO_LCKR_LCK0_Pos (0U)
7831#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos)
7832#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
7833#define GPIO_LCKR_LCK1_Pos (1U)
7834#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos)
7835#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
7836#define GPIO_LCKR_LCK2_Pos (2U)
7837#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos)
7838#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
7839#define GPIO_LCKR_LCK3_Pos (3U)
7840#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos)
7841#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
7842#define GPIO_LCKR_LCK4_Pos (4U)
7843#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos)
7844#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
7845#define GPIO_LCKR_LCK5_Pos (5U)
7846#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos)
7847#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
7848#define GPIO_LCKR_LCK6_Pos (6U)
7849#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos)
7850#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
7851#define GPIO_LCKR_LCK7_Pos (7U)
7852#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos)
7853#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
7854#define GPIO_LCKR_LCK8_Pos (8U)
7855#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos)
7856#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
7857#define GPIO_LCKR_LCK9_Pos (9U)
7858#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos)
7859#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
7860#define GPIO_LCKR_LCK10_Pos (10U)
7861#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos)
7862#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
7863#define GPIO_LCKR_LCK11_Pos (11U)
7864#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos)
7865#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
7866#define GPIO_LCKR_LCK12_Pos (12U)
7867#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos)
7868#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
7869#define GPIO_LCKR_LCK13_Pos (13U)
7870#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos)
7871#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
7872#define GPIO_LCKR_LCK14_Pos (14U)
7873#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos)
7874#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
7875#define GPIO_LCKR_LCK15_Pos (15U)
7876#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos)
7877#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
7878#define GPIO_LCKR_LCKK_Pos (16U)
7879#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos)
7880#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
7881
7882/****************** Bit definition for GPIO_AFRL register *********************/
7883#define GPIO_AFRL_AFSEL0_Pos (0U)
7884#define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos)
7885#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
7886#define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos)
7887#define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos)
7888#define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos)
7889#define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos)
7890#define GPIO_AFRL_AFSEL1_Pos (4U)
7891#define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos)
7892#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
7893#define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos)
7894#define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos)
7895#define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos)
7896#define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos)
7897#define GPIO_AFRL_AFSEL2_Pos (8U)
7898#define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos)
7899#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
7900#define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos)
7901#define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos)
7902#define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos)
7903#define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos)
7904#define GPIO_AFRL_AFSEL3_Pos (12U)
7905#define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos)
7906#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
7907#define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos)
7908#define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos)
7909#define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos)
7910#define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos)
7911#define GPIO_AFRL_AFSEL4_Pos (16U)
7912#define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos)
7913#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
7914#define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos)
7915#define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos)
7916#define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos)
7917#define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos)
7918#define GPIO_AFRL_AFSEL5_Pos (20U)
7919#define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos)
7920#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
7921#define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos)
7922#define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos)
7923#define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos)
7924#define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos)
7925#define GPIO_AFRL_AFSEL6_Pos (24U)
7926#define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos)
7927#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
7928#define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos)
7929#define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos)
7930#define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos)
7931#define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos)
7932#define GPIO_AFRL_AFSEL7_Pos (28U)
7933#define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos)
7934#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
7935#define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos)
7936#define GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos)
7937#define GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos)
7938#define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos)
7940/* Legacy defines */
7941#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
7942#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
7943#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
7944#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
7945#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
7946#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
7947#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
7948#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
7949
7950/****************** Bit definition for GPIO_AFRH register *********************/
7951#define GPIO_AFRH_AFSEL8_Pos (0U)
7952#define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos)
7953#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
7954#define GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos)
7955#define GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos)
7956#define GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos)
7957#define GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos)
7958#define GPIO_AFRH_AFSEL9_Pos (4U)
7959#define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos)
7960#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
7961#define GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos)
7962#define GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos)
7963#define GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos)
7964#define GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos)
7965#define GPIO_AFRH_AFSEL10_Pos (8U)
7966#define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos)
7967#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
7968#define GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos)
7969#define GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos)
7970#define GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos)
7971#define GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos)
7972#define GPIO_AFRH_AFSEL11_Pos (12U)
7973#define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos)
7974#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
7975#define GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos)
7976#define GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos)
7977#define GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos)
7978#define GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos)
7979#define GPIO_AFRH_AFSEL12_Pos (16U)
7980#define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos)
7981#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
7982#define GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos)
7983#define GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos)
7984#define GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos)
7985#define GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos)
7986#define GPIO_AFRH_AFSEL13_Pos (20U)
7987#define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos)
7988#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
7989#define GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos)
7990#define GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos)
7991#define GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos)
7992#define GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos)
7993#define GPIO_AFRH_AFSEL14_Pos (24U)
7994#define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos)
7995#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
7996#define GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos)
7997#define GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos)
7998#define GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos)
7999#define GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos)
8000#define GPIO_AFRH_AFSEL15_Pos (28U)
8001#define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos)
8002#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
8003#define GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos)
8004#define GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos)
8005#define GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos)
8006#define GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos)
8008/* Legacy defines */
8009#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
8010#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
8011#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
8012#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
8013#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
8014#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
8015#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
8016#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
8017
8018/****************** Bits definition for GPIO_BRR register ******************/
8019#define GPIO_BRR_BR0_Pos (0U)
8020#define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos)
8021#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk
8022#define GPIO_BRR_BR1_Pos (1U)
8023#define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos)
8024#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk
8025#define GPIO_BRR_BR2_Pos (2U)
8026#define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos)
8027#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk
8028#define GPIO_BRR_BR3_Pos (3U)
8029#define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos)
8030#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk
8031#define GPIO_BRR_BR4_Pos (4U)
8032#define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos)
8033#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk
8034#define GPIO_BRR_BR5_Pos (5U)
8035#define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos)
8036#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk
8037#define GPIO_BRR_BR6_Pos (6U)
8038#define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos)
8039#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk
8040#define GPIO_BRR_BR7_Pos (7U)
8041#define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos)
8042#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk
8043#define GPIO_BRR_BR8_Pos (8U)
8044#define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos)
8045#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk
8046#define GPIO_BRR_BR9_Pos (9U)
8047#define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos)
8048#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk
8049#define GPIO_BRR_BR10_Pos (10U)
8050#define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos)
8051#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk
8052#define GPIO_BRR_BR11_Pos (11U)
8053#define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos)
8054#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk
8055#define GPIO_BRR_BR12_Pos (12U)
8056#define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos)
8057#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk
8058#define GPIO_BRR_BR13_Pos (13U)
8059#define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos)
8060#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk
8061#define GPIO_BRR_BR14_Pos (14U)
8062#define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos)
8063#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk
8064#define GPIO_BRR_BR15_Pos (15U)
8065#define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos)
8066#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk
8067
8068/* Legacy defines */
8069#define GPIO_BRR_BR_0 GPIO_BRR_BR0
8070#define GPIO_BRR_BR_1 GPIO_BRR_BR1
8071#define GPIO_BRR_BR_2 GPIO_BRR_BR2
8072#define GPIO_BRR_BR_3 GPIO_BRR_BR3
8073#define GPIO_BRR_BR_4 GPIO_BRR_BR4
8074#define GPIO_BRR_BR_5 GPIO_BRR_BR5
8075#define GPIO_BRR_BR_6 GPIO_BRR_BR6
8076#define GPIO_BRR_BR_7 GPIO_BRR_BR7
8077#define GPIO_BRR_BR_8 GPIO_BRR_BR8
8078#define GPIO_BRR_BR_9 GPIO_BRR_BR9
8079#define GPIO_BRR_BR_10 GPIO_BRR_BR10
8080#define GPIO_BRR_BR_11 GPIO_BRR_BR11
8081#define GPIO_BRR_BR_12 GPIO_BRR_BR12
8082#define GPIO_BRR_BR_13 GPIO_BRR_BR13
8083#define GPIO_BRR_BR_14 GPIO_BRR_BR14
8084#define GPIO_BRR_BR_15 GPIO_BRR_BR15
8085
8086
8087
8088/******************************************************************************/
8089/* */
8090/* Inter-integrated Circuit Interface (I2C) */
8091/* */
8092/******************************************************************************/
8093/******************* Bit definition for I2C_CR1 register *******************/
8094#define I2C_CR1_PE_Pos (0U)
8095#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos)
8096#define I2C_CR1_PE I2C_CR1_PE_Msk
8097#define I2C_CR1_TXIE_Pos (1U)
8098#define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos)
8099#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk
8100#define I2C_CR1_RXIE_Pos (2U)
8101#define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos)
8102#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk
8103#define I2C_CR1_ADDRIE_Pos (3U)
8104#define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos)
8105#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk
8106#define I2C_CR1_NACKIE_Pos (4U)
8107#define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos)
8108#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk
8109#define I2C_CR1_STOPIE_Pos (5U)
8110#define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos)
8111#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk
8112#define I2C_CR1_TCIE_Pos (6U)
8113#define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos)
8114#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk
8115#define I2C_CR1_ERRIE_Pos (7U)
8116#define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos)
8117#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk
8118#define I2C_CR1_DNF_Pos (8U)
8119#define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos)
8120#define I2C_CR1_DNF I2C_CR1_DNF_Msk
8121#define I2C_CR1_ANFOFF_Pos (12U)
8122#define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos)
8123#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk
8124#define I2C_CR1_SWRST_Pos (13U)
8125#define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos)
8126#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk
8127#define I2C_CR1_TXDMAEN_Pos (14U)
8128#define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos)
8129#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk
8130#define I2C_CR1_RXDMAEN_Pos (15U)
8131#define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos)
8132#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk
8133#define I2C_CR1_SBC_Pos (16U)
8134#define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos)
8135#define I2C_CR1_SBC I2C_CR1_SBC_Msk
8136#define I2C_CR1_NOSTRETCH_Pos (17U)
8137#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos)
8138#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk
8139#define I2C_CR1_WUPEN_Pos (18U)
8140#define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos)
8141#define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk
8142#define I2C_CR1_GCEN_Pos (19U)
8143#define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos)
8144#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk
8145#define I2C_CR1_SMBHEN_Pos (20U)
8146#define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos)
8147#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk
8148#define I2C_CR1_SMBDEN_Pos (21U)
8149#define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos)
8150#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk
8151#define I2C_CR1_ALERTEN_Pos (22U)
8152#define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos)
8153#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk
8154#define I2C_CR1_PECEN_Pos (23U)
8155#define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos)
8156#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk
8158/****************** Bit definition for I2C_CR2 register ********************/
8159#define I2C_CR2_SADD_Pos (0U)
8160#define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos)
8161#define I2C_CR2_SADD I2C_CR2_SADD_Msk
8162#define I2C_CR2_RD_WRN_Pos (10U)
8163#define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos)
8164#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk
8165#define I2C_CR2_ADD10_Pos (11U)
8166#define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos)
8167#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk
8168#define I2C_CR2_HEAD10R_Pos (12U)
8169#define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos)
8170#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk
8171#define I2C_CR2_START_Pos (13U)
8172#define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos)
8173#define I2C_CR2_START I2C_CR2_START_Msk
8174#define I2C_CR2_STOP_Pos (14U)
8175#define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos)
8176#define I2C_CR2_STOP I2C_CR2_STOP_Msk
8177#define I2C_CR2_NACK_Pos (15U)
8178#define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos)
8179#define I2C_CR2_NACK I2C_CR2_NACK_Msk
8180#define I2C_CR2_NBYTES_Pos (16U)
8181#define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos)
8182#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk
8183#define I2C_CR2_RELOAD_Pos (24U)
8184#define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos)
8185#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk
8186#define I2C_CR2_AUTOEND_Pos (25U)
8187#define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos)
8188#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk
8189#define I2C_CR2_PECBYTE_Pos (26U)
8190#define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos)
8191#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk
8193/******************* Bit definition for I2C_OAR1 register ******************/
8194#define I2C_OAR1_OA1_Pos (0U)
8195#define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos)
8196#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk
8197#define I2C_OAR1_OA1MODE_Pos (10U)
8198#define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos)
8199#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk
8200#define I2C_OAR1_OA1EN_Pos (15U)
8201#define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos)
8202#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk
8204/******************* Bit definition for I2C_OAR2 register ******************/
8205#define I2C_OAR2_OA2_Pos (1U)
8206#define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos)
8207#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk
8208#define I2C_OAR2_OA2MSK_Pos (8U)
8209#define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos)
8210#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk
8211#define I2C_OAR2_OA2NOMASK (0x00000000UL)
8212#define I2C_OAR2_OA2MASK01_Pos (8U)
8213#define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos)
8214#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk
8215#define I2C_OAR2_OA2MASK02_Pos (9U)
8216#define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos)
8217#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk
8218#define I2C_OAR2_OA2MASK03_Pos (8U)
8219#define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos)
8220#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk
8221#define I2C_OAR2_OA2MASK04_Pos (10U)
8222#define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos)
8223#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk
8224#define I2C_OAR2_OA2MASK05_Pos (8U)
8225#define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos)
8226#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk
8227#define I2C_OAR2_OA2MASK06_Pos (9U)
8228#define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos)
8229#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk
8230#define I2C_OAR2_OA2MASK07_Pos (8U)
8231#define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos)
8232#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk
8233#define I2C_OAR2_OA2EN_Pos (15U)
8234#define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos)
8235#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk
8237/******************* Bit definition for I2C_TIMINGR register *******************/
8238#define I2C_TIMINGR_SCLL_Pos (0U)
8239#define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos)
8240#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk
8241#define I2C_TIMINGR_SCLH_Pos (8U)
8242#define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos)
8243#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk
8244#define I2C_TIMINGR_SDADEL_Pos (16U)
8245#define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos)
8246#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk
8247#define I2C_TIMINGR_SCLDEL_Pos (20U)
8248#define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos)
8249#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk
8250#define I2C_TIMINGR_PRESC_Pos (28U)
8251#define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos)
8252#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk
8254/******************* Bit definition for I2C_TIMEOUTR register *******************/
8255#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
8256#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)
8257#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk
8258#define I2C_TIMEOUTR_TIDLE_Pos (12U)
8259#define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)
8260#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk
8261#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
8262#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)
8263#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk
8264#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
8265#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)
8266#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk
8267#define I2C_TIMEOUTR_TEXTEN_Pos (31U)
8268#define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)
8269#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk
8271/****************** Bit definition for I2C_ISR register *********************/
8272#define I2C_ISR_TXE_Pos (0U)
8273#define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos)
8274#define I2C_ISR_TXE I2C_ISR_TXE_Msk
8275#define I2C_ISR_TXIS_Pos (1U)
8276#define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos)
8277#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk
8278#define I2C_ISR_RXNE_Pos (2U)
8279#define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos)
8280#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk
8281#define I2C_ISR_ADDR_Pos (3U)
8282#define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos)
8283#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk
8284#define I2C_ISR_NACKF_Pos (4U)
8285#define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos)
8286#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk
8287#define I2C_ISR_STOPF_Pos (5U)
8288#define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos)
8289#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk
8290#define I2C_ISR_TC_Pos (6U)
8291#define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos)
8292#define I2C_ISR_TC I2C_ISR_TC_Msk
8293#define I2C_ISR_TCR_Pos (7U)
8294#define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos)
8295#define I2C_ISR_TCR I2C_ISR_TCR_Msk
8296#define I2C_ISR_BERR_Pos (8U)
8297#define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos)
8298#define I2C_ISR_BERR I2C_ISR_BERR_Msk
8299#define I2C_ISR_ARLO_Pos (9U)
8300#define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos)
8301#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk
8302#define I2C_ISR_OVR_Pos (10U)
8303#define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos)
8304#define I2C_ISR_OVR I2C_ISR_OVR_Msk
8305#define I2C_ISR_PECERR_Pos (11U)
8306#define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos)
8307#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk
8308#define I2C_ISR_TIMEOUT_Pos (12U)
8309#define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos)
8310#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk
8311#define I2C_ISR_ALERT_Pos (13U)
8312#define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos)
8313#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk
8314#define I2C_ISR_BUSY_Pos (15U)
8315#define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos)
8316#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk
8317#define I2C_ISR_DIR_Pos (16U)
8318#define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos)
8319#define I2C_ISR_DIR I2C_ISR_DIR_Msk
8320#define I2C_ISR_ADDCODE_Pos (17U)
8321#define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos)
8322#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk
8324/****************** Bit definition for I2C_ICR register *********************/
8325#define I2C_ICR_ADDRCF_Pos (3U)
8326#define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos)
8327#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk
8328#define I2C_ICR_NACKCF_Pos (4U)
8329#define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos)
8330#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk
8331#define I2C_ICR_STOPCF_Pos (5U)
8332#define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos)
8333#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk
8334#define I2C_ICR_BERRCF_Pos (8U)
8335#define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos)
8336#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk
8337#define I2C_ICR_ARLOCF_Pos (9U)
8338#define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos)
8339#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk
8340#define I2C_ICR_OVRCF_Pos (10U)
8341#define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos)
8342#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk
8343#define I2C_ICR_PECCF_Pos (11U)
8344#define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos)
8345#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk
8346#define I2C_ICR_TIMOUTCF_Pos (12U)
8347#define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos)
8348#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk
8349#define I2C_ICR_ALERTCF_Pos (13U)
8350#define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos)
8351#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk
8353/****************** Bit definition for I2C_PECR register *********************/
8354#define I2C_PECR_PEC_Pos (0U)
8355#define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos)
8356#define I2C_PECR_PEC I2C_PECR_PEC_Msk
8358/****************** Bit definition for I2C_RXDR register *********************/
8359#define I2C_RXDR_RXDATA_Pos (0U)
8360#define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos)
8361#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk
8363/****************** Bit definition for I2C_TXDR register *********************/
8364#define I2C_TXDR_TXDATA_Pos (0U)
8365#define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos)
8366#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk
8368/******************************************************************************/
8369/* */
8370/* Independent WATCHDOG */
8371/* */
8372/******************************************************************************/
8373/******************* Bit definition for IWDG_KR register ********************/
8374#define IWDG_KR_KEY_Pos (0U)
8375#define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos)
8376#define IWDG_KR_KEY IWDG_KR_KEY_Msk
8378/******************* Bit definition for IWDG_PR register ********************/
8379#define IWDG_PR_PR_Pos (0U)
8380#define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos)
8381#define IWDG_PR_PR IWDG_PR_PR_Msk
8382#define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos)
8383#define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos)
8384#define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos)
8386/******************* Bit definition for IWDG_RLR register *******************/
8387#define IWDG_RLR_RL_Pos (0U)
8388#define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos)
8389#define IWDG_RLR_RL IWDG_RLR_RL_Msk
8391/******************* Bit definition for IWDG_SR register ********************/
8392#define IWDG_SR_PVU_Pos (0U)
8393#define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos)
8394#define IWDG_SR_PVU IWDG_SR_PVU_Msk
8395#define IWDG_SR_RVU_Pos (1U)
8396#define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos)
8397#define IWDG_SR_RVU IWDG_SR_RVU_Msk
8398#define IWDG_SR_WVU_Pos (2U)
8399#define IWDG_SR_WVU_Msk (0x1UL << IWDG_SR_WVU_Pos)
8400#define IWDG_SR_WVU IWDG_SR_WVU_Msk
8402/******************* Bit definition for IWDG_KR register ********************/
8403#define IWDG_WINR_WIN_Pos (0U)
8404#define IWDG_WINR_WIN_Msk (0xFFFUL << IWDG_WINR_WIN_Pos)
8405#define IWDG_WINR_WIN IWDG_WINR_WIN_Msk
8407/******************************************************************************/
8408/* */
8409/* Firewall */
8410/* */
8411/******************************************************************************/
8412
8413/*******Bit definition for CSSA;CSL;NVDSSA;NVDSL;VDSSA;VDSL register */
8414#define FW_CSSA_ADD_Pos (8U)
8415#define FW_CSSA_ADD_Msk (0xFFFFUL << FW_CSSA_ADD_Pos)
8416#define FW_CSSA_ADD FW_CSSA_ADD_Msk
8417#define FW_CSL_LENG_Pos (8U)
8418#define FW_CSL_LENG_Msk (0x3FFFUL << FW_CSL_LENG_Pos)
8419#define FW_CSL_LENG FW_CSL_LENG_Msk
8420#define FW_NVDSSA_ADD_Pos (8U)
8421#define FW_NVDSSA_ADD_Msk (0xFFFFUL << FW_NVDSSA_ADD_Pos)
8422#define FW_NVDSSA_ADD FW_NVDSSA_ADD_Msk
8423#define FW_NVDSL_LENG_Pos (8U)
8424#define FW_NVDSL_LENG_Msk (0x3FFFUL << FW_NVDSL_LENG_Pos)
8425#define FW_NVDSL_LENG FW_NVDSL_LENG_Msk
8426#define FW_VDSSA_ADD_Pos (6U)
8427#define FW_VDSSA_ADD_Msk (0x7FFUL << FW_VDSSA_ADD_Pos)
8428#define FW_VDSSA_ADD FW_VDSSA_ADD_Msk
8429#define FW_VDSL_LENG_Pos (6U)
8430#define FW_VDSL_LENG_Msk (0x7FFUL << FW_VDSL_LENG_Pos)
8431#define FW_VDSL_LENG FW_VDSL_LENG_Msk
8433/**************************Bit definition for CR register *********************/
8434#define FW_CR_FPA_Pos (0U)
8435#define FW_CR_FPA_Msk (0x1UL << FW_CR_FPA_Pos)
8436#define FW_CR_FPA FW_CR_FPA_Msk
8437#define FW_CR_VDS_Pos (1U)
8438#define FW_CR_VDS_Msk (0x1UL << FW_CR_VDS_Pos)
8439#define FW_CR_VDS FW_CR_VDS_Msk
8440#define FW_CR_VDE_Pos (2U)
8441#define FW_CR_VDE_Msk (0x1UL << FW_CR_VDE_Pos)
8442#define FW_CR_VDE FW_CR_VDE_Msk
8444/******************************************************************************/
8445/* */
8446/* Power Control */
8447/* */
8448/******************************************************************************/
8449
8450/******************** Bit definition for PWR_CR1 register ********************/
8451
8452#define PWR_CR1_LPR_Pos (14U)
8453#define PWR_CR1_LPR_Msk (0x1UL << PWR_CR1_LPR_Pos)
8454#define PWR_CR1_LPR PWR_CR1_LPR_Msk
8455#define PWR_CR1_VOS_Pos (9U)
8456#define PWR_CR1_VOS_Msk (0x3UL << PWR_CR1_VOS_Pos)
8457#define PWR_CR1_VOS PWR_CR1_VOS_Msk
8458#define PWR_CR1_VOS_0 (0x1UL << PWR_CR1_VOS_Pos)
8459#define PWR_CR1_VOS_1 (0x2UL << PWR_CR1_VOS_Pos)
8460#define PWR_CR1_DBP_Pos (8U)
8461#define PWR_CR1_DBP_Msk (0x1UL << PWR_CR1_DBP_Pos)
8462#define PWR_CR1_DBP PWR_CR1_DBP_Msk
8463#define PWR_CR1_LPMS_Pos (0U)
8464#define PWR_CR1_LPMS_Msk (0x7UL << PWR_CR1_LPMS_Pos)
8465#define PWR_CR1_LPMS PWR_CR1_LPMS_Msk
8466#define PWR_CR1_LPMS_STOP0 (0x00000000UL)
8467#define PWR_CR1_LPMS_STOP1_Pos (0U)
8468#define PWR_CR1_LPMS_STOP1_Msk (0x1UL << PWR_CR1_LPMS_STOP1_Pos)
8469#define PWR_CR1_LPMS_STOP1 PWR_CR1_LPMS_STOP1_Msk
8470#define PWR_CR1_LPMS_STOP2_Pos (1U)
8471#define PWR_CR1_LPMS_STOP2_Msk (0x1UL << PWR_CR1_LPMS_STOP2_Pos)
8472#define PWR_CR1_LPMS_STOP2 PWR_CR1_LPMS_STOP2_Msk
8473#define PWR_CR1_LPMS_STANDBY_Pos (0U)
8474#define PWR_CR1_LPMS_STANDBY_Msk (0x3UL << PWR_CR1_LPMS_STANDBY_Pos)
8475#define PWR_CR1_LPMS_STANDBY PWR_CR1_LPMS_STANDBY_Msk
8476#define PWR_CR1_LPMS_SHUTDOWN_Pos (2U)
8477#define PWR_CR1_LPMS_SHUTDOWN_Msk (0x1UL << PWR_CR1_LPMS_SHUTDOWN_Pos)
8478#define PWR_CR1_LPMS_SHUTDOWN PWR_CR1_LPMS_SHUTDOWN_Msk
8481/******************** Bit definition for PWR_CR2 register ********************/
8483#define PWR_CR2_PVME_Pos (6U)
8484#define PWR_CR2_PVME_Msk (0x3UL << PWR_CR2_PVME_Pos)
8485#define PWR_CR2_PVME PWR_CR2_PVME_Msk
8486#define PWR_CR2_PVME4_Pos (7U)
8487#define PWR_CR2_PVME4_Msk (0x1UL << PWR_CR2_PVME4_Pos)
8488#define PWR_CR2_PVME4 PWR_CR2_PVME4_Msk
8489#define PWR_CR2_PVME3_Pos (6U)
8490#define PWR_CR2_PVME3_Msk (0x1UL << PWR_CR2_PVME3_Pos)
8491#define PWR_CR2_PVME3 PWR_CR2_PVME3_Msk
8493#define PWR_CR2_PLS_Pos (1U)
8494#define PWR_CR2_PLS_Msk (0x7UL << PWR_CR2_PLS_Pos)
8495#define PWR_CR2_PLS PWR_CR2_PLS_Msk
8496#define PWR_CR2_PLS_LEV0 (0x00000000UL)
8497#define PWR_CR2_PLS_LEV1_Pos (1U)
8498#define PWR_CR2_PLS_LEV1_Msk (0x1UL << PWR_CR2_PLS_LEV1_Pos)
8499#define PWR_CR2_PLS_LEV1 PWR_CR2_PLS_LEV1_Msk
8500#define PWR_CR2_PLS_LEV2_Pos (2U)
8501#define PWR_CR2_PLS_LEV2_Msk (0x1UL << PWR_CR2_PLS_LEV2_Pos)
8502#define PWR_CR2_PLS_LEV2 PWR_CR2_PLS_LEV2_Msk
8503#define PWR_CR2_PLS_LEV3_Pos (1U)
8504#define PWR_CR2_PLS_LEV3_Msk (0x3UL << PWR_CR2_PLS_LEV3_Pos)
8505#define PWR_CR2_PLS_LEV3 PWR_CR2_PLS_LEV3_Msk
8506#define PWR_CR2_PLS_LEV4_Pos (3U)
8507#define PWR_CR2_PLS_LEV4_Msk (0x1UL << PWR_CR2_PLS_LEV4_Pos)
8508#define PWR_CR2_PLS_LEV4 PWR_CR2_PLS_LEV4_Msk
8509#define PWR_CR2_PLS_LEV5_Pos (1U)
8510#define PWR_CR2_PLS_LEV5_Msk (0x5UL << PWR_CR2_PLS_LEV5_Pos)
8511#define PWR_CR2_PLS_LEV5 PWR_CR2_PLS_LEV5_Msk
8512#define PWR_CR2_PLS_LEV6_Pos (2U)
8513#define PWR_CR2_PLS_LEV6_Msk (0x3UL << PWR_CR2_PLS_LEV6_Pos)
8514#define PWR_CR2_PLS_LEV6 PWR_CR2_PLS_LEV6_Msk
8515#define PWR_CR2_PLS_LEV7_Pos (1U)
8516#define PWR_CR2_PLS_LEV7_Msk (0x7UL << PWR_CR2_PLS_LEV7_Pos)
8517#define PWR_CR2_PLS_LEV7 PWR_CR2_PLS_LEV7_Msk
8518#define PWR_CR2_PVDE_Pos (0U)
8519#define PWR_CR2_PVDE_Msk (0x1UL << PWR_CR2_PVDE_Pos)
8520#define PWR_CR2_PVDE PWR_CR2_PVDE_Msk
8522/******************** Bit definition for PWR_CR3 register ********************/
8523#define PWR_CR3_EIWUL_Pos (15U)
8524#define PWR_CR3_EIWUL_Msk (0x1UL << PWR_CR3_EIWUL_Pos)
8525#define PWR_CR3_EIWUL PWR_CR3_EIWUL_Msk
8526#define PWR_CR3_APC_Pos (10U)
8527#define PWR_CR3_APC_Msk (0x1UL << PWR_CR3_APC_Pos)
8528#define PWR_CR3_APC PWR_CR3_APC_Msk
8529#define PWR_CR3_RRS_Pos (8U)
8530#define PWR_CR3_RRS_Msk (0x1UL << PWR_CR3_RRS_Pos)
8531#define PWR_CR3_RRS PWR_CR3_RRS_Msk
8532#define PWR_CR3_EWUP5_Pos (4U)
8533#define PWR_CR3_EWUP5_Msk (0x1UL << PWR_CR3_EWUP5_Pos)
8534#define PWR_CR3_EWUP5 PWR_CR3_EWUP5_Msk
8535#define PWR_CR3_EWUP4_Pos (3U)
8536#define PWR_CR3_EWUP4_Msk (0x1UL << PWR_CR3_EWUP4_Pos)
8537#define PWR_CR3_EWUP4 PWR_CR3_EWUP4_Msk
8538#define PWR_CR3_EWUP3_Pos (2U)
8539#define PWR_CR3_EWUP3_Msk (0x1UL << PWR_CR3_EWUP3_Pos)
8540#define PWR_CR3_EWUP3 PWR_CR3_EWUP3_Msk
8541#define PWR_CR3_EWUP2_Pos (1U)
8542#define PWR_CR3_EWUP2_Msk (0x1UL << PWR_CR3_EWUP2_Pos)
8543#define PWR_CR3_EWUP2 PWR_CR3_EWUP2_Msk
8544#define PWR_CR3_EWUP1_Pos (0U)
8545#define PWR_CR3_EWUP1_Msk (0x1UL << PWR_CR3_EWUP1_Pos)
8546#define PWR_CR3_EWUP1 PWR_CR3_EWUP1_Msk
8547#define PWR_CR3_EWUP_Pos (0U)
8548#define PWR_CR3_EWUP_Msk (0x1FUL << PWR_CR3_EWUP_Pos)
8549#define PWR_CR3_EWUP PWR_CR3_EWUP_Msk
8551/* Legacy defines */
8552#define PWR_CR3_EIWF_Pos PWR_CR3_EIWUL_Pos
8553#define PWR_CR3_EIWF_Msk PWR_CR3_EIWUL_Msk
8554#define PWR_CR3_EIWF PWR_CR3_EIWUL
8555
8556
8557/******************** Bit definition for PWR_CR4 register ********************/
8558#define PWR_CR4_VBRS_Pos (9U)
8559#define PWR_CR4_VBRS_Msk (0x1UL << PWR_CR4_VBRS_Pos)
8560#define PWR_CR4_VBRS PWR_CR4_VBRS_Msk
8561#define PWR_CR4_VBE_Pos (8U)
8562#define PWR_CR4_VBE_Msk (0x1UL << PWR_CR4_VBE_Pos)
8563#define PWR_CR4_VBE PWR_CR4_VBE_Msk
8564#define PWR_CR4_WP5_Pos (4U)
8565#define PWR_CR4_WP5_Msk (0x1UL << PWR_CR4_WP5_Pos)
8566#define PWR_CR4_WP5 PWR_CR4_WP5_Msk
8567#define PWR_CR4_WP4_Pos (3U)
8568#define PWR_CR4_WP4_Msk (0x1UL << PWR_CR4_WP4_Pos)
8569#define PWR_CR4_WP4 PWR_CR4_WP4_Msk
8570#define PWR_CR4_WP3_Pos (2U)
8571#define PWR_CR4_WP3_Msk (0x1UL << PWR_CR4_WP3_Pos)
8572#define PWR_CR4_WP3 PWR_CR4_WP3_Msk
8573#define PWR_CR4_WP2_Pos (1U)
8574#define PWR_CR4_WP2_Msk (0x1UL << PWR_CR4_WP2_Pos)
8575#define PWR_CR4_WP2 PWR_CR4_WP2_Msk
8576#define PWR_CR4_WP1_Pos (0U)
8577#define PWR_CR4_WP1_Msk (0x1UL << PWR_CR4_WP1_Pos)
8578#define PWR_CR4_WP1 PWR_CR4_WP1_Msk
8580/******************** Bit definition for PWR_SR1 register ********************/
8581#define PWR_SR1_WUFI_Pos (15U)
8582#define PWR_SR1_WUFI_Msk (0x1UL << PWR_SR1_WUFI_Pos)
8583#define PWR_SR1_WUFI PWR_SR1_WUFI_Msk
8584#define PWR_SR1_SBF_Pos (8U)
8585#define PWR_SR1_SBF_Msk (0x1UL << PWR_SR1_SBF_Pos)
8586#define PWR_SR1_SBF PWR_SR1_SBF_Msk
8587#define PWR_SR1_WUF_Pos (0U)
8588#define PWR_SR1_WUF_Msk (0x1FUL << PWR_SR1_WUF_Pos)
8589#define PWR_SR1_WUF PWR_SR1_WUF_Msk
8590#define PWR_SR1_WUF5_Pos (4U)
8591#define PWR_SR1_WUF5_Msk (0x1UL << PWR_SR1_WUF5_Pos)
8592#define PWR_SR1_WUF5 PWR_SR1_WUF5_Msk
8593#define PWR_SR1_WUF4_Pos (3U)
8594#define PWR_SR1_WUF4_Msk (0x1UL << PWR_SR1_WUF4_Pos)
8595#define PWR_SR1_WUF4 PWR_SR1_WUF4_Msk
8596#define PWR_SR1_WUF3_Pos (2U)
8597#define PWR_SR1_WUF3_Msk (0x1UL << PWR_SR1_WUF3_Pos)
8598#define PWR_SR1_WUF3 PWR_SR1_WUF3_Msk
8599#define PWR_SR1_WUF2_Pos (1U)
8600#define PWR_SR1_WUF2_Msk (0x1UL << PWR_SR1_WUF2_Pos)
8601#define PWR_SR1_WUF2 PWR_SR1_WUF2_Msk
8602#define PWR_SR1_WUF1_Pos (0U)
8603#define PWR_SR1_WUF1_Msk (0x1UL << PWR_SR1_WUF1_Pos)
8604#define PWR_SR1_WUF1 PWR_SR1_WUF1_Msk
8606/******************** Bit definition for PWR_SR2 register ********************/
8607#define PWR_SR2_PVMO4_Pos (15U)
8608#define PWR_SR2_PVMO4_Msk (0x1UL << PWR_SR2_PVMO4_Pos)
8609#define PWR_SR2_PVMO4 PWR_SR2_PVMO4_Msk
8610#define PWR_SR2_PVMO3_Pos (14U)
8611#define PWR_SR2_PVMO3_Msk (0x1UL << PWR_SR2_PVMO3_Pos)
8612#define PWR_SR2_PVMO3 PWR_SR2_PVMO3_Msk
8613#define PWR_SR2_PVDO_Pos (11U)
8614#define PWR_SR2_PVDO_Msk (0x1UL << PWR_SR2_PVDO_Pos)
8615#define PWR_SR2_PVDO PWR_SR2_PVDO_Msk
8616#define PWR_SR2_VOSF_Pos (10U)
8617#define PWR_SR2_VOSF_Msk (0x1UL << PWR_SR2_VOSF_Pos)
8618#define PWR_SR2_VOSF PWR_SR2_VOSF_Msk
8619#define PWR_SR2_REGLPF_Pos (9U)
8620#define PWR_SR2_REGLPF_Msk (0x1UL << PWR_SR2_REGLPF_Pos)
8621#define PWR_SR2_REGLPF PWR_SR2_REGLPF_Msk
8622#define PWR_SR2_REGLPS_Pos (8U)
8623#define PWR_SR2_REGLPS_Msk (0x1UL << PWR_SR2_REGLPS_Pos)
8624#define PWR_SR2_REGLPS PWR_SR2_REGLPS_Msk
8626/******************** Bit definition for PWR_SCR register ********************/
8627#define PWR_SCR_CSBF_Pos (8U)
8628#define PWR_SCR_CSBF_Msk (0x1UL << PWR_SCR_CSBF_Pos)
8629#define PWR_SCR_CSBF PWR_SCR_CSBF_Msk
8630#define PWR_SCR_CWUF_Pos (0U)
8631#define PWR_SCR_CWUF_Msk (0x1FUL << PWR_SCR_CWUF_Pos)
8632#define PWR_SCR_CWUF PWR_SCR_CWUF_Msk
8633#define PWR_SCR_CWUF5_Pos (4U)
8634#define PWR_SCR_CWUF5_Msk (0x1UL << PWR_SCR_CWUF5_Pos)
8635#define PWR_SCR_CWUF5 PWR_SCR_CWUF5_Msk
8636#define PWR_SCR_CWUF4_Pos (3U)
8637#define PWR_SCR_CWUF4_Msk (0x1UL << PWR_SCR_CWUF4_Pos)
8638#define PWR_SCR_CWUF4 PWR_SCR_CWUF4_Msk
8639#define PWR_SCR_CWUF3_Pos (2U)
8640#define PWR_SCR_CWUF3_Msk (0x1UL << PWR_SCR_CWUF3_Pos)
8641#define PWR_SCR_CWUF3 PWR_SCR_CWUF3_Msk
8642#define PWR_SCR_CWUF2_Pos (1U)
8643#define PWR_SCR_CWUF2_Msk (0x1UL << PWR_SCR_CWUF2_Pos)
8644#define PWR_SCR_CWUF2 PWR_SCR_CWUF2_Msk
8645#define PWR_SCR_CWUF1_Pos (0U)
8646#define PWR_SCR_CWUF1_Msk (0x1UL << PWR_SCR_CWUF1_Pos)
8647#define PWR_SCR_CWUF1 PWR_SCR_CWUF1_Msk
8649/******************** Bit definition for PWR_PUCRA register ********************/
8650#define PWR_PUCRA_PA15_Pos (15U)
8651#define PWR_PUCRA_PA15_Msk (0x1UL << PWR_PUCRA_PA15_Pos)
8652#define PWR_PUCRA_PA15 PWR_PUCRA_PA15_Msk
8653#define PWR_PUCRA_PA13_Pos (13U)
8654#define PWR_PUCRA_PA13_Msk (0x1UL << PWR_PUCRA_PA13_Pos)
8655#define PWR_PUCRA_PA13 PWR_PUCRA_PA13_Msk
8656#define PWR_PUCRA_PA12_Pos (12U)
8657#define PWR_PUCRA_PA12_Msk (0x1UL << PWR_PUCRA_PA12_Pos)
8658#define PWR_PUCRA_PA12 PWR_PUCRA_PA12_Msk
8659#define PWR_PUCRA_PA11_Pos (11U)
8660#define PWR_PUCRA_PA11_Msk (0x1UL << PWR_PUCRA_PA11_Pos)
8661#define PWR_PUCRA_PA11 PWR_PUCRA_PA11_Msk
8662#define PWR_PUCRA_PA10_Pos (10U)
8663#define PWR_PUCRA_PA10_Msk (0x1UL << PWR_PUCRA_PA10_Pos)
8664#define PWR_PUCRA_PA10 PWR_PUCRA_PA10_Msk
8665#define PWR_PUCRA_PA9_Pos (9U)
8666#define PWR_PUCRA_PA9_Msk (0x1UL << PWR_PUCRA_PA9_Pos)
8667#define PWR_PUCRA_PA9 PWR_PUCRA_PA9_Msk
8668#define PWR_PUCRA_PA8_Pos (8U)
8669#define PWR_PUCRA_PA8_Msk (0x1UL << PWR_PUCRA_PA8_Pos)
8670#define PWR_PUCRA_PA8 PWR_PUCRA_PA8_Msk
8671#define PWR_PUCRA_PA7_Pos (7U)
8672#define PWR_PUCRA_PA7_Msk (0x1UL << PWR_PUCRA_PA7_Pos)
8673#define PWR_PUCRA_PA7 PWR_PUCRA_PA7_Msk
8674#define PWR_PUCRA_PA6_Pos (6U)
8675#define PWR_PUCRA_PA6_Msk (0x1UL << PWR_PUCRA_PA6_Pos)
8676#define PWR_PUCRA_PA6 PWR_PUCRA_PA6_Msk
8677#define PWR_PUCRA_PA5_Pos (5U)
8678#define PWR_PUCRA_PA5_Msk (0x1UL << PWR_PUCRA_PA5_Pos)
8679#define PWR_PUCRA_PA5 PWR_PUCRA_PA5_Msk
8680#define PWR_PUCRA_PA4_Pos (4U)
8681#define PWR_PUCRA_PA4_Msk (0x1UL << PWR_PUCRA_PA4_Pos)
8682#define PWR_PUCRA_PA4 PWR_PUCRA_PA4_Msk
8683#define PWR_PUCRA_PA3_Pos (3U)
8684#define PWR_PUCRA_PA3_Msk (0x1UL << PWR_PUCRA_PA3_Pos)
8685#define PWR_PUCRA_PA3 PWR_PUCRA_PA3_Msk
8686#define PWR_PUCRA_PA2_Pos (2U)
8687#define PWR_PUCRA_PA2_Msk (0x1UL << PWR_PUCRA_PA2_Pos)
8688#define PWR_PUCRA_PA2 PWR_PUCRA_PA2_Msk
8689#define PWR_PUCRA_PA1_Pos (1U)
8690#define PWR_PUCRA_PA1_Msk (0x1UL << PWR_PUCRA_PA1_Pos)
8691#define PWR_PUCRA_PA1 PWR_PUCRA_PA1_Msk
8692#define PWR_PUCRA_PA0_Pos (0U)
8693#define PWR_PUCRA_PA0_Msk (0x1UL << PWR_PUCRA_PA0_Pos)
8694#define PWR_PUCRA_PA0 PWR_PUCRA_PA0_Msk
8696/******************** Bit definition for PWR_PDCRA register ********************/
8697#define PWR_PDCRA_PA14_Pos (14U)
8698#define PWR_PDCRA_PA14_Msk (0x1UL << PWR_PDCRA_PA14_Pos)
8699#define PWR_PDCRA_PA14 PWR_PDCRA_PA14_Msk
8700#define PWR_PDCRA_PA12_Pos (12U)
8701#define PWR_PDCRA_PA12_Msk (0x1UL << PWR_PDCRA_PA12_Pos)
8702#define PWR_PDCRA_PA12 PWR_PDCRA_PA12_Msk
8703#define PWR_PDCRA_PA11_Pos (11U)
8704#define PWR_PDCRA_PA11_Msk (0x1UL << PWR_PDCRA_PA11_Pos)
8705#define PWR_PDCRA_PA11 PWR_PDCRA_PA11_Msk
8706#define PWR_PDCRA_PA10_Pos (10U)
8707#define PWR_PDCRA_PA10_Msk (0x1UL << PWR_PDCRA_PA10_Pos)
8708#define PWR_PDCRA_PA10 PWR_PDCRA_PA10_Msk
8709#define PWR_PDCRA_PA9_Pos (9U)
8710#define PWR_PDCRA_PA9_Msk (0x1UL << PWR_PDCRA_PA9_Pos)
8711#define PWR_PDCRA_PA9 PWR_PDCRA_PA9_Msk
8712#define PWR_PDCRA_PA8_Pos (8U)
8713#define PWR_PDCRA_PA8_Msk (0x1UL << PWR_PDCRA_PA8_Pos)
8714#define PWR_PDCRA_PA8 PWR_PDCRA_PA8_Msk
8715#define PWR_PDCRA_PA7_Pos (7U)
8716#define PWR_PDCRA_PA7_Msk (0x1UL << PWR_PDCRA_PA7_Pos)
8717#define PWR_PDCRA_PA7 PWR_PDCRA_PA7_Msk
8718#define PWR_PDCRA_PA6_Pos (6U)
8719#define PWR_PDCRA_PA6_Msk (0x1UL << PWR_PDCRA_PA6_Pos)
8720#define PWR_PDCRA_PA6 PWR_PDCRA_PA6_Msk
8721#define PWR_PDCRA_PA5_Pos (5U)
8722#define PWR_PDCRA_PA5_Msk (0x1UL << PWR_PDCRA_PA5_Pos)
8723#define PWR_PDCRA_PA5 PWR_PDCRA_PA5_Msk
8724#define PWR_PDCRA_PA4_Pos (4U)
8725#define PWR_PDCRA_PA4_Msk (0x1UL << PWR_PDCRA_PA4_Pos)
8726#define PWR_PDCRA_PA4 PWR_PDCRA_PA4_Msk
8727#define PWR_PDCRA_PA3_Pos (3U)
8728#define PWR_PDCRA_PA3_Msk (0x1UL << PWR_PDCRA_PA3_Pos)
8729#define PWR_PDCRA_PA3 PWR_PDCRA_PA3_Msk
8730#define PWR_PDCRA_PA2_Pos (2U)
8731#define PWR_PDCRA_PA2_Msk (0x1UL << PWR_PDCRA_PA2_Pos)
8732#define PWR_PDCRA_PA2 PWR_PDCRA_PA2_Msk
8733#define PWR_PDCRA_PA1_Pos (1U)
8734#define PWR_PDCRA_PA1_Msk (0x1UL << PWR_PDCRA_PA1_Pos)
8735#define PWR_PDCRA_PA1 PWR_PDCRA_PA1_Msk
8736#define PWR_PDCRA_PA0_Pos (0U)
8737#define PWR_PDCRA_PA0_Msk (0x1UL << PWR_PDCRA_PA0_Pos)
8738#define PWR_PDCRA_PA0 PWR_PDCRA_PA0_Msk
8740/******************** Bit definition for PWR_PUCRB register ********************/
8741#define PWR_PUCRB_PB15_Pos (15U)
8742#define PWR_PUCRB_PB15_Msk (0x1UL << PWR_PUCRB_PB15_Pos)
8743#define PWR_PUCRB_PB15 PWR_PUCRB_PB15_Msk
8744#define PWR_PUCRB_PB14_Pos (14U)
8745#define PWR_PUCRB_PB14_Msk (0x1UL << PWR_PUCRB_PB14_Pos)
8746#define PWR_PUCRB_PB14 PWR_PUCRB_PB14_Msk
8747#define PWR_PUCRB_PB13_Pos (13U)
8748#define PWR_PUCRB_PB13_Msk (0x1UL << PWR_PUCRB_PB13_Pos)
8749#define PWR_PUCRB_PB13 PWR_PUCRB_PB13_Msk
8750#define PWR_PUCRB_PB12_Pos (12U)
8751#define PWR_PUCRB_PB12_Msk (0x1UL << PWR_PUCRB_PB12_Pos)
8752#define PWR_PUCRB_PB12 PWR_PUCRB_PB12_Msk
8753#define PWR_PUCRB_PB11_Pos (11U)
8754#define PWR_PUCRB_PB11_Msk (0x1UL << PWR_PUCRB_PB11_Pos)
8755#define PWR_PUCRB_PB11 PWR_PUCRB_PB11_Msk
8756#define PWR_PUCRB_PB10_Pos (10U)
8757#define PWR_PUCRB_PB10_Msk (0x1UL << PWR_PUCRB_PB10_Pos)
8758#define PWR_PUCRB_PB10 PWR_PUCRB_PB10_Msk
8759#define PWR_PUCRB_PB9_Pos (9U)
8760#define PWR_PUCRB_PB9_Msk (0x1UL << PWR_PUCRB_PB9_Pos)
8761#define PWR_PUCRB_PB9 PWR_PUCRB_PB9_Msk
8762#define PWR_PUCRB_PB8_Pos (8U)
8763#define PWR_PUCRB_PB8_Msk (0x1UL << PWR_PUCRB_PB8_Pos)
8764#define PWR_PUCRB_PB8 PWR_PUCRB_PB8_Msk
8765#define PWR_PUCRB_PB7_Pos (7U)
8766#define PWR_PUCRB_PB7_Msk (0x1UL << PWR_PUCRB_PB7_Pos)
8767#define PWR_PUCRB_PB7 PWR_PUCRB_PB7_Msk
8768#define PWR_PUCRB_PB6_Pos (6U)
8769#define PWR_PUCRB_PB6_Msk (0x1UL << PWR_PUCRB_PB6_Pos)
8770#define PWR_PUCRB_PB6 PWR_PUCRB_PB6_Msk
8771#define PWR_PUCRB_PB5_Pos (5U)
8772#define PWR_PUCRB_PB5_Msk (0x1UL << PWR_PUCRB_PB5_Pos)
8773#define PWR_PUCRB_PB5 PWR_PUCRB_PB5_Msk
8774#define PWR_PUCRB_PB4_Pos (4U)
8775#define PWR_PUCRB_PB4_Msk (0x1UL << PWR_PUCRB_PB4_Pos)
8776#define PWR_PUCRB_PB4 PWR_PUCRB_PB4_Msk
8777#define PWR_PUCRB_PB3_Pos (3U)
8778#define PWR_PUCRB_PB3_Msk (0x1UL << PWR_PUCRB_PB3_Pos)
8779#define PWR_PUCRB_PB3 PWR_PUCRB_PB3_Msk
8780#define PWR_PUCRB_PB2_Pos (2U)
8781#define PWR_PUCRB_PB2_Msk (0x1UL << PWR_PUCRB_PB2_Pos)
8782#define PWR_PUCRB_PB2 PWR_PUCRB_PB2_Msk
8783#define PWR_PUCRB_PB1_Pos (1U)
8784#define PWR_PUCRB_PB1_Msk (0x1UL << PWR_PUCRB_PB1_Pos)
8785#define PWR_PUCRB_PB1 PWR_PUCRB_PB1_Msk
8786#define PWR_PUCRB_PB0_Pos (0U)
8787#define PWR_PUCRB_PB0_Msk (0x1UL << PWR_PUCRB_PB0_Pos)
8788#define PWR_PUCRB_PB0 PWR_PUCRB_PB0_Msk
8790/******************** Bit definition for PWR_PDCRB register ********************/
8791#define PWR_PDCRB_PB15_Pos (15U)
8792#define PWR_PDCRB_PB15_Msk (0x1UL << PWR_PDCRB_PB15_Pos)
8793#define PWR_PDCRB_PB15 PWR_PDCRB_PB15_Msk
8794#define PWR_PDCRB_PB14_Pos (14U)
8795#define PWR_PDCRB_PB14_Msk (0x1UL << PWR_PDCRB_PB14_Pos)
8796#define PWR_PDCRB_PB14 PWR_PDCRB_PB14_Msk
8797#define PWR_PDCRB_PB13_Pos (13U)
8798#define PWR_PDCRB_PB13_Msk (0x1UL << PWR_PDCRB_PB13_Pos)
8799#define PWR_PDCRB_PB13 PWR_PDCRB_PB13_Msk
8800#define PWR_PDCRB_PB12_Pos (12U)
8801#define PWR_PDCRB_PB12_Msk (0x1UL << PWR_PDCRB_PB12_Pos)
8802#define PWR_PDCRB_PB12 PWR_PDCRB_PB12_Msk
8803#define PWR_PDCRB_PB11_Pos (11U)
8804#define PWR_PDCRB_PB11_Msk (0x1UL << PWR_PDCRB_PB11_Pos)
8805#define PWR_PDCRB_PB11 PWR_PDCRB_PB11_Msk
8806#define PWR_PDCRB_PB10_Pos (10U)
8807#define PWR_PDCRB_PB10_Msk (0x1UL << PWR_PDCRB_PB10_Pos)
8808#define PWR_PDCRB_PB10 PWR_PDCRB_PB10_Msk
8809#define PWR_PDCRB_PB9_Pos (9U)
8810#define PWR_PDCRB_PB9_Msk (0x1UL << PWR_PDCRB_PB9_Pos)
8811#define PWR_PDCRB_PB9 PWR_PDCRB_PB9_Msk
8812#define PWR_PDCRB_PB8_Pos (8U)
8813#define PWR_PDCRB_PB8_Msk (0x1UL << PWR_PDCRB_PB8_Pos)
8814#define PWR_PDCRB_PB8 PWR_PDCRB_PB8_Msk
8815#define PWR_PDCRB_PB7_Pos (7U)
8816#define PWR_PDCRB_PB7_Msk (0x1UL << PWR_PDCRB_PB7_Pos)
8817#define PWR_PDCRB_PB7 PWR_PDCRB_PB7_Msk
8818#define PWR_PDCRB_PB6_Pos (6U)
8819#define PWR_PDCRB_PB6_Msk (0x1UL << PWR_PDCRB_PB6_Pos)
8820#define PWR_PDCRB_PB6 PWR_PDCRB_PB6_Msk
8821#define PWR_PDCRB_PB5_Pos (5U)
8822#define PWR_PDCRB_PB5_Msk (0x1UL << PWR_PDCRB_PB5_Pos)
8823#define PWR_PDCRB_PB5 PWR_PDCRB_PB5_Msk
8824#define PWR_PDCRB_PB3_Pos (3U)
8825#define PWR_PDCRB_PB3_Msk (0x1UL << PWR_PDCRB_PB3_Pos)
8826#define PWR_PDCRB_PB3 PWR_PDCRB_PB3_Msk
8827#define PWR_PDCRB_PB2_Pos (2U)
8828#define PWR_PDCRB_PB2_Msk (0x1UL << PWR_PDCRB_PB2_Pos)
8829#define PWR_PDCRB_PB2 PWR_PDCRB_PB2_Msk
8830#define PWR_PDCRB_PB1_Pos (1U)
8831#define PWR_PDCRB_PB1_Msk (0x1UL << PWR_PDCRB_PB1_Pos)
8832#define PWR_PDCRB_PB1 PWR_PDCRB_PB1_Msk
8833#define PWR_PDCRB_PB0_Pos (0U)
8834#define PWR_PDCRB_PB0_Msk (0x1UL << PWR_PDCRB_PB0_Pos)
8835#define PWR_PDCRB_PB0 PWR_PDCRB_PB0_Msk
8837/******************** Bit definition for PWR_PUCRC register ********************/
8838#define PWR_PUCRC_PC15_Pos (15U)
8839#define PWR_PUCRC_PC15_Msk (0x1UL << PWR_PUCRC_PC15_Pos)
8840#define PWR_PUCRC_PC15 PWR_PUCRC_PC15_Msk
8841#define PWR_PUCRC_PC14_Pos (14U)
8842#define PWR_PUCRC_PC14_Msk (0x1UL << PWR_PUCRC_PC14_Pos)
8843#define PWR_PUCRC_PC14 PWR_PUCRC_PC14_Msk
8844#define PWR_PUCRC_PC13_Pos (13U)
8845#define PWR_PUCRC_PC13_Msk (0x1UL << PWR_PUCRC_PC13_Pos)
8846#define PWR_PUCRC_PC13 PWR_PUCRC_PC13_Msk
8847#define PWR_PUCRC_PC12_Pos (12U)
8848#define PWR_PUCRC_PC12_Msk (0x1UL << PWR_PUCRC_PC12_Pos)
8849#define PWR_PUCRC_PC12 PWR_PUCRC_PC12_Msk
8850#define PWR_PUCRC_PC11_Pos (11U)
8851#define PWR_PUCRC_PC11_Msk (0x1UL << PWR_PUCRC_PC11_Pos)
8852#define PWR_PUCRC_PC11 PWR_PUCRC_PC11_Msk
8853#define PWR_PUCRC_PC10_Pos (10U)
8854#define PWR_PUCRC_PC10_Msk (0x1UL << PWR_PUCRC_PC10_Pos)
8855#define PWR_PUCRC_PC10 PWR_PUCRC_PC10_Msk
8856#define PWR_PUCRC_PC9_Pos (9U)
8857#define PWR_PUCRC_PC9_Msk (0x1UL << PWR_PUCRC_PC9_Pos)
8858#define PWR_PUCRC_PC9 PWR_PUCRC_PC9_Msk
8859#define PWR_PUCRC_PC8_Pos (8U)
8860#define PWR_PUCRC_PC8_Msk (0x1UL << PWR_PUCRC_PC8_Pos)
8861#define PWR_PUCRC_PC8 PWR_PUCRC_PC8_Msk
8862#define PWR_PUCRC_PC7_Pos (7U)
8863#define PWR_PUCRC_PC7_Msk (0x1UL << PWR_PUCRC_PC7_Pos)
8864#define PWR_PUCRC_PC7 PWR_PUCRC_PC7_Msk
8865#define PWR_PUCRC_PC6_Pos (6U)
8866#define PWR_PUCRC_PC6_Msk (0x1UL << PWR_PUCRC_PC6_Pos)
8867#define PWR_PUCRC_PC6 PWR_PUCRC_PC6_Msk
8868#define PWR_PUCRC_PC5_Pos (5U)
8869#define PWR_PUCRC_PC5_Msk (0x1UL << PWR_PUCRC_PC5_Pos)
8870#define PWR_PUCRC_PC5 PWR_PUCRC_PC5_Msk
8871#define PWR_PUCRC_PC4_Pos (4U)
8872#define PWR_PUCRC_PC4_Msk (0x1UL << PWR_PUCRC_PC4_Pos)
8873#define PWR_PUCRC_PC4 PWR_PUCRC_PC4_Msk
8874#define PWR_PUCRC_PC3_Pos (3U)
8875#define PWR_PUCRC_PC3_Msk (0x1UL << PWR_PUCRC_PC3_Pos)
8876#define PWR_PUCRC_PC3 PWR_PUCRC_PC3_Msk
8877#define PWR_PUCRC_PC2_Pos (2U)
8878#define PWR_PUCRC_PC2_Msk (0x1UL << PWR_PUCRC_PC2_Pos)
8879#define PWR_PUCRC_PC2 PWR_PUCRC_PC2_Msk
8880#define PWR_PUCRC_PC1_Pos (1U)
8881#define PWR_PUCRC_PC1_Msk (0x1UL << PWR_PUCRC_PC1_Pos)
8882#define PWR_PUCRC_PC1 PWR_PUCRC_PC1_Msk
8883#define PWR_PUCRC_PC0_Pos (0U)
8884#define PWR_PUCRC_PC0_Msk (0x1UL << PWR_PUCRC_PC0_Pos)
8885#define PWR_PUCRC_PC0 PWR_PUCRC_PC0_Msk
8887/******************** Bit definition for PWR_PDCRC register ********************/
8888#define PWR_PDCRC_PC15_Pos (15U)
8889#define PWR_PDCRC_PC15_Msk (0x1UL << PWR_PDCRC_PC15_Pos)
8890#define PWR_PDCRC_PC15 PWR_PDCRC_PC15_Msk
8891#define PWR_PDCRC_PC14_Pos (14U)
8892#define PWR_PDCRC_PC14_Msk (0x1UL << PWR_PDCRC_PC14_Pos)
8893#define PWR_PDCRC_PC14 PWR_PDCRC_PC14_Msk
8894#define PWR_PDCRC_PC13_Pos (13U)
8895#define PWR_PDCRC_PC13_Msk (0x1UL << PWR_PDCRC_PC13_Pos)
8896#define PWR_PDCRC_PC13 PWR_PDCRC_PC13_Msk
8897#define PWR_PDCRC_PC12_Pos (12U)
8898#define PWR_PDCRC_PC12_Msk (0x1UL << PWR_PDCRC_PC12_Pos)
8899#define PWR_PDCRC_PC12 PWR_PDCRC_PC12_Msk
8900#define PWR_PDCRC_PC11_Pos (11U)
8901#define PWR_PDCRC_PC11_Msk (0x1UL << PWR_PDCRC_PC11_Pos)
8902#define PWR_PDCRC_PC11 PWR_PDCRC_PC11_Msk
8903#define PWR_PDCRC_PC10_Pos (10U)
8904#define PWR_PDCRC_PC10_Msk (0x1UL << PWR_PDCRC_PC10_Pos)
8905#define PWR_PDCRC_PC10 PWR_PDCRC_PC10_Msk
8906#define PWR_PDCRC_PC9_Pos (9U)
8907#define PWR_PDCRC_PC9_Msk (0x1UL << PWR_PDCRC_PC9_Pos)
8908#define PWR_PDCRC_PC9 PWR_PDCRC_PC9_Msk
8909#define PWR_PDCRC_PC8_Pos (8U)
8910#define PWR_PDCRC_PC8_Msk (0x1UL << PWR_PDCRC_PC8_Pos)
8911#define PWR_PDCRC_PC8 PWR_PDCRC_PC8_Msk
8912#define PWR_PDCRC_PC7_Pos (7U)
8913#define PWR_PDCRC_PC7_Msk (0x1UL << PWR_PDCRC_PC7_Pos)
8914#define PWR_PDCRC_PC7 PWR_PDCRC_PC7_Msk
8915#define PWR_PDCRC_PC6_Pos (6U)
8916#define PWR_PDCRC_PC6_Msk (0x1UL << PWR_PDCRC_PC6_Pos)
8917#define PWR_PDCRC_PC6 PWR_PDCRC_PC6_Msk
8918#define PWR_PDCRC_PC5_Pos (5U)
8919#define PWR_PDCRC_PC5_Msk (0x1UL << PWR_PDCRC_PC5_Pos)
8920#define PWR_PDCRC_PC5 PWR_PDCRC_PC5_Msk
8921#define PWR_PDCRC_PC4_Pos (4U)
8922#define PWR_PDCRC_PC4_Msk (0x1UL << PWR_PDCRC_PC4_Pos)
8923#define PWR_PDCRC_PC4 PWR_PDCRC_PC4_Msk
8924#define PWR_PDCRC_PC3_Pos (3U)
8925#define PWR_PDCRC_PC3_Msk (0x1UL << PWR_PDCRC_PC3_Pos)
8926#define PWR_PDCRC_PC3 PWR_PDCRC_PC3_Msk
8927#define PWR_PDCRC_PC2_Pos (2U)
8928#define PWR_PDCRC_PC2_Msk (0x1UL << PWR_PDCRC_PC2_Pos)
8929#define PWR_PDCRC_PC2 PWR_PDCRC_PC2_Msk
8930#define PWR_PDCRC_PC1_Pos (1U)
8931#define PWR_PDCRC_PC1_Msk (0x1UL << PWR_PDCRC_PC1_Pos)
8932#define PWR_PDCRC_PC1 PWR_PDCRC_PC1_Msk
8933#define PWR_PDCRC_PC0_Pos (0U)
8934#define PWR_PDCRC_PC0_Msk (0x1UL << PWR_PDCRC_PC0_Pos)
8935#define PWR_PDCRC_PC0 PWR_PDCRC_PC0_Msk
8937/******************** Bit definition for PWR_PUCRD register ********************/
8938#define PWR_PUCRD_PD15_Pos (15U)
8939#define PWR_PUCRD_PD15_Msk (0x1UL << PWR_PUCRD_PD15_Pos)
8940#define PWR_PUCRD_PD15 PWR_PUCRD_PD15_Msk
8941#define PWR_PUCRD_PD14_Pos (14U)
8942#define PWR_PUCRD_PD14_Msk (0x1UL << PWR_PUCRD_PD14_Pos)
8943#define PWR_PUCRD_PD14 PWR_PUCRD_PD14_Msk
8944#define PWR_PUCRD_PD13_Pos (13U)
8945#define PWR_PUCRD_PD13_Msk (0x1UL << PWR_PUCRD_PD13_Pos)
8946#define PWR_PUCRD_PD13 PWR_PUCRD_PD13_Msk
8947#define PWR_PUCRD_PD12_Pos (12U)
8948#define PWR_PUCRD_PD12_Msk (0x1UL << PWR_PUCRD_PD12_Pos)
8949#define PWR_PUCRD_PD12 PWR_PUCRD_PD12_Msk
8950#define PWR_PUCRD_PD11_Pos (11U)
8951#define PWR_PUCRD_PD11_Msk (0x1UL << PWR_PUCRD_PD11_Pos)
8952#define PWR_PUCRD_PD11 PWR_PUCRD_PD11_Msk
8953#define PWR_PUCRD_PD10_Pos (10U)
8954#define PWR_PUCRD_PD10_Msk (0x1UL << PWR_PUCRD_PD10_Pos)
8955#define PWR_PUCRD_PD10 PWR_PUCRD_PD10_Msk
8956#define PWR_PUCRD_PD9_Pos (9U)
8957#define PWR_PUCRD_PD9_Msk (0x1UL << PWR_PUCRD_PD9_Pos)
8958#define PWR_PUCRD_PD9 PWR_PUCRD_PD9_Msk
8959#define PWR_PUCRD_PD8_Pos (8U)
8960#define PWR_PUCRD_PD8_Msk (0x1UL << PWR_PUCRD_PD8_Pos)
8961#define PWR_PUCRD_PD8 PWR_PUCRD_PD8_Msk
8962#define PWR_PUCRD_PD7_Pos (7U)
8963#define PWR_PUCRD_PD7_Msk (0x1UL << PWR_PUCRD_PD7_Pos)
8964#define PWR_PUCRD_PD7 PWR_PUCRD_PD7_Msk
8965#define PWR_PUCRD_PD6_Pos (6U)
8966#define PWR_PUCRD_PD6_Msk (0x1UL << PWR_PUCRD_PD6_Pos)
8967#define PWR_PUCRD_PD6 PWR_PUCRD_PD6_Msk
8968#define PWR_PUCRD_PD5_Pos (5U)
8969#define PWR_PUCRD_PD5_Msk (0x1UL << PWR_PUCRD_PD5_Pos)
8970#define PWR_PUCRD_PD5 PWR_PUCRD_PD5_Msk
8971#define PWR_PUCRD_PD4_Pos (4U)
8972#define PWR_PUCRD_PD4_Msk (0x1UL << PWR_PUCRD_PD4_Pos)
8973#define PWR_PUCRD_PD4 PWR_PUCRD_PD4_Msk
8974#define PWR_PUCRD_PD3_Pos (3U)
8975#define PWR_PUCRD_PD3_Msk (0x1UL << PWR_PUCRD_PD3_Pos)
8976#define PWR_PUCRD_PD3 PWR_PUCRD_PD3_Msk
8977#define PWR_PUCRD_PD2_Pos (2U)
8978#define PWR_PUCRD_PD2_Msk (0x1UL << PWR_PUCRD_PD2_Pos)
8979#define PWR_PUCRD_PD2 PWR_PUCRD_PD2_Msk
8980#define PWR_PUCRD_PD1_Pos (1U)
8981#define PWR_PUCRD_PD1_Msk (0x1UL << PWR_PUCRD_PD1_Pos)
8982#define PWR_PUCRD_PD1 PWR_PUCRD_PD1_Msk
8983#define PWR_PUCRD_PD0_Pos (0U)
8984#define PWR_PUCRD_PD0_Msk (0x1UL << PWR_PUCRD_PD0_Pos)
8985#define PWR_PUCRD_PD0 PWR_PUCRD_PD0_Msk
8987/******************** Bit definition for PWR_PDCRD register ********************/
8988#define PWR_PDCRD_PD15_Pos (15U)
8989#define PWR_PDCRD_PD15_Msk (0x1UL << PWR_PDCRD_PD15_Pos)
8990#define PWR_PDCRD_PD15 PWR_PDCRD_PD15_Msk
8991#define PWR_PDCRD_PD14_Pos (14U)
8992#define PWR_PDCRD_PD14_Msk (0x1UL << PWR_PDCRD_PD14_Pos)
8993#define PWR_PDCRD_PD14 PWR_PDCRD_PD14_Msk
8994#define PWR_PDCRD_PD13_Pos (13U)
8995#define PWR_PDCRD_PD13_Msk (0x1UL << PWR_PDCRD_PD13_Pos)
8996#define PWR_PDCRD_PD13 PWR_PDCRD_PD13_Msk
8997#define PWR_PDCRD_PD12_Pos (12U)
8998#define PWR_PDCRD_PD12_Msk (0x1UL << PWR_PDCRD_PD12_Pos)
8999#define PWR_PDCRD_PD12 PWR_PDCRD_PD12_Msk
9000#define PWR_PDCRD_PD11_Pos (11U)
9001#define PWR_PDCRD_PD11_Msk (0x1UL << PWR_PDCRD_PD11_Pos)
9002#define PWR_PDCRD_PD11 PWR_PDCRD_PD11_Msk
9003#define PWR_PDCRD_PD10_Pos (10U)
9004#define PWR_PDCRD_PD10_Msk (0x1UL << PWR_PDCRD_PD10_Pos)
9005#define PWR_PDCRD_PD10 PWR_PDCRD_PD10_Msk
9006#define PWR_PDCRD_PD9_Pos (9U)
9007#define PWR_PDCRD_PD9_Msk (0x1UL << PWR_PDCRD_PD9_Pos)
9008#define PWR_PDCRD_PD9 PWR_PDCRD_PD9_Msk
9009#define PWR_PDCRD_PD8_Pos (8U)
9010#define PWR_PDCRD_PD8_Msk (0x1UL << PWR_PDCRD_PD8_Pos)
9011#define PWR_PDCRD_PD8 PWR_PDCRD_PD8_Msk
9012#define PWR_PDCRD_PD7_Pos (7U)
9013#define PWR_PDCRD_PD7_Msk (0x1UL << PWR_PDCRD_PD7_Pos)
9014#define PWR_PDCRD_PD7 PWR_PDCRD_PD7_Msk
9015#define PWR_PDCRD_PD6_Pos (6U)
9016#define PWR_PDCRD_PD6_Msk (0x1UL << PWR_PDCRD_PD6_Pos)
9017#define PWR_PDCRD_PD6 PWR_PDCRD_PD6_Msk
9018#define PWR_PDCRD_PD5_Pos (5U)
9019#define PWR_PDCRD_PD5_Msk (0x1UL << PWR_PDCRD_PD5_Pos)
9020#define PWR_PDCRD_PD5 PWR_PDCRD_PD5_Msk
9021#define PWR_PDCRD_PD4_Pos (4U)
9022#define PWR_PDCRD_PD4_Msk (0x1UL << PWR_PDCRD_PD4_Pos)
9023#define PWR_PDCRD_PD4 PWR_PDCRD_PD4_Msk
9024#define PWR_PDCRD_PD3_Pos (3U)
9025#define PWR_PDCRD_PD3_Msk (0x1UL << PWR_PDCRD_PD3_Pos)
9026#define PWR_PDCRD_PD3 PWR_PDCRD_PD3_Msk
9027#define PWR_PDCRD_PD2_Pos (2U)
9028#define PWR_PDCRD_PD2_Msk (0x1UL << PWR_PDCRD_PD2_Pos)
9029#define PWR_PDCRD_PD2 PWR_PDCRD_PD2_Msk
9030#define PWR_PDCRD_PD1_Pos (1U)
9031#define PWR_PDCRD_PD1_Msk (0x1UL << PWR_PDCRD_PD1_Pos)
9032#define PWR_PDCRD_PD1 PWR_PDCRD_PD1_Msk
9033#define PWR_PDCRD_PD0_Pos (0U)
9034#define PWR_PDCRD_PD0_Msk (0x1UL << PWR_PDCRD_PD0_Pos)
9035#define PWR_PDCRD_PD0 PWR_PDCRD_PD0_Msk
9037/******************** Bit definition for PWR_PUCRE register ********************/
9038#define PWR_PUCRE_PE15_Pos (15U)
9039#define PWR_PUCRE_PE15_Msk (0x1UL << PWR_PUCRE_PE15_Pos)
9040#define PWR_PUCRE_PE15 PWR_PUCRE_PE15_Msk
9041#define PWR_PUCRE_PE14_Pos (14U)
9042#define PWR_PUCRE_PE14_Msk (0x1UL << PWR_PUCRE_PE14_Pos)
9043#define PWR_PUCRE_PE14 PWR_PUCRE_PE14_Msk
9044#define PWR_PUCRE_PE13_Pos (13U)
9045#define PWR_PUCRE_PE13_Msk (0x1UL << PWR_PUCRE_PE13_Pos)
9046#define PWR_PUCRE_PE13 PWR_PUCRE_PE13_Msk
9047#define PWR_PUCRE_PE12_Pos (12U)
9048#define PWR_PUCRE_PE12_Msk (0x1UL << PWR_PUCRE_PE12_Pos)
9049#define PWR_PUCRE_PE12 PWR_PUCRE_PE12_Msk
9050#define PWR_PUCRE_PE11_Pos (11U)
9051#define PWR_PUCRE_PE11_Msk (0x1UL << PWR_PUCRE_PE11_Pos)
9052#define PWR_PUCRE_PE11 PWR_PUCRE_PE11_Msk
9053#define PWR_PUCRE_PE10_Pos (10U)
9054#define PWR_PUCRE_PE10_Msk (0x1UL << PWR_PUCRE_PE10_Pos)
9055#define PWR_PUCRE_PE10 PWR_PUCRE_PE10_Msk
9056#define PWR_PUCRE_PE9_Pos (9U)
9057#define PWR_PUCRE_PE9_Msk (0x1UL << PWR_PUCRE_PE9_Pos)
9058#define PWR_PUCRE_PE9 PWR_PUCRE_PE9_Msk
9059#define PWR_PUCRE_PE8_Pos (8U)
9060#define PWR_PUCRE_PE8_Msk (0x1UL << PWR_PUCRE_PE8_Pos)
9061#define PWR_PUCRE_PE8 PWR_PUCRE_PE8_Msk
9062#define PWR_PUCRE_PE7_Pos (7U)
9063#define PWR_PUCRE_PE7_Msk (0x1UL << PWR_PUCRE_PE7_Pos)
9064#define PWR_PUCRE_PE7 PWR_PUCRE_PE7_Msk
9065#define PWR_PUCRE_PE6_Pos (6U)
9066#define PWR_PUCRE_PE6_Msk (0x1UL << PWR_PUCRE_PE6_Pos)
9067#define PWR_PUCRE_PE6 PWR_PUCRE_PE6_Msk
9068#define PWR_PUCRE_PE5_Pos (5U)
9069#define PWR_PUCRE_PE5_Msk (0x1UL << PWR_PUCRE_PE5_Pos)
9070#define PWR_PUCRE_PE5 PWR_PUCRE_PE5_Msk
9071#define PWR_PUCRE_PE4_Pos (4U)
9072#define PWR_PUCRE_PE4_Msk (0x1UL << PWR_PUCRE_PE4_Pos)
9073#define PWR_PUCRE_PE4 PWR_PUCRE_PE4_Msk
9074#define PWR_PUCRE_PE3_Pos (3U)
9075#define PWR_PUCRE_PE3_Msk (0x1UL << PWR_PUCRE_PE3_Pos)
9076#define PWR_PUCRE_PE3 PWR_PUCRE_PE3_Msk
9077#define PWR_PUCRE_PE2_Pos (2U)
9078#define PWR_PUCRE_PE2_Msk (0x1UL << PWR_PUCRE_PE2_Pos)
9079#define PWR_PUCRE_PE2 PWR_PUCRE_PE2_Msk
9080#define PWR_PUCRE_PE1_Pos (1U)
9081#define PWR_PUCRE_PE1_Msk (0x1UL << PWR_PUCRE_PE1_Pos)
9082#define PWR_PUCRE_PE1 PWR_PUCRE_PE1_Msk
9083#define PWR_PUCRE_PE0_Pos (0U)
9084#define PWR_PUCRE_PE0_Msk (0x1UL << PWR_PUCRE_PE0_Pos)
9085#define PWR_PUCRE_PE0 PWR_PUCRE_PE0_Msk
9087/******************** Bit definition for PWR_PDCRE register ********************/
9088#define PWR_PDCRE_PE15_Pos (15U)
9089#define PWR_PDCRE_PE15_Msk (0x1UL << PWR_PDCRE_PE15_Pos)
9090#define PWR_PDCRE_PE15 PWR_PDCRE_PE15_Msk
9091#define PWR_PDCRE_PE14_Pos (14U)
9092#define PWR_PDCRE_PE14_Msk (0x1UL << PWR_PDCRE_PE14_Pos)
9093#define PWR_PDCRE_PE14 PWR_PDCRE_PE14_Msk
9094#define PWR_PDCRE_PE13_Pos (13U)
9095#define PWR_PDCRE_PE13_Msk (0x1UL << PWR_PDCRE_PE13_Pos)
9096#define PWR_PDCRE_PE13 PWR_PDCRE_PE13_Msk
9097#define PWR_PDCRE_PE12_Pos (12U)
9098#define PWR_PDCRE_PE12_Msk (0x1UL << PWR_PDCRE_PE12_Pos)
9099#define PWR_PDCRE_PE12 PWR_PDCRE_PE12_Msk
9100#define PWR_PDCRE_PE11_Pos (11U)
9101#define PWR_PDCRE_PE11_Msk (0x1UL << PWR_PDCRE_PE11_Pos)
9102#define PWR_PDCRE_PE11 PWR_PDCRE_PE11_Msk
9103#define PWR_PDCRE_PE10_Pos (10U)
9104#define PWR_PDCRE_PE10_Msk (0x1UL << PWR_PDCRE_PE10_Pos)
9105#define PWR_PDCRE_PE10 PWR_PDCRE_PE10_Msk
9106#define PWR_PDCRE_PE9_Pos (9U)
9107#define PWR_PDCRE_PE9_Msk (0x1UL << PWR_PDCRE_PE9_Pos)
9108#define PWR_PDCRE_PE9 PWR_PDCRE_PE9_Msk
9109#define PWR_PDCRE_PE8_Pos (8U)
9110#define PWR_PDCRE_PE8_Msk (0x1UL << PWR_PDCRE_PE8_Pos)
9111#define PWR_PDCRE_PE8 PWR_PDCRE_PE8_Msk
9112#define PWR_PDCRE_PE7_Pos (7U)
9113#define PWR_PDCRE_PE7_Msk (0x1UL << PWR_PDCRE_PE7_Pos)
9114#define PWR_PDCRE_PE7 PWR_PDCRE_PE7_Msk
9115#define PWR_PDCRE_PE6_Pos (6U)
9116#define PWR_PDCRE_PE6_Msk (0x1UL << PWR_PDCRE_PE6_Pos)
9117#define PWR_PDCRE_PE6 PWR_PDCRE_PE6_Msk
9118#define PWR_PDCRE_PE5_Pos (5U)
9119#define PWR_PDCRE_PE5_Msk (0x1UL << PWR_PDCRE_PE5_Pos)
9120#define PWR_PDCRE_PE5 PWR_PDCRE_PE5_Msk
9121#define PWR_PDCRE_PE4_Pos (4U)
9122#define PWR_PDCRE_PE4_Msk (0x1UL << PWR_PDCRE_PE4_Pos)
9123#define PWR_PDCRE_PE4 PWR_PDCRE_PE4_Msk
9124#define PWR_PDCRE_PE3_Pos (3U)
9125#define PWR_PDCRE_PE3_Msk (0x1UL << PWR_PDCRE_PE3_Pos)
9126#define PWR_PDCRE_PE3 PWR_PDCRE_PE3_Msk
9127#define PWR_PDCRE_PE2_Pos (2U)
9128#define PWR_PDCRE_PE2_Msk (0x1UL << PWR_PDCRE_PE2_Pos)
9129#define PWR_PDCRE_PE2 PWR_PDCRE_PE2_Msk
9130#define PWR_PDCRE_PE1_Pos (1U)
9131#define PWR_PDCRE_PE1_Msk (0x1UL << PWR_PDCRE_PE1_Pos)
9132#define PWR_PDCRE_PE1 PWR_PDCRE_PE1_Msk
9133#define PWR_PDCRE_PE0_Pos (0U)
9134#define PWR_PDCRE_PE0_Msk (0x1UL << PWR_PDCRE_PE0_Pos)
9135#define PWR_PDCRE_PE0 PWR_PDCRE_PE0_Msk
9138/******************** Bit definition for PWR_PUCRH register ********************/
9139#define PWR_PUCRH_PH3_Pos (3U)
9140#define PWR_PUCRH_PH3_Msk (0x1UL << PWR_PUCRH_PH3_Pos)
9141#define PWR_PUCRH_PH3 PWR_PUCRH_PH3_Msk
9142#define PWR_PUCRH_PH1_Pos (1U)
9143#define PWR_PUCRH_PH1_Msk (0x1UL << PWR_PUCRH_PH1_Pos)
9144#define PWR_PUCRH_PH1 PWR_PUCRH_PH1_Msk
9145#define PWR_PUCRH_PH0_Pos (0U)
9146#define PWR_PUCRH_PH0_Msk (0x1UL << PWR_PUCRH_PH0_Pos)
9147#define PWR_PUCRH_PH0 PWR_PUCRH_PH0_Msk
9149/******************** Bit definition for PWR_PDCRH register ********************/
9150#define PWR_PDCRH_PH3_Pos (3U)
9151#define PWR_PDCRH_PH3_Msk (0x1UL << PWR_PDCRH_PH3_Pos)
9152#define PWR_PDCRH_PH3 PWR_PDCRH_PH3_Msk
9153#define PWR_PDCRH_PH1_Pos (1U)
9154#define PWR_PDCRH_PH1_Msk (0x1UL << PWR_PDCRH_PH1_Pos)
9155#define PWR_PDCRH_PH1 PWR_PDCRH_PH1_Msk
9156#define PWR_PDCRH_PH0_Pos (0U)
9157#define PWR_PDCRH_PH0_Msk (0x1UL << PWR_PDCRH_PH0_Pos)
9158#define PWR_PDCRH_PH0 PWR_PDCRH_PH0_Msk
9161/******************************************************************************/
9162/* */
9163/* Reset and Clock Control */
9164/* */
9165/******************************************************************************/
9166/*
9167* @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)
9168*/
9169#define RCC_PLLSAI1_SUPPORT
9170#define RCC_PLLP_SUPPORT
9171#define RCC_HSI48_SUPPORT
9172#define RCC_PLLP_DIV_2_31_SUPPORT
9173#define RCC_PLLSAI1P_DIV_2_31_SUPPORT
9174
9175/******************** Bit definition for RCC_CR register ********************/
9176#define RCC_CR_MSION_Pos (0U)
9177#define RCC_CR_MSION_Msk (0x1UL << RCC_CR_MSION_Pos)
9178#define RCC_CR_MSION RCC_CR_MSION_Msk
9179#define RCC_CR_MSIRDY_Pos (1U)
9180#define RCC_CR_MSIRDY_Msk (0x1UL << RCC_CR_MSIRDY_Pos)
9181#define RCC_CR_MSIRDY RCC_CR_MSIRDY_Msk
9182#define RCC_CR_MSIPLLEN_Pos (2U)
9183#define RCC_CR_MSIPLLEN_Msk (0x1UL << RCC_CR_MSIPLLEN_Pos)
9184#define RCC_CR_MSIPLLEN RCC_CR_MSIPLLEN_Msk
9185#define RCC_CR_MSIRGSEL_Pos (3U)
9186#define RCC_CR_MSIRGSEL_Msk (0x1UL << RCC_CR_MSIRGSEL_Pos)
9187#define RCC_CR_MSIRGSEL RCC_CR_MSIRGSEL_Msk
9190#define RCC_CR_MSIRANGE_Pos (4U)
9191#define RCC_CR_MSIRANGE_Msk (0xFUL << RCC_CR_MSIRANGE_Pos)
9192#define RCC_CR_MSIRANGE RCC_CR_MSIRANGE_Msk
9193#define RCC_CR_MSIRANGE_0 (0x0UL << RCC_CR_MSIRANGE_Pos)
9194#define RCC_CR_MSIRANGE_1 (0x1UL << RCC_CR_MSIRANGE_Pos)
9195#define RCC_CR_MSIRANGE_2 (0x2UL << RCC_CR_MSIRANGE_Pos)
9196#define RCC_CR_MSIRANGE_3 (0x3UL << RCC_CR_MSIRANGE_Pos)
9197#define RCC_CR_MSIRANGE_4 (0x4UL << RCC_CR_MSIRANGE_Pos)
9198#define RCC_CR_MSIRANGE_5 (0x5UL << RCC_CR_MSIRANGE_Pos)
9199#define RCC_CR_MSIRANGE_6 (0x6UL << RCC_CR_MSIRANGE_Pos)
9200#define RCC_CR_MSIRANGE_7 (0x7UL << RCC_CR_MSIRANGE_Pos)
9201#define RCC_CR_MSIRANGE_8 (0x8UL << RCC_CR_MSIRANGE_Pos)
9202#define RCC_CR_MSIRANGE_9 (0x9UL << RCC_CR_MSIRANGE_Pos)
9203#define RCC_CR_MSIRANGE_10 (0xAUL << RCC_CR_MSIRANGE_Pos)
9204#define RCC_CR_MSIRANGE_11 (0xBUL << RCC_CR_MSIRANGE_Pos)
9206#define RCC_CR_HSION_Pos (8U)
9207#define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos)
9208#define RCC_CR_HSION RCC_CR_HSION_Msk
9209#define RCC_CR_HSIKERON_Pos (9U)
9210#define RCC_CR_HSIKERON_Msk (0x1UL << RCC_CR_HSIKERON_Pos)
9211#define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk
9212#define RCC_CR_HSIRDY_Pos (10U)
9213#define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos)
9214#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk
9215#define RCC_CR_HSIASFS_Pos (11U)
9216#define RCC_CR_HSIASFS_Msk (0x1UL << RCC_CR_HSIASFS_Pos)
9217#define RCC_CR_HSIASFS RCC_CR_HSIASFS_Msk
9219#define RCC_CR_HSEON_Pos (16U)
9220#define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos)
9221#define RCC_CR_HSEON RCC_CR_HSEON_Msk
9222#define RCC_CR_HSERDY_Pos (17U)
9223#define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos)
9224#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk
9225#define RCC_CR_HSEBYP_Pos (18U)
9226#define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos)
9227#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk
9228#define RCC_CR_CSSON_Pos (19U)
9229#define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos)
9230#define RCC_CR_CSSON RCC_CR_CSSON_Msk
9232#define RCC_CR_PLLON_Pos (24U)
9233#define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos)
9234#define RCC_CR_PLLON RCC_CR_PLLON_Msk
9235#define RCC_CR_PLLRDY_Pos (25U)
9236#define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos)
9237#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk
9238#define RCC_CR_PLLSAI1ON_Pos (26U)
9239#define RCC_CR_PLLSAI1ON_Msk (0x1UL << RCC_CR_PLLSAI1ON_Pos)
9240#define RCC_CR_PLLSAI1ON RCC_CR_PLLSAI1ON_Msk
9241#define RCC_CR_PLLSAI1RDY_Pos (27U)
9242#define RCC_CR_PLLSAI1RDY_Msk (0x1UL << RCC_CR_PLLSAI1RDY_Pos)
9243#define RCC_CR_PLLSAI1RDY RCC_CR_PLLSAI1RDY_Msk
9245/******************** Bit definition for RCC_ICSCR register ***************/
9247#define RCC_ICSCR_MSICAL_Pos (0U)
9248#define RCC_ICSCR_MSICAL_Msk (0xFFUL << RCC_ICSCR_MSICAL_Pos)
9249#define RCC_ICSCR_MSICAL RCC_ICSCR_MSICAL_Msk
9250#define RCC_ICSCR_MSICAL_0 (0x01UL << RCC_ICSCR_MSICAL_Pos)
9251#define RCC_ICSCR_MSICAL_1 (0x02UL << RCC_ICSCR_MSICAL_Pos)
9252#define RCC_ICSCR_MSICAL_2 (0x04UL << RCC_ICSCR_MSICAL_Pos)
9253#define RCC_ICSCR_MSICAL_3 (0x08UL << RCC_ICSCR_MSICAL_Pos)
9254#define RCC_ICSCR_MSICAL_4 (0x10UL << RCC_ICSCR_MSICAL_Pos)
9255#define RCC_ICSCR_MSICAL_5 (0x20UL << RCC_ICSCR_MSICAL_Pos)
9256#define RCC_ICSCR_MSICAL_6 (0x40UL << RCC_ICSCR_MSICAL_Pos)
9257#define RCC_ICSCR_MSICAL_7 (0x80UL << RCC_ICSCR_MSICAL_Pos)
9260#define RCC_ICSCR_MSITRIM_Pos (8U)
9261#define RCC_ICSCR_MSITRIM_Msk (0xFFUL << RCC_ICSCR_MSITRIM_Pos)
9262#define RCC_ICSCR_MSITRIM RCC_ICSCR_MSITRIM_Msk
9263#define RCC_ICSCR_MSITRIM_0 (0x01UL << RCC_ICSCR_MSITRIM_Pos)
9264#define RCC_ICSCR_MSITRIM_1 (0x02UL << RCC_ICSCR_MSITRIM_Pos)
9265#define RCC_ICSCR_MSITRIM_2 (0x04UL << RCC_ICSCR_MSITRIM_Pos)
9266#define RCC_ICSCR_MSITRIM_3 (0x08UL << RCC_ICSCR_MSITRIM_Pos)
9267#define RCC_ICSCR_MSITRIM_4 (0x10UL << RCC_ICSCR_MSITRIM_Pos)
9268#define RCC_ICSCR_MSITRIM_5 (0x20UL << RCC_ICSCR_MSITRIM_Pos)
9269#define RCC_ICSCR_MSITRIM_6 (0x40UL << RCC_ICSCR_MSITRIM_Pos)
9270#define RCC_ICSCR_MSITRIM_7 (0x80UL << RCC_ICSCR_MSITRIM_Pos)
9273#define RCC_ICSCR_HSICAL_Pos (16U)
9274#define RCC_ICSCR_HSICAL_Msk (0xFFUL << RCC_ICSCR_HSICAL_Pos)
9275#define RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_Msk
9276#define RCC_ICSCR_HSICAL_0 (0x01UL << RCC_ICSCR_HSICAL_Pos)
9277#define RCC_ICSCR_HSICAL_1 (0x02UL << RCC_ICSCR_HSICAL_Pos)
9278#define RCC_ICSCR_HSICAL_2 (0x04UL << RCC_ICSCR_HSICAL_Pos)
9279#define RCC_ICSCR_HSICAL_3 (0x08UL << RCC_ICSCR_HSICAL_Pos)
9280#define RCC_ICSCR_HSICAL_4 (0x10UL << RCC_ICSCR_HSICAL_Pos)
9281#define RCC_ICSCR_HSICAL_5 (0x20UL << RCC_ICSCR_HSICAL_Pos)
9282#define RCC_ICSCR_HSICAL_6 (0x40UL << RCC_ICSCR_HSICAL_Pos)
9283#define RCC_ICSCR_HSICAL_7 (0x80UL << RCC_ICSCR_HSICAL_Pos)
9286#define RCC_ICSCR_HSITRIM_Pos (24U)
9287#define RCC_ICSCR_HSITRIM_Msk (0x1FUL << RCC_ICSCR_HSITRIM_Pos)
9288#define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk
9289#define RCC_ICSCR_HSITRIM_0 (0x01UL << RCC_ICSCR_HSITRIM_Pos)
9290#define RCC_ICSCR_HSITRIM_1 (0x02UL << RCC_ICSCR_HSITRIM_Pos)
9291#define RCC_ICSCR_HSITRIM_2 (0x04UL << RCC_ICSCR_HSITRIM_Pos)
9292#define RCC_ICSCR_HSITRIM_3 (0x08UL << RCC_ICSCR_HSITRIM_Pos)
9293#define RCC_ICSCR_HSITRIM_4 (0x10UL << RCC_ICSCR_HSITRIM_Pos)
9295/******************** Bit definition for RCC_CFGR register ******************/
9297#define RCC_CFGR_SW_Pos (0U)
9298#define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos)
9299#define RCC_CFGR_SW RCC_CFGR_SW_Msk
9300#define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos)
9301#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos)
9303#define RCC_CFGR_SW_MSI (0x00000000UL)
9304#define RCC_CFGR_SW_HSI (0x00000001UL)
9305#define RCC_CFGR_SW_HSE (0x00000002UL)
9306#define RCC_CFGR_SW_PLL (0x00000003UL)
9309#define RCC_CFGR_SWS_Pos (2U)
9310#define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos)
9311#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk
9312#define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos)
9313#define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos)
9315#define RCC_CFGR_SWS_MSI (0x00000000UL)
9316#define RCC_CFGR_SWS_HSI (0x00000004UL)
9317#define RCC_CFGR_SWS_HSE (0x00000008UL)
9318#define RCC_CFGR_SWS_PLL (0x0000000CUL)
9321#define RCC_CFGR_HPRE_Pos (4U)
9322#define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos)
9323#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk
9324#define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos)
9325#define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos)
9326#define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos)
9327#define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos)
9329#define RCC_CFGR_HPRE_DIV1 (0x00000000UL)
9330#define RCC_CFGR_HPRE_DIV2 (0x00000080UL)
9331#define RCC_CFGR_HPRE_DIV4 (0x00000090UL)
9332#define RCC_CFGR_HPRE_DIV8 (0x000000A0UL)
9333#define RCC_CFGR_HPRE_DIV16 (0x000000B0UL)
9334#define RCC_CFGR_HPRE_DIV64 (0x000000C0UL)
9335#define RCC_CFGR_HPRE_DIV128 (0x000000D0UL)
9336#define RCC_CFGR_HPRE_DIV256 (0x000000E0UL)
9337#define RCC_CFGR_HPRE_DIV512 (0x000000F0UL)
9340#define RCC_CFGR_PPRE1_Pos (8U)
9341#define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos)
9342#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk
9343#define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos)
9344#define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos)
9345#define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos)
9347#define RCC_CFGR_PPRE1_DIV1 (0x00000000UL)
9348#define RCC_CFGR_PPRE1_DIV2 (0x00000400UL)
9349#define RCC_CFGR_PPRE1_DIV4 (0x00000500UL)
9350#define RCC_CFGR_PPRE1_DIV8 (0x00000600UL)
9351#define RCC_CFGR_PPRE1_DIV16 (0x00000700UL)
9354#define RCC_CFGR_PPRE2_Pos (11U)
9355#define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos)
9356#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk
9357#define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos)
9358#define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos)
9359#define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos)
9361#define RCC_CFGR_PPRE2_DIV1 (0x00000000UL)
9362#define RCC_CFGR_PPRE2_DIV2 (0x00002000UL)
9363#define RCC_CFGR_PPRE2_DIV4 (0x00002800UL)
9364#define RCC_CFGR_PPRE2_DIV8 (0x00003000UL)
9365#define RCC_CFGR_PPRE2_DIV16 (0x00003800UL)
9367#define RCC_CFGR_STOPWUCK_Pos (15U)
9368#define RCC_CFGR_STOPWUCK_Msk (0x1UL << RCC_CFGR_STOPWUCK_Pos)
9369#define RCC_CFGR_STOPWUCK RCC_CFGR_STOPWUCK_Msk
9372#define RCC_CFGR_MCOSEL_Pos (24U)
9373#define RCC_CFGR_MCOSEL_Msk (0xFUL << RCC_CFGR_MCOSEL_Pos)
9374#define RCC_CFGR_MCOSEL RCC_CFGR_MCOSEL_Msk
9375#define RCC_CFGR_MCOSEL_0 (0x1UL << RCC_CFGR_MCOSEL_Pos)
9376#define RCC_CFGR_MCOSEL_1 (0x2UL << RCC_CFGR_MCOSEL_Pos)
9377#define RCC_CFGR_MCOSEL_2 (0x4UL << RCC_CFGR_MCOSEL_Pos)
9378#define RCC_CFGR_MCOSEL_3 (0x8UL << RCC_CFGR_MCOSEL_Pos)
9380#define RCC_CFGR_MCOPRE_Pos (28U)
9381#define RCC_CFGR_MCOPRE_Msk (0x7UL << RCC_CFGR_MCOPRE_Pos)
9382#define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk
9383#define RCC_CFGR_MCOPRE_0 (0x1UL << RCC_CFGR_MCOPRE_Pos)
9384#define RCC_CFGR_MCOPRE_1 (0x2UL << RCC_CFGR_MCOPRE_Pos)
9385#define RCC_CFGR_MCOPRE_2 (0x4UL << RCC_CFGR_MCOPRE_Pos)
9387#define RCC_CFGR_MCOPRE_DIV1 (0x00000000UL)
9388#define RCC_CFGR_MCOPRE_DIV2 (0x10000000UL)
9389#define RCC_CFGR_MCOPRE_DIV4 (0x20000000UL)
9390#define RCC_CFGR_MCOPRE_DIV8 (0x30000000UL)
9391#define RCC_CFGR_MCOPRE_DIV16 (0x40000000UL)
9393/* Legacy aliases */
9394#define RCC_CFGR_MCO_PRE RCC_CFGR_MCOPRE
9395#define RCC_CFGR_MCO_PRE_1 RCC_CFGR_MCOPRE_DIV1
9396#define RCC_CFGR_MCO_PRE_2 RCC_CFGR_MCOPRE_DIV2
9397#define RCC_CFGR_MCO_PRE_4 RCC_CFGR_MCOPRE_DIV4
9398#define RCC_CFGR_MCO_PRE_8 RCC_CFGR_MCOPRE_DIV8
9399#define RCC_CFGR_MCO_PRE_16 RCC_CFGR_MCOPRE_DIV16
9400
9401/******************** Bit definition for RCC_PLLCFGR register ***************/
9402#define RCC_PLLCFGR_PLLSRC_Pos (0U)
9403#define RCC_PLLCFGR_PLLSRC_Msk (0x3UL << RCC_PLLCFGR_PLLSRC_Pos)
9404#define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk
9405
9406#define RCC_PLLCFGR_PLLSRC_MSI_Pos (0U)
9407#define RCC_PLLCFGR_PLLSRC_MSI_Msk (0x1UL << RCC_PLLCFGR_PLLSRC_MSI_Pos)
9408#define RCC_PLLCFGR_PLLSRC_MSI RCC_PLLCFGR_PLLSRC_MSI_Msk
9409#define RCC_PLLCFGR_PLLSRC_HSI_Pos (1U)
9410#define RCC_PLLCFGR_PLLSRC_HSI_Msk (0x1UL << RCC_PLLCFGR_PLLSRC_HSI_Pos)
9411#define RCC_PLLCFGR_PLLSRC_HSI RCC_PLLCFGR_PLLSRC_HSI_Msk
9412#define RCC_PLLCFGR_PLLSRC_HSE_Pos (0U)
9413#define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x3UL << RCC_PLLCFGR_PLLSRC_HSE_Pos)
9414#define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk
9416#define RCC_PLLCFGR_PLLM_Pos (4U)
9417#define RCC_PLLCFGR_PLLM_Msk (0x7UL << RCC_PLLCFGR_PLLM_Pos)
9418#define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk
9419#define RCC_PLLCFGR_PLLM_0 (0x1UL << RCC_PLLCFGR_PLLM_Pos)
9420#define RCC_PLLCFGR_PLLM_1 (0x2UL << RCC_PLLCFGR_PLLM_Pos)
9421#define RCC_PLLCFGR_PLLM_2 (0x4UL << RCC_PLLCFGR_PLLM_Pos)
9423#define RCC_PLLCFGR_PLLN_Pos (8U)
9424#define RCC_PLLCFGR_PLLN_Msk (0x7FUL << RCC_PLLCFGR_PLLN_Pos)
9425#define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk
9426#define RCC_PLLCFGR_PLLN_0 (0x01UL << RCC_PLLCFGR_PLLN_Pos)
9427#define RCC_PLLCFGR_PLLN_1 (0x02UL << RCC_PLLCFGR_PLLN_Pos)
9428#define RCC_PLLCFGR_PLLN_2 (0x04UL << RCC_PLLCFGR_PLLN_Pos)
9429#define RCC_PLLCFGR_PLLN_3 (0x08UL << RCC_PLLCFGR_PLLN_Pos)
9430#define RCC_PLLCFGR_PLLN_4 (0x10UL << RCC_PLLCFGR_PLLN_Pos)
9431#define RCC_PLLCFGR_PLLN_5 (0x20UL << RCC_PLLCFGR_PLLN_Pos)
9432#define RCC_PLLCFGR_PLLN_6 (0x40UL << RCC_PLLCFGR_PLLN_Pos)
9434#define RCC_PLLCFGR_PLLPEN_Pos (16U)
9435#define RCC_PLLCFGR_PLLPEN_Msk (0x1UL << RCC_PLLCFGR_PLLPEN_Pos)
9436#define RCC_PLLCFGR_PLLPEN RCC_PLLCFGR_PLLPEN_Msk
9437#define RCC_PLLCFGR_PLLP_Pos (17U)
9438#define RCC_PLLCFGR_PLLP_Msk (0x1UL << RCC_PLLCFGR_PLLP_Pos)
9439#define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk
9440#define RCC_PLLCFGR_PLLQEN_Pos (20U)
9441#define RCC_PLLCFGR_PLLQEN_Msk (0x1UL << RCC_PLLCFGR_PLLQEN_Pos)
9442#define RCC_PLLCFGR_PLLQEN RCC_PLLCFGR_PLLQEN_Msk
9443
9444#define RCC_PLLCFGR_PLLQ_Pos (21U)
9445#define RCC_PLLCFGR_PLLQ_Msk (0x3UL << RCC_PLLCFGR_PLLQ_Pos)
9446#define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk
9447#define RCC_PLLCFGR_PLLQ_0 (0x1UL << RCC_PLLCFGR_PLLQ_Pos)
9448#define RCC_PLLCFGR_PLLQ_1 (0x2UL << RCC_PLLCFGR_PLLQ_Pos)
9450#define RCC_PLLCFGR_PLLREN_Pos (24U)
9451#define RCC_PLLCFGR_PLLREN_Msk (0x1UL << RCC_PLLCFGR_PLLREN_Pos)
9452#define RCC_PLLCFGR_PLLREN RCC_PLLCFGR_PLLREN_Msk
9453#define RCC_PLLCFGR_PLLR_Pos (25U)
9454#define RCC_PLLCFGR_PLLR_Msk (0x3UL << RCC_PLLCFGR_PLLR_Pos)
9455#define RCC_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_Msk
9456#define RCC_PLLCFGR_PLLR_0 (0x1UL << RCC_PLLCFGR_PLLR_Pos)
9457#define RCC_PLLCFGR_PLLR_1 (0x2UL << RCC_PLLCFGR_PLLR_Pos)
9459#define RCC_PLLCFGR_PLLPDIV_Pos (27U)
9460#define RCC_PLLCFGR_PLLPDIV_Msk (0x1FUL << RCC_PLLCFGR_PLLPDIV_Pos)
9461#define RCC_PLLCFGR_PLLPDIV RCC_PLLCFGR_PLLPDIV_Msk
9462#define RCC_PLLCFGR_PLLPDIV_0 (0x01UL << RCC_PLLCFGR_PLLPDIV_Pos)
9463#define RCC_PLLCFGR_PLLPDIV_1 (0x02UL << RCC_PLLCFGR_PLLPDIV_Pos)
9464#define RCC_PLLCFGR_PLLPDIV_2 (0x04UL << RCC_PLLCFGR_PLLPDIV_Pos)
9465#define RCC_PLLCFGR_PLLPDIV_3 (0x08UL << RCC_PLLCFGR_PLLPDIV_Pos)
9466#define RCC_PLLCFGR_PLLPDIV_4 (0x10UL << RCC_PLLCFGR_PLLPDIV_Pos)
9468/******************** Bit definition for RCC_PLLSAI1CFGR register ************/
9469#define RCC_PLLSAI1CFGR_PLLSAI1N_Pos (8U)
9470#define RCC_PLLSAI1CFGR_PLLSAI1N_Msk (0x7FUL << RCC_PLLSAI1CFGR_PLLSAI1N_Pos)
9471#define RCC_PLLSAI1CFGR_PLLSAI1N RCC_PLLSAI1CFGR_PLLSAI1N_Msk
9472#define RCC_PLLSAI1CFGR_PLLSAI1N_0 (0x01UL << RCC_PLLSAI1CFGR_PLLSAI1N_Pos)
9473#define RCC_PLLSAI1CFGR_PLLSAI1N_1 (0x02UL << RCC_PLLSAI1CFGR_PLLSAI1N_Pos)
9474#define RCC_PLLSAI1CFGR_PLLSAI1N_2 (0x04UL << RCC_PLLSAI1CFGR_PLLSAI1N_Pos)
9475#define RCC_PLLSAI1CFGR_PLLSAI1N_3 (0x08UL << RCC_PLLSAI1CFGR_PLLSAI1N_Pos)
9476#define RCC_PLLSAI1CFGR_PLLSAI1N_4 (0x10UL << RCC_PLLSAI1CFGR_PLLSAI1N_Pos)
9477#define RCC_PLLSAI1CFGR_PLLSAI1N_5 (0x20UL << RCC_PLLSAI1CFGR_PLLSAI1N_Pos)
9478#define RCC_PLLSAI1CFGR_PLLSAI1N_6 (0x40UL << RCC_PLLSAI1CFGR_PLLSAI1N_Pos)
9480#define RCC_PLLSAI1CFGR_PLLSAI1PEN_Pos (16U)
9481#define RCC_PLLSAI1CFGR_PLLSAI1PEN_Msk (0x1UL << RCC_PLLSAI1CFGR_PLLSAI1PEN_Pos)
9482#define RCC_PLLSAI1CFGR_PLLSAI1PEN RCC_PLLSAI1CFGR_PLLSAI1PEN_Msk
9483#define RCC_PLLSAI1CFGR_PLLSAI1P_Pos (17U)
9484#define RCC_PLLSAI1CFGR_PLLSAI1P_Msk (0x1UL << RCC_PLLSAI1CFGR_PLLSAI1P_Pos)
9485#define RCC_PLLSAI1CFGR_PLLSAI1P RCC_PLLSAI1CFGR_PLLSAI1P_Msk
9486
9487#define RCC_PLLSAI1CFGR_PLLSAI1QEN_Pos (20U)
9488#define RCC_PLLSAI1CFGR_PLLSAI1QEN_Msk (0x1UL << RCC_PLLSAI1CFGR_PLLSAI1QEN_Pos)
9489#define RCC_PLLSAI1CFGR_PLLSAI1QEN RCC_PLLSAI1CFGR_PLLSAI1QEN_Msk
9490#define RCC_PLLSAI1CFGR_PLLSAI1Q_Pos (21U)
9491#define RCC_PLLSAI1CFGR_PLLSAI1Q_Msk (0x3UL << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos)
9492#define RCC_PLLSAI1CFGR_PLLSAI1Q RCC_PLLSAI1CFGR_PLLSAI1Q_Msk
9493#define RCC_PLLSAI1CFGR_PLLSAI1Q_0 (0x1UL << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos)
9494#define RCC_PLLSAI1CFGR_PLLSAI1Q_1 (0x2UL << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos)
9496#define RCC_PLLSAI1CFGR_PLLSAI1REN_Pos (24U)
9497#define RCC_PLLSAI1CFGR_PLLSAI1REN_Msk (0x1UL << RCC_PLLSAI1CFGR_PLLSAI1REN_Pos)
9498#define RCC_PLLSAI1CFGR_PLLSAI1REN RCC_PLLSAI1CFGR_PLLSAI1REN_Msk
9499#define RCC_PLLSAI1CFGR_PLLSAI1R_Pos (25U)
9500#define RCC_PLLSAI1CFGR_PLLSAI1R_Msk (0x3UL << RCC_PLLSAI1CFGR_PLLSAI1R_Pos)
9501#define RCC_PLLSAI1CFGR_PLLSAI1R RCC_PLLSAI1CFGR_PLLSAI1R_Msk
9502#define RCC_PLLSAI1CFGR_PLLSAI1R_0 (0x1UL << RCC_PLLSAI1CFGR_PLLSAI1R_Pos)
9503#define RCC_PLLSAI1CFGR_PLLSAI1R_1 (0x2UL << RCC_PLLSAI1CFGR_PLLSAI1R_Pos)
9505#define RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos (27U)
9506#define RCC_PLLSAI1CFGR_PLLSAI1PDIV_Msk (0x1FUL << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos)
9507#define RCC_PLLSAI1CFGR_PLLSAI1PDIV RCC_PLLSAI1CFGR_PLLSAI1PDIV_Msk
9508#define RCC_PLLSAI1CFGR_PLLSAI1PDIV_0 (0x01UL << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos)
9509#define RCC_PLLSAI1CFGR_PLLSAI1PDIV_1 (0x02UL << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos)
9510#define RCC_PLLSAI1CFGR_PLLSAI1PDIV_2 (0x04UL << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos)
9511#define RCC_PLLSAI1CFGR_PLLSAI1PDIV_3 (0x08UL << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos)
9512#define RCC_PLLSAI1CFGR_PLLSAI1PDIV_4 (0x10UL << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos)
9514/******************** Bit definition for RCC_CIER register ******************/
9515#define RCC_CIER_LSIRDYIE_Pos (0U)
9516#define RCC_CIER_LSIRDYIE_Msk (0x1UL << RCC_CIER_LSIRDYIE_Pos)
9517#define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk
9518#define RCC_CIER_LSERDYIE_Pos (1U)
9519#define RCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos)
9520#define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk
9521#define RCC_CIER_MSIRDYIE_Pos (2U)
9522#define RCC_CIER_MSIRDYIE_Msk (0x1UL << RCC_CIER_MSIRDYIE_Pos)
9523#define RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE_Msk
9524#define RCC_CIER_HSIRDYIE_Pos (3U)
9525#define RCC_CIER_HSIRDYIE_Msk (0x1UL << RCC_CIER_HSIRDYIE_Pos)
9526#define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk
9527#define RCC_CIER_HSERDYIE_Pos (4U)
9528#define RCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos)
9529#define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk
9530#define RCC_CIER_PLLRDYIE_Pos (5U)
9531#define RCC_CIER_PLLRDYIE_Msk (0x1UL << RCC_CIER_PLLRDYIE_Pos)
9532#define RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE_Msk
9533#define RCC_CIER_PLLSAI1RDYIE_Pos (6U)
9534#define RCC_CIER_PLLSAI1RDYIE_Msk (0x1UL << RCC_CIER_PLLSAI1RDYIE_Pos)
9535#define RCC_CIER_PLLSAI1RDYIE RCC_CIER_PLLSAI1RDYIE_Msk
9536#define RCC_CIER_LSECSSIE_Pos (9U)
9537#define RCC_CIER_LSECSSIE_Msk (0x1UL << RCC_CIER_LSECSSIE_Pos)
9538#define RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE_Msk
9539#define RCC_CIER_HSI48RDYIE_Pos (10U)
9540#define RCC_CIER_HSI48RDYIE_Msk (0x1UL << RCC_CIER_HSI48RDYIE_Pos)
9541#define RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE_Msk
9542
9543/******************** Bit definition for RCC_CIFR register ******************/
9544#define RCC_CIFR_LSIRDYF_Pos (0U)
9545#define RCC_CIFR_LSIRDYF_Msk (0x1UL << RCC_CIFR_LSIRDYF_Pos)
9546#define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk
9547#define RCC_CIFR_LSERDYF_Pos (1U)
9548#define RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos)
9549#define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk
9550#define RCC_CIFR_MSIRDYF_Pos (2U)
9551#define RCC_CIFR_MSIRDYF_Msk (0x1UL << RCC_CIFR_MSIRDYF_Pos)
9552#define RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF_Msk
9553#define RCC_CIFR_HSIRDYF_Pos (3U)
9554#define RCC_CIFR_HSIRDYF_Msk (0x1UL << RCC_CIFR_HSIRDYF_Pos)
9555#define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk
9556#define RCC_CIFR_HSERDYF_Pos (4U)
9557#define RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos)
9558#define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk
9559#define RCC_CIFR_PLLRDYF_Pos (5U)
9560#define RCC_CIFR_PLLRDYF_Msk (0x1UL << RCC_CIFR_PLLRDYF_Pos)
9561#define RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF_Msk
9562#define RCC_CIFR_PLLSAI1RDYF_Pos (6U)
9563#define RCC_CIFR_PLLSAI1RDYF_Msk (0x1UL << RCC_CIFR_PLLSAI1RDYF_Pos)
9564#define RCC_CIFR_PLLSAI1RDYF RCC_CIFR_PLLSAI1RDYF_Msk
9565#define RCC_CIFR_CSSF_Pos (8U)
9566#define RCC_CIFR_CSSF_Msk (0x1UL << RCC_CIFR_CSSF_Pos)
9567#define RCC_CIFR_CSSF RCC_CIFR_CSSF_Msk
9568#define RCC_CIFR_LSECSSF_Pos (9U)
9569#define RCC_CIFR_LSECSSF_Msk (0x1UL << RCC_CIFR_LSECSSF_Pos)
9570#define RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF_Msk
9571#define RCC_CIFR_HSI48RDYF_Pos (10U)
9572#define RCC_CIFR_HSI48RDYF_Msk (0x1UL << RCC_CIFR_HSI48RDYF_Pos)
9573#define RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF_Msk
9574
9575/******************** Bit definition for RCC_CICR register ******************/
9576#define RCC_CICR_LSIRDYC_Pos (0U)
9577#define RCC_CICR_LSIRDYC_Msk (0x1UL << RCC_CICR_LSIRDYC_Pos)
9578#define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk
9579#define RCC_CICR_LSERDYC_Pos (1U)
9580#define RCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos)
9581#define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk
9582#define RCC_CICR_MSIRDYC_Pos (2U)
9583#define RCC_CICR_MSIRDYC_Msk (0x1UL << RCC_CICR_MSIRDYC_Pos)
9584#define RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC_Msk
9585#define RCC_CICR_HSIRDYC_Pos (3U)
9586#define RCC_CICR_HSIRDYC_Msk (0x1UL << RCC_CICR_HSIRDYC_Pos)
9587#define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk
9588#define RCC_CICR_HSERDYC_Pos (4U)
9589#define RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos)
9590#define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk
9591#define RCC_CICR_PLLRDYC_Pos (5U)
9592#define RCC_CICR_PLLRDYC_Msk (0x1UL << RCC_CICR_PLLRDYC_Pos)
9593#define RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC_Msk
9594#define RCC_CICR_PLLSAI1RDYC_Pos (6U)
9595#define RCC_CICR_PLLSAI1RDYC_Msk (0x1UL << RCC_CICR_PLLSAI1RDYC_Pos)
9596#define RCC_CICR_PLLSAI1RDYC RCC_CICR_PLLSAI1RDYC_Msk
9597#define RCC_CICR_CSSC_Pos (8U)
9598#define RCC_CICR_CSSC_Msk (0x1UL << RCC_CICR_CSSC_Pos)
9599#define RCC_CICR_CSSC RCC_CICR_CSSC_Msk
9600#define RCC_CICR_LSECSSC_Pos (9U)
9601#define RCC_CICR_LSECSSC_Msk (0x1UL << RCC_CICR_LSECSSC_Pos)
9602#define RCC_CICR_LSECSSC RCC_CICR_LSECSSC_Msk
9603#define RCC_CICR_HSI48RDYC_Pos (10U)
9604#define RCC_CICR_HSI48RDYC_Msk (0x1UL << RCC_CICR_HSI48RDYC_Pos)
9605#define RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC_Msk
9606
9607/******************** Bit definition for RCC_AHB1RSTR register **************/
9608#define RCC_AHB1RSTR_DMA1RST_Pos (0U)
9609#define RCC_AHB1RSTR_DMA1RST_Msk (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)
9610#define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
9611#define RCC_AHB1RSTR_DMA2RST_Pos (1U)
9612#define RCC_AHB1RSTR_DMA2RST_Msk (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)
9613#define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
9614#define RCC_AHB1RSTR_FLASHRST_Pos (8U)
9615#define RCC_AHB1RSTR_FLASHRST_Msk (0x1UL << RCC_AHB1RSTR_FLASHRST_Pos)
9616#define RCC_AHB1RSTR_FLASHRST RCC_AHB1RSTR_FLASHRST_Msk
9617#define RCC_AHB1RSTR_CRCRST_Pos (12U)
9618#define RCC_AHB1RSTR_CRCRST_Msk (0x1UL << RCC_AHB1RSTR_CRCRST_Pos)
9619#define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk
9620#define RCC_AHB1RSTR_TSCRST_Pos (16U)
9621#define RCC_AHB1RSTR_TSCRST_Msk (0x1UL << RCC_AHB1RSTR_TSCRST_Pos)
9622#define RCC_AHB1RSTR_TSCRST RCC_AHB1RSTR_TSCRST_Msk
9623
9624/******************** Bit definition for RCC_AHB2RSTR register **************/
9625#define RCC_AHB2RSTR_GPIOARST_Pos (0U)
9626#define RCC_AHB2RSTR_GPIOARST_Msk (0x1UL << RCC_AHB2RSTR_GPIOARST_Pos)
9627#define RCC_AHB2RSTR_GPIOARST RCC_AHB2RSTR_GPIOARST_Msk
9628#define RCC_AHB2RSTR_GPIOBRST_Pos (1U)
9629#define RCC_AHB2RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOBRST_Pos)
9630#define RCC_AHB2RSTR_GPIOBRST RCC_AHB2RSTR_GPIOBRST_Msk
9631#define RCC_AHB2RSTR_GPIOCRST_Pos (2U)
9632#define RCC_AHB2RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOCRST_Pos)
9633#define RCC_AHB2RSTR_GPIOCRST RCC_AHB2RSTR_GPIOCRST_Msk
9634#define RCC_AHB2RSTR_GPIODRST_Pos (3U)
9635#define RCC_AHB2RSTR_GPIODRST_Msk (0x1UL << RCC_AHB2RSTR_GPIODRST_Pos)
9636#define RCC_AHB2RSTR_GPIODRST RCC_AHB2RSTR_GPIODRST_Msk
9637#define RCC_AHB2RSTR_GPIOERST_Pos (4U)
9638#define RCC_AHB2RSTR_GPIOERST_Msk (0x1UL << RCC_AHB2RSTR_GPIOERST_Pos)
9639#define RCC_AHB2RSTR_GPIOERST RCC_AHB2RSTR_GPIOERST_Msk
9640#define RCC_AHB2RSTR_GPIOHRST_Pos (7U)
9641#define RCC_AHB2RSTR_GPIOHRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOHRST_Pos)
9642#define RCC_AHB2RSTR_GPIOHRST RCC_AHB2RSTR_GPIOHRST_Msk
9643#define RCC_AHB2RSTR_ADCRST_Pos (13U)
9644#define RCC_AHB2RSTR_ADCRST_Msk (0x1UL << RCC_AHB2RSTR_ADCRST_Pos)
9645#define RCC_AHB2RSTR_ADCRST RCC_AHB2RSTR_ADCRST_Msk
9646#define RCC_AHB2RSTR_RNGRST_Pos (18U)
9647#define RCC_AHB2RSTR_RNGRST_Msk (0x1UL << RCC_AHB2RSTR_RNGRST_Pos)
9648#define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
9649
9650/******************** Bit definition for RCC_AHB3RSTR register **************/
9651#define RCC_AHB3RSTR_QSPIRST_Pos (8U)
9652#define RCC_AHB3RSTR_QSPIRST_Msk (0x1UL << RCC_AHB3RSTR_QSPIRST_Pos)
9653#define RCC_AHB3RSTR_QSPIRST RCC_AHB3RSTR_QSPIRST_Msk
9654
9655/******************** Bit definition for RCC_APB1RSTR1 register **************/
9656#define RCC_APB1RSTR1_TIM2RST_Pos (0U)
9657#define RCC_APB1RSTR1_TIM2RST_Msk (0x1UL << RCC_APB1RSTR1_TIM2RST_Pos)
9658#define RCC_APB1RSTR1_TIM2RST RCC_APB1RSTR1_TIM2RST_Msk
9659#define RCC_APB1RSTR1_TIM6RST_Pos (4U)
9660#define RCC_APB1RSTR1_TIM6RST_Msk (0x1UL << RCC_APB1RSTR1_TIM6RST_Pos)
9661#define RCC_APB1RSTR1_TIM6RST RCC_APB1RSTR1_TIM6RST_Msk
9662#define RCC_APB1RSTR1_TIM7RST_Pos (5U)
9663#define RCC_APB1RSTR1_TIM7RST_Msk (0x1UL << RCC_APB1RSTR1_TIM7RST_Pos)
9664#define RCC_APB1RSTR1_TIM7RST RCC_APB1RSTR1_TIM7RST_Msk
9665#define RCC_APB1RSTR1_SPI2RST_Pos (14U)
9666#define RCC_APB1RSTR1_SPI2RST_Msk (0x1UL << RCC_APB1RSTR1_SPI2RST_Pos)
9667#define RCC_APB1RSTR1_SPI2RST RCC_APB1RSTR1_SPI2RST_Msk
9668#define RCC_APB1RSTR1_SPI3RST_Pos (15U)
9669#define RCC_APB1RSTR1_SPI3RST_Msk (0x1UL << RCC_APB1RSTR1_SPI3RST_Pos)
9670#define RCC_APB1RSTR1_SPI3RST RCC_APB1RSTR1_SPI3RST_Msk
9671#define RCC_APB1RSTR1_USART2RST_Pos (17U)
9672#define RCC_APB1RSTR1_USART2RST_Msk (0x1UL << RCC_APB1RSTR1_USART2RST_Pos)
9673#define RCC_APB1RSTR1_USART2RST RCC_APB1RSTR1_USART2RST_Msk
9674#define RCC_APB1RSTR1_USART3RST_Pos (18U)
9675#define RCC_APB1RSTR1_USART3RST_Msk (0x1UL << RCC_APB1RSTR1_USART3RST_Pos)
9676#define RCC_APB1RSTR1_USART3RST RCC_APB1RSTR1_USART3RST_Msk
9677#define RCC_APB1RSTR1_I2C1RST_Pos (21U)
9678#define RCC_APB1RSTR1_I2C1RST_Msk (0x1UL << RCC_APB1RSTR1_I2C1RST_Pos)
9679#define RCC_APB1RSTR1_I2C1RST RCC_APB1RSTR1_I2C1RST_Msk
9680#define RCC_APB1RSTR1_I2C2RST_Pos (22U)
9681#define RCC_APB1RSTR1_I2C2RST_Msk (0x1UL << RCC_APB1RSTR1_I2C2RST_Pos)
9682#define RCC_APB1RSTR1_I2C2RST RCC_APB1RSTR1_I2C2RST_Msk
9683#define RCC_APB1RSTR1_I2C3RST_Pos (23U)
9684#define RCC_APB1RSTR1_I2C3RST_Msk (0x1UL << RCC_APB1RSTR1_I2C3RST_Pos)
9685#define RCC_APB1RSTR1_I2C3RST RCC_APB1RSTR1_I2C3RST_Msk
9686#define RCC_APB1RSTR1_CRSRST_Pos (24U)
9687#define RCC_APB1RSTR1_CRSRST_Msk (0x1UL << RCC_APB1RSTR1_CRSRST_Pos)
9688#define RCC_APB1RSTR1_CRSRST RCC_APB1RSTR1_CRSRST_Msk
9689#define RCC_APB1RSTR1_CAN1RST_Pos (25U)
9690#define RCC_APB1RSTR1_CAN1RST_Msk (0x1UL << RCC_APB1RSTR1_CAN1RST_Pos)
9691#define RCC_APB1RSTR1_CAN1RST RCC_APB1RSTR1_CAN1RST_Msk
9692#define RCC_APB1RSTR1_PWRRST_Pos (28U)
9693#define RCC_APB1RSTR1_PWRRST_Msk (0x1UL << RCC_APB1RSTR1_PWRRST_Pos)
9694#define RCC_APB1RSTR1_PWRRST RCC_APB1RSTR1_PWRRST_Msk
9695#define RCC_APB1RSTR1_DAC1RST_Pos (29U)
9696#define RCC_APB1RSTR1_DAC1RST_Msk (0x1UL << RCC_APB1RSTR1_DAC1RST_Pos)
9697#define RCC_APB1RSTR1_DAC1RST RCC_APB1RSTR1_DAC1RST_Msk
9698#define RCC_APB1RSTR1_OPAMPRST_Pos (30U)
9699#define RCC_APB1RSTR1_OPAMPRST_Msk (0x1UL << RCC_APB1RSTR1_OPAMPRST_Pos)
9700#define RCC_APB1RSTR1_OPAMPRST RCC_APB1RSTR1_OPAMPRST_Msk
9701#define RCC_APB1RSTR1_LPTIM1RST_Pos (31U)
9702#define RCC_APB1RSTR1_LPTIM1RST_Msk (0x1UL << RCC_APB1RSTR1_LPTIM1RST_Pos)
9703#define RCC_APB1RSTR1_LPTIM1RST RCC_APB1RSTR1_LPTIM1RST_Msk
9704
9705/******************** Bit definition for RCC_APB1RSTR2 register **************/
9706#define RCC_APB1RSTR2_LPUART1RST_Pos (0U)
9707#define RCC_APB1RSTR2_LPUART1RST_Msk (0x1UL << RCC_APB1RSTR2_LPUART1RST_Pos)
9708#define RCC_APB1RSTR2_LPUART1RST RCC_APB1RSTR2_LPUART1RST_Msk
9709#define RCC_APB1RSTR2_SWPMI1RST_Pos (2U)
9710#define RCC_APB1RSTR2_SWPMI1RST_Msk (0x1UL << RCC_APB1RSTR2_SWPMI1RST_Pos)
9711#define RCC_APB1RSTR2_SWPMI1RST RCC_APB1RSTR2_SWPMI1RST_Msk
9712#define RCC_APB1RSTR2_LPTIM2RST_Pos (5U)
9713#define RCC_APB1RSTR2_LPTIM2RST_Msk (0x1UL << RCC_APB1RSTR2_LPTIM2RST_Pos)
9714#define RCC_APB1RSTR2_LPTIM2RST RCC_APB1RSTR2_LPTIM2RST_Msk
9715
9716/******************** Bit definition for RCC_APB2RSTR register **************/
9717#define RCC_APB2RSTR_SYSCFGRST_Pos (0U)
9718#define RCC_APB2RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos)
9719#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk
9720#define RCC_APB2RSTR_SDMMC1RST_Pos (10U)
9721#define RCC_APB2RSTR_SDMMC1RST_Msk (0x1UL << RCC_APB2RSTR_SDMMC1RST_Pos)
9722#define RCC_APB2RSTR_SDMMC1RST RCC_APB2RSTR_SDMMC1RST_Msk
9723#define RCC_APB2RSTR_TIM1RST_Pos (11U)
9724#define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)
9725#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
9726#define RCC_APB2RSTR_SPI1RST_Pos (12U)
9727#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)
9728#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
9729#define RCC_APB2RSTR_USART1RST_Pos (14U)
9730#define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos)
9731#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
9732#define RCC_APB2RSTR_TIM15RST_Pos (16U)
9733#define RCC_APB2RSTR_TIM15RST_Msk (0x1UL << RCC_APB2RSTR_TIM15RST_Pos)
9734#define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk
9735#define RCC_APB2RSTR_TIM16RST_Pos (17U)
9736#define RCC_APB2RSTR_TIM16RST_Msk (0x1UL << RCC_APB2RSTR_TIM16RST_Pos)
9737#define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk
9738#define RCC_APB2RSTR_SAI1RST_Pos (21U)
9739#define RCC_APB2RSTR_SAI1RST_Msk (0x1UL << RCC_APB2RSTR_SAI1RST_Pos)
9740#define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk
9741
9742/******************** Bit definition for RCC_AHB1ENR register ***************/
9743#define RCC_AHB1ENR_DMA1EN_Pos (0U)
9744#define RCC_AHB1ENR_DMA1EN_Msk (0x1UL << RCC_AHB1ENR_DMA1EN_Pos)
9745#define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
9746#define RCC_AHB1ENR_DMA2EN_Pos (1U)
9747#define RCC_AHB1ENR_DMA2EN_Msk (0x1UL << RCC_AHB1ENR_DMA2EN_Pos)
9748#define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
9749#define RCC_AHB1ENR_FLASHEN_Pos (8U)
9750#define RCC_AHB1ENR_FLASHEN_Msk (0x1UL << RCC_AHB1ENR_FLASHEN_Pos)
9751#define RCC_AHB1ENR_FLASHEN RCC_AHB1ENR_FLASHEN_Msk
9752#define RCC_AHB1ENR_CRCEN_Pos (12U)
9753#define RCC_AHB1ENR_CRCEN_Msk (0x1UL << RCC_AHB1ENR_CRCEN_Pos)
9754#define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk
9755#define RCC_AHB1ENR_TSCEN_Pos (16U)
9756#define RCC_AHB1ENR_TSCEN_Msk (0x1UL << RCC_AHB1ENR_TSCEN_Pos)
9757#define RCC_AHB1ENR_TSCEN RCC_AHB1ENR_TSCEN_Msk
9758
9759/******************** Bit definition for RCC_AHB2ENR register ***************/
9760#define RCC_AHB2ENR_GPIOAEN_Pos (0U)
9761#define RCC_AHB2ENR_GPIOAEN_Msk (0x1UL << RCC_AHB2ENR_GPIOAEN_Pos)
9762#define RCC_AHB2ENR_GPIOAEN RCC_AHB2ENR_GPIOAEN_Msk
9763#define RCC_AHB2ENR_GPIOBEN_Pos (1U)
9764#define RCC_AHB2ENR_GPIOBEN_Msk (0x1UL << RCC_AHB2ENR_GPIOBEN_Pos)
9765#define RCC_AHB2ENR_GPIOBEN RCC_AHB2ENR_GPIOBEN_Msk
9766#define RCC_AHB2ENR_GPIOCEN_Pos (2U)
9767#define RCC_AHB2ENR_GPIOCEN_Msk (0x1UL << RCC_AHB2ENR_GPIOCEN_Pos)
9768#define RCC_AHB2ENR_GPIOCEN RCC_AHB2ENR_GPIOCEN_Msk
9769#define RCC_AHB2ENR_GPIODEN_Pos (3U)
9770#define RCC_AHB2ENR_GPIODEN_Msk (0x1UL << RCC_AHB2ENR_GPIODEN_Pos)
9771#define RCC_AHB2ENR_GPIODEN RCC_AHB2ENR_GPIODEN_Msk
9772#define RCC_AHB2ENR_GPIOEEN_Pos (4U)
9773#define RCC_AHB2ENR_GPIOEEN_Msk (0x1UL << RCC_AHB2ENR_GPIOEEN_Pos)
9774#define RCC_AHB2ENR_GPIOEEN RCC_AHB2ENR_GPIOEEN_Msk
9775#define RCC_AHB2ENR_GPIOHEN_Pos (7U)
9776#define RCC_AHB2ENR_GPIOHEN_Msk (0x1UL << RCC_AHB2ENR_GPIOHEN_Pos)
9777#define RCC_AHB2ENR_GPIOHEN RCC_AHB2ENR_GPIOHEN_Msk
9778#define RCC_AHB2ENR_ADCEN_Pos (13U)
9779#define RCC_AHB2ENR_ADCEN_Msk (0x1UL << RCC_AHB2ENR_ADCEN_Pos)
9780#define RCC_AHB2ENR_ADCEN RCC_AHB2ENR_ADCEN_Msk
9781#define RCC_AHB2ENR_RNGEN_Pos (18U)
9782#define RCC_AHB2ENR_RNGEN_Msk (0x1UL << RCC_AHB2ENR_RNGEN_Pos)
9783#define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
9784
9785/******************** Bit definition for RCC_AHB3ENR register ***************/
9786#define RCC_AHB3ENR_QSPIEN_Pos (8U)
9787#define RCC_AHB3ENR_QSPIEN_Msk (0x1UL << RCC_AHB3ENR_QSPIEN_Pos)
9788#define RCC_AHB3ENR_QSPIEN RCC_AHB3ENR_QSPIEN_Msk
9789
9790/******************** Bit definition for RCC_APB1ENR1 register ***************/
9791#define RCC_APB1ENR1_TIM2EN_Pos (0U)
9792#define RCC_APB1ENR1_TIM2EN_Msk (0x1UL << RCC_APB1ENR1_TIM2EN_Pos)
9793#define RCC_APB1ENR1_TIM2EN RCC_APB1ENR1_TIM2EN_Msk
9794#define RCC_APB1ENR1_TIM6EN_Pos (4U)
9795#define RCC_APB1ENR1_TIM6EN_Msk (0x1UL << RCC_APB1ENR1_TIM6EN_Pos)
9796#define RCC_APB1ENR1_TIM6EN RCC_APB1ENR1_TIM6EN_Msk
9797#define RCC_APB1ENR1_TIM7EN_Pos (5U)
9798#define RCC_APB1ENR1_TIM7EN_Msk (0x1UL << RCC_APB1ENR1_TIM7EN_Pos)
9799#define RCC_APB1ENR1_TIM7EN RCC_APB1ENR1_TIM7EN_Msk
9800#define RCC_APB1ENR1_RTCAPBEN_Pos (10U)
9801#define RCC_APB1ENR1_RTCAPBEN_Msk (0x1UL << RCC_APB1ENR1_RTCAPBEN_Pos)
9802#define RCC_APB1ENR1_RTCAPBEN RCC_APB1ENR1_RTCAPBEN_Msk
9803#define RCC_APB1ENR1_WWDGEN_Pos (11U)
9804#define RCC_APB1ENR1_WWDGEN_Msk (0x1UL << RCC_APB1ENR1_WWDGEN_Pos)
9805#define RCC_APB1ENR1_WWDGEN RCC_APB1ENR1_WWDGEN_Msk
9806#define RCC_APB1ENR1_SPI2EN_Pos (14U)
9807#define RCC_APB1ENR1_SPI2EN_Msk (0x1UL << RCC_APB1ENR1_SPI2EN_Pos)
9808#define RCC_APB1ENR1_SPI2EN RCC_APB1ENR1_SPI2EN_Msk
9809#define RCC_APB1ENR1_SPI3EN_Pos (15U)
9810#define RCC_APB1ENR1_SPI3EN_Msk (0x1UL << RCC_APB1ENR1_SPI3EN_Pos)
9811#define RCC_APB1ENR1_SPI3EN RCC_APB1ENR1_SPI3EN_Msk
9812#define RCC_APB1ENR1_USART2EN_Pos (17U)
9813#define RCC_APB1ENR1_USART2EN_Msk (0x1UL << RCC_APB1ENR1_USART2EN_Pos)
9814#define RCC_APB1ENR1_USART2EN RCC_APB1ENR1_USART2EN_Msk
9815#define RCC_APB1ENR1_USART3EN_Pos (18U)
9816#define RCC_APB1ENR1_USART3EN_Msk (0x1UL << RCC_APB1ENR1_USART3EN_Pos)
9817#define RCC_APB1ENR1_USART3EN RCC_APB1ENR1_USART3EN_Msk
9818#define RCC_APB1ENR1_I2C1EN_Pos (21U)
9819#define RCC_APB1ENR1_I2C1EN_Msk (0x1UL << RCC_APB1ENR1_I2C1EN_Pos)
9820#define RCC_APB1ENR1_I2C1EN RCC_APB1ENR1_I2C1EN_Msk
9821#define RCC_APB1ENR1_I2C2EN_Pos (22U)
9822#define RCC_APB1ENR1_I2C2EN_Msk (0x1UL << RCC_APB1ENR1_I2C2EN_Pos)
9823#define RCC_APB1ENR1_I2C2EN RCC_APB1ENR1_I2C2EN_Msk
9824#define RCC_APB1ENR1_I2C3EN_Pos (23U)
9825#define RCC_APB1ENR1_I2C3EN_Msk (0x1UL << RCC_APB1ENR1_I2C3EN_Pos)
9826#define RCC_APB1ENR1_I2C3EN RCC_APB1ENR1_I2C3EN_Msk
9827#define RCC_APB1ENR1_CRSEN_Pos (24U)
9828#define RCC_APB1ENR1_CRSEN_Msk (0x1UL << RCC_APB1ENR1_CRSEN_Pos)
9829#define RCC_APB1ENR1_CRSEN RCC_APB1ENR1_CRSEN_Msk
9830#define RCC_APB1ENR1_CAN1EN_Pos (25U)
9831#define RCC_APB1ENR1_CAN1EN_Msk (0x1UL << RCC_APB1ENR1_CAN1EN_Pos)
9832#define RCC_APB1ENR1_CAN1EN RCC_APB1ENR1_CAN1EN_Msk
9833#define RCC_APB1ENR1_PWREN_Pos (28U)
9834#define RCC_APB1ENR1_PWREN_Msk (0x1UL << RCC_APB1ENR1_PWREN_Pos)
9835#define RCC_APB1ENR1_PWREN RCC_APB1ENR1_PWREN_Msk
9836#define RCC_APB1ENR1_DAC1EN_Pos (29U)
9837#define RCC_APB1ENR1_DAC1EN_Msk (0x1UL << RCC_APB1ENR1_DAC1EN_Pos)
9838#define RCC_APB1ENR1_DAC1EN RCC_APB1ENR1_DAC1EN_Msk
9839#define RCC_APB1ENR1_OPAMPEN_Pos (30U)
9840#define RCC_APB1ENR1_OPAMPEN_Msk (0x1UL << RCC_APB1ENR1_OPAMPEN_Pos)
9841#define RCC_APB1ENR1_OPAMPEN RCC_APB1ENR1_OPAMPEN_Msk
9842#define RCC_APB1ENR1_LPTIM1EN_Pos (31U)
9843#define RCC_APB1ENR1_LPTIM1EN_Msk (0x1UL << RCC_APB1ENR1_LPTIM1EN_Pos)
9844#define RCC_APB1ENR1_LPTIM1EN RCC_APB1ENR1_LPTIM1EN_Msk
9845
9846/******************** Bit definition for RCC_APB1RSTR2 register **************/
9847#define RCC_APB1ENR2_LPUART1EN_Pos (0U)
9848#define RCC_APB1ENR2_LPUART1EN_Msk (0x1UL << RCC_APB1ENR2_LPUART1EN_Pos)
9849#define RCC_APB1ENR2_LPUART1EN RCC_APB1ENR2_LPUART1EN_Msk
9850#define RCC_APB1ENR2_SWPMI1EN_Pos (2U)
9851#define RCC_APB1ENR2_SWPMI1EN_Msk (0x1UL << RCC_APB1ENR2_SWPMI1EN_Pos)
9852#define RCC_APB1ENR2_SWPMI1EN RCC_APB1ENR2_SWPMI1EN_Msk
9853#define RCC_APB1ENR2_LPTIM2EN_Pos (5U)
9854#define RCC_APB1ENR2_LPTIM2EN_Msk (0x1UL << RCC_APB1ENR2_LPTIM2EN_Pos)
9855#define RCC_APB1ENR2_LPTIM2EN RCC_APB1ENR2_LPTIM2EN_Msk
9856
9857/******************** Bit definition for RCC_APB2ENR register ***************/
9858#define RCC_APB2ENR_SYSCFGEN_Pos (0U)
9859#define RCC_APB2ENR_SYSCFGEN_Msk (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos)
9860#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk
9861#define RCC_APB2ENR_FWEN_Pos (7U)
9862#define RCC_APB2ENR_FWEN_Msk (0x1UL << RCC_APB2ENR_FWEN_Pos)
9863#define RCC_APB2ENR_FWEN RCC_APB2ENR_FWEN_Msk
9864#define RCC_APB2ENR_SDMMC1EN_Pos (10U)
9865#define RCC_APB2ENR_SDMMC1EN_Msk (0x1UL << RCC_APB2ENR_SDMMC1EN_Pos)
9866#define RCC_APB2ENR_SDMMC1EN RCC_APB2ENR_SDMMC1EN_Msk
9867#define RCC_APB2ENR_TIM1EN_Pos (11U)
9868#define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos)
9869#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
9870#define RCC_APB2ENR_SPI1EN_Pos (12U)
9871#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos)
9872#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
9873#define RCC_APB2ENR_USART1EN_Pos (14U)
9874#define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos)
9875#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
9876#define RCC_APB2ENR_TIM15EN_Pos (16U)
9877#define RCC_APB2ENR_TIM15EN_Msk (0x1UL << RCC_APB2ENR_TIM15EN_Pos)
9878#define RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk
9879#define RCC_APB2ENR_TIM16EN_Pos (17U)
9880#define RCC_APB2ENR_TIM16EN_Msk (0x1UL << RCC_APB2ENR_TIM16EN_Pos)
9881#define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk
9882#define RCC_APB2ENR_SAI1EN_Pos (21U)
9883#define RCC_APB2ENR_SAI1EN_Msk (0x1UL << RCC_APB2ENR_SAI1EN_Pos)
9884#define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk
9885
9886/******************** Bit definition for RCC_AHB1SMENR register ***************/
9887#define RCC_AHB1SMENR_DMA1SMEN_Pos (0U)
9888#define RCC_AHB1SMENR_DMA1SMEN_Msk (0x1UL << RCC_AHB1SMENR_DMA1SMEN_Pos)
9889#define RCC_AHB1SMENR_DMA1SMEN RCC_AHB1SMENR_DMA1SMEN_Msk
9890#define RCC_AHB1SMENR_DMA2SMEN_Pos (1U)
9891#define RCC_AHB1SMENR_DMA2SMEN_Msk (0x1UL << RCC_AHB1SMENR_DMA2SMEN_Pos)
9892#define RCC_AHB1SMENR_DMA2SMEN RCC_AHB1SMENR_DMA2SMEN_Msk
9893#define RCC_AHB1SMENR_FLASHSMEN_Pos (8U)
9894#define RCC_AHB1SMENR_FLASHSMEN_Msk (0x1UL << RCC_AHB1SMENR_FLASHSMEN_Pos)
9895#define RCC_AHB1SMENR_FLASHSMEN RCC_AHB1SMENR_FLASHSMEN_Msk
9896#define RCC_AHB1SMENR_SRAM1SMEN_Pos (9U)
9897#define RCC_AHB1SMENR_SRAM1SMEN_Msk (0x1UL << RCC_AHB1SMENR_SRAM1SMEN_Pos)
9898#define RCC_AHB1SMENR_SRAM1SMEN RCC_AHB1SMENR_SRAM1SMEN_Msk
9899#define RCC_AHB1SMENR_CRCSMEN_Pos (12U)
9900#define RCC_AHB1SMENR_CRCSMEN_Msk (0x1UL << RCC_AHB1SMENR_CRCSMEN_Pos)
9901#define RCC_AHB1SMENR_CRCSMEN RCC_AHB1SMENR_CRCSMEN_Msk
9902#define RCC_AHB1SMENR_TSCSMEN_Pos (16U)
9903#define RCC_AHB1SMENR_TSCSMEN_Msk (0x1UL << RCC_AHB1SMENR_TSCSMEN_Pos)
9904#define RCC_AHB1SMENR_TSCSMEN RCC_AHB1SMENR_TSCSMEN_Msk
9905
9906/******************** Bit definition for RCC_AHB2SMENR register *************/
9907#define RCC_AHB2SMENR_GPIOASMEN_Pos (0U)
9908#define RCC_AHB2SMENR_GPIOASMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOASMEN_Pos)
9909#define RCC_AHB2SMENR_GPIOASMEN RCC_AHB2SMENR_GPIOASMEN_Msk
9910#define RCC_AHB2SMENR_GPIOBSMEN_Pos (1U)
9911#define RCC_AHB2SMENR_GPIOBSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOBSMEN_Pos)
9912#define RCC_AHB2SMENR_GPIOBSMEN RCC_AHB2SMENR_GPIOBSMEN_Msk
9913#define RCC_AHB2SMENR_GPIOCSMEN_Pos (2U)
9914#define RCC_AHB2SMENR_GPIOCSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOCSMEN_Pos)
9915#define RCC_AHB2SMENR_GPIOCSMEN RCC_AHB2SMENR_GPIOCSMEN_Msk
9916#define RCC_AHB2SMENR_GPIODSMEN_Pos (3U)
9917#define RCC_AHB2SMENR_GPIODSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIODSMEN_Pos)
9918#define RCC_AHB2SMENR_GPIODSMEN RCC_AHB2SMENR_GPIODSMEN_Msk
9919#define RCC_AHB2SMENR_GPIOESMEN_Pos (4U)
9920#define RCC_AHB2SMENR_GPIOESMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOESMEN_Pos)
9921#define RCC_AHB2SMENR_GPIOESMEN RCC_AHB2SMENR_GPIOESMEN_Msk
9922#define RCC_AHB2SMENR_GPIOHSMEN_Pos (7U)
9923#define RCC_AHB2SMENR_GPIOHSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOHSMEN_Pos)
9924#define RCC_AHB2SMENR_GPIOHSMEN RCC_AHB2SMENR_GPIOHSMEN_Msk
9925#define RCC_AHB2SMENR_SRAM2SMEN_Pos (9U)
9926#define RCC_AHB2SMENR_SRAM2SMEN_Msk (0x1UL << RCC_AHB2SMENR_SRAM2SMEN_Pos)
9927#define RCC_AHB2SMENR_SRAM2SMEN RCC_AHB2SMENR_SRAM2SMEN_Msk
9928#define RCC_AHB2SMENR_ADCSMEN_Pos (13U)
9929#define RCC_AHB2SMENR_ADCSMEN_Msk (0x1UL << RCC_AHB2SMENR_ADCSMEN_Pos)
9930#define RCC_AHB2SMENR_ADCSMEN RCC_AHB2SMENR_ADCSMEN_Msk
9931#define RCC_AHB2SMENR_RNGSMEN_Pos (18U)
9932#define RCC_AHB2SMENR_RNGSMEN_Msk (0x1UL << RCC_AHB2SMENR_RNGSMEN_Pos)
9933#define RCC_AHB2SMENR_RNGSMEN RCC_AHB2SMENR_RNGSMEN_Msk
9934
9935/******************** Bit definition for RCC_AHB3SMENR register *************/
9936#define RCC_AHB3SMENR_QSPISMEN_Pos (8U)
9937#define RCC_AHB3SMENR_QSPISMEN_Msk (0x1UL << RCC_AHB3SMENR_QSPISMEN_Pos)
9938#define RCC_AHB3SMENR_QSPISMEN RCC_AHB3SMENR_QSPISMEN_Msk
9939
9940/******************** Bit definition for RCC_APB1SMENR1 register *************/
9941#define RCC_APB1SMENR1_TIM2SMEN_Pos (0U)
9942#define RCC_APB1SMENR1_TIM2SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM2SMEN_Pos)
9943#define RCC_APB1SMENR1_TIM2SMEN RCC_APB1SMENR1_TIM2SMEN_Msk
9944#define RCC_APB1SMENR1_TIM6SMEN_Pos (4U)
9945#define RCC_APB1SMENR1_TIM6SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM6SMEN_Pos)
9946#define RCC_APB1SMENR1_TIM6SMEN RCC_APB1SMENR1_TIM6SMEN_Msk
9947#define RCC_APB1SMENR1_TIM7SMEN_Pos (5U)
9948#define RCC_APB1SMENR1_TIM7SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM7SMEN_Pos)
9949#define RCC_APB1SMENR1_TIM7SMEN RCC_APB1SMENR1_TIM7SMEN_Msk
9950#define RCC_APB1SMENR1_RTCAPBSMEN_Pos (10U)
9951#define RCC_APB1SMENR1_RTCAPBSMEN_Msk (0x1UL << RCC_APB1SMENR1_RTCAPBSMEN_Pos)
9952#define RCC_APB1SMENR1_RTCAPBSMEN RCC_APB1SMENR1_RTCAPBSMEN_Msk
9953#define RCC_APB1SMENR1_WWDGSMEN_Pos (11U)
9954#define RCC_APB1SMENR1_WWDGSMEN_Msk (0x1UL << RCC_APB1SMENR1_WWDGSMEN_Pos)
9955#define RCC_APB1SMENR1_WWDGSMEN RCC_APB1SMENR1_WWDGSMEN_Msk
9956#define RCC_APB1SMENR1_SPI2SMEN_Pos (14U)
9957#define RCC_APB1SMENR1_SPI2SMEN_Msk (0x1UL << RCC_APB1SMENR1_SPI2SMEN_Pos)
9958#define RCC_APB1SMENR1_SPI2SMEN RCC_APB1SMENR1_SPI2SMEN_Msk
9959#define RCC_APB1SMENR1_SPI3SMEN_Pos (15U)
9960#define RCC_APB1SMENR1_SPI3SMEN_Msk (0x1UL << RCC_APB1SMENR1_SPI3SMEN_Pos)
9961#define RCC_APB1SMENR1_SPI3SMEN RCC_APB1SMENR1_SPI3SMEN_Msk
9962#define RCC_APB1SMENR1_USART2SMEN_Pos (17U)
9963#define RCC_APB1SMENR1_USART2SMEN_Msk (0x1UL << RCC_APB1SMENR1_USART2SMEN_Pos)
9964#define RCC_APB1SMENR1_USART2SMEN RCC_APB1SMENR1_USART2SMEN_Msk
9965#define RCC_APB1SMENR1_USART3SMEN_Pos (18U)
9966#define RCC_APB1SMENR1_USART3SMEN_Msk (0x1UL << RCC_APB1SMENR1_USART3SMEN_Pos)
9967#define RCC_APB1SMENR1_USART3SMEN RCC_APB1SMENR1_USART3SMEN_Msk
9968#define RCC_APB1SMENR1_I2C1SMEN_Pos (21U)
9969#define RCC_APB1SMENR1_I2C1SMEN_Msk (0x1UL << RCC_APB1SMENR1_I2C1SMEN_Pos)
9970#define RCC_APB1SMENR1_I2C1SMEN RCC_APB1SMENR1_I2C1SMEN_Msk
9971#define RCC_APB1SMENR1_I2C2SMEN_Pos (22U)
9972#define RCC_APB1SMENR1_I2C2SMEN_Msk (0x1UL << RCC_APB1SMENR1_I2C2SMEN_Pos)
9973#define RCC_APB1SMENR1_I2C2SMEN RCC_APB1SMENR1_I2C2SMEN_Msk
9974#define RCC_APB1SMENR1_I2C3SMEN_Pos (23U)
9975#define RCC_APB1SMENR1_I2C3SMEN_Msk (0x1UL << RCC_APB1SMENR1_I2C3SMEN_Pos)
9976#define RCC_APB1SMENR1_I2C3SMEN RCC_APB1SMENR1_I2C3SMEN_Msk
9977#define RCC_APB1SMENR1_CRSSMEN_Pos (24U)
9978#define RCC_APB1SMENR1_CRSSMEN_Msk (0x1UL << RCC_APB1SMENR1_CRSSMEN_Pos)
9979#define RCC_APB1SMENR1_CRSSMEN RCC_APB1SMENR1_CRSSMEN_Msk
9980#define RCC_APB1SMENR1_CAN1SMEN_Pos (25U)
9981#define RCC_APB1SMENR1_CAN1SMEN_Msk (0x1UL << RCC_APB1SMENR1_CAN1SMEN_Pos)
9982#define RCC_APB1SMENR1_CAN1SMEN RCC_APB1SMENR1_CAN1SMEN_Msk
9983#define RCC_APB1SMENR1_PWRSMEN_Pos (28U)
9984#define RCC_APB1SMENR1_PWRSMEN_Msk (0x1UL << RCC_APB1SMENR1_PWRSMEN_Pos)
9985#define RCC_APB1SMENR1_PWRSMEN RCC_APB1SMENR1_PWRSMEN_Msk
9986#define RCC_APB1SMENR1_DAC1SMEN_Pos (29U)
9987#define RCC_APB1SMENR1_DAC1SMEN_Msk (0x1UL << RCC_APB1SMENR1_DAC1SMEN_Pos)
9988#define RCC_APB1SMENR1_DAC1SMEN RCC_APB1SMENR1_DAC1SMEN_Msk
9989#define RCC_APB1SMENR1_OPAMPSMEN_Pos (30U)
9990#define RCC_APB1SMENR1_OPAMPSMEN_Msk (0x1UL << RCC_APB1SMENR1_OPAMPSMEN_Pos)
9991#define RCC_APB1SMENR1_OPAMPSMEN RCC_APB1SMENR1_OPAMPSMEN_Msk
9992#define RCC_APB1SMENR1_LPTIM1SMEN_Pos (31U)
9993#define RCC_APB1SMENR1_LPTIM1SMEN_Msk (0x1UL << RCC_APB1SMENR1_LPTIM1SMEN_Pos)
9994#define RCC_APB1SMENR1_LPTIM1SMEN RCC_APB1SMENR1_LPTIM1SMEN_Msk
9995
9996/******************** Bit definition for RCC_APB1SMENR2 register *************/
9997#define RCC_APB1SMENR2_LPUART1SMEN_Pos (0U)
9998#define RCC_APB1SMENR2_LPUART1SMEN_Msk (0x1UL << RCC_APB1SMENR2_LPUART1SMEN_Pos)
9999#define RCC_APB1SMENR2_LPUART1SMEN RCC_APB1SMENR2_LPUART1SMEN_Msk
10000#define RCC_APB1SMENR2_SWPMI1SMEN_Pos (2U)
10001#define RCC_APB1SMENR2_SWPMI1SMEN_Msk (0x1UL << RCC_APB1SMENR2_SWPMI1SMEN_Pos)
10002#define RCC_APB1SMENR2_SWPMI1SMEN RCC_APB1SMENR2_SWPMI1SMEN_Msk
10003#define RCC_APB1SMENR2_LPTIM2SMEN_Pos (5U)
10004#define RCC_APB1SMENR2_LPTIM2SMEN_Msk (0x1UL << RCC_APB1SMENR2_LPTIM2SMEN_Pos)
10005#define RCC_APB1SMENR2_LPTIM2SMEN RCC_APB1SMENR2_LPTIM2SMEN_Msk
10006
10007/******************** Bit definition for RCC_APB2SMENR register *************/
10008#define RCC_APB2SMENR_SYSCFGSMEN_Pos (0U)
10009#define RCC_APB2SMENR_SYSCFGSMEN_Msk (0x1UL << RCC_APB2SMENR_SYSCFGSMEN_Pos)
10010#define RCC_APB2SMENR_SYSCFGSMEN RCC_APB2SMENR_SYSCFGSMEN_Msk
10011#define RCC_APB2SMENR_SDMMC1SMEN_Pos (10U)
10012#define RCC_APB2SMENR_SDMMC1SMEN_Msk (0x1UL << RCC_APB2SMENR_SDMMC1SMEN_Pos)
10013#define RCC_APB2SMENR_SDMMC1SMEN RCC_APB2SMENR_SDMMC1SMEN_Msk
10014#define RCC_APB2SMENR_TIM1SMEN_Pos (11U)
10015#define RCC_APB2SMENR_TIM1SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM1SMEN_Pos)
10016#define RCC_APB2SMENR_TIM1SMEN RCC_APB2SMENR_TIM1SMEN_Msk
10017#define RCC_APB2SMENR_SPI1SMEN_Pos (12U)
10018#define RCC_APB2SMENR_SPI1SMEN_Msk (0x1UL << RCC_APB2SMENR_SPI1SMEN_Pos)
10019#define RCC_APB2SMENR_SPI1SMEN RCC_APB2SMENR_SPI1SMEN_Msk
10020#define RCC_APB2SMENR_USART1SMEN_Pos (14U)
10021#define RCC_APB2SMENR_USART1SMEN_Msk (0x1UL << RCC_APB2SMENR_USART1SMEN_Pos)
10022#define RCC_APB2SMENR_USART1SMEN RCC_APB2SMENR_USART1SMEN_Msk
10023#define RCC_APB2SMENR_TIM15SMEN_Pos (16U)
10024#define RCC_APB2SMENR_TIM15SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM15SMEN_Pos)
10025#define RCC_APB2SMENR_TIM15SMEN RCC_APB2SMENR_TIM15SMEN_Msk
10026#define RCC_APB2SMENR_TIM16SMEN_Pos (17U)
10027#define RCC_APB2SMENR_TIM16SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM16SMEN_Pos)
10028#define RCC_APB2SMENR_TIM16SMEN RCC_APB2SMENR_TIM16SMEN_Msk
10029#define RCC_APB2SMENR_SAI1SMEN_Pos (21U)
10030#define RCC_APB2SMENR_SAI1SMEN_Msk (0x1UL << RCC_APB2SMENR_SAI1SMEN_Pos)
10031#define RCC_APB2SMENR_SAI1SMEN RCC_APB2SMENR_SAI1SMEN_Msk
10032
10033/******************** Bit definition for RCC_CCIPR register ******************/
10034#define RCC_CCIPR_USART1SEL_Pos (0U)
10035#define RCC_CCIPR_USART1SEL_Msk (0x3UL << RCC_CCIPR_USART1SEL_Pos)
10036#define RCC_CCIPR_USART1SEL RCC_CCIPR_USART1SEL_Msk
10037#define RCC_CCIPR_USART1SEL_0 (0x1UL << RCC_CCIPR_USART1SEL_Pos)
10038#define RCC_CCIPR_USART1SEL_1 (0x2UL << RCC_CCIPR_USART1SEL_Pos)
10040#define RCC_CCIPR_USART2SEL_Pos (2U)
10041#define RCC_CCIPR_USART2SEL_Msk (0x3UL << RCC_CCIPR_USART2SEL_Pos)
10042#define RCC_CCIPR_USART2SEL RCC_CCIPR_USART2SEL_Msk
10043#define RCC_CCIPR_USART2SEL_0 (0x1UL << RCC_CCIPR_USART2SEL_Pos)
10044#define RCC_CCIPR_USART2SEL_1 (0x2UL << RCC_CCIPR_USART2SEL_Pos)
10046#define RCC_CCIPR_USART3SEL_Pos (4U)
10047#define RCC_CCIPR_USART3SEL_Msk (0x3UL << RCC_CCIPR_USART3SEL_Pos)
10048#define RCC_CCIPR_USART3SEL RCC_CCIPR_USART3SEL_Msk
10049#define RCC_CCIPR_USART3SEL_0 (0x1UL << RCC_CCIPR_USART3SEL_Pos)
10050#define RCC_CCIPR_USART3SEL_1 (0x2UL << RCC_CCIPR_USART3SEL_Pos)
10052#define RCC_CCIPR_LPUART1SEL_Pos (10U)
10053#define RCC_CCIPR_LPUART1SEL_Msk (0x3UL << RCC_CCIPR_LPUART1SEL_Pos)
10054#define RCC_CCIPR_LPUART1SEL RCC_CCIPR_LPUART1SEL_Msk
10055#define RCC_CCIPR_LPUART1SEL_0 (0x1UL << RCC_CCIPR_LPUART1SEL_Pos)
10056#define RCC_CCIPR_LPUART1SEL_1 (0x2UL << RCC_CCIPR_LPUART1SEL_Pos)
10058#define RCC_CCIPR_I2C1SEL_Pos (12U)
10059#define RCC_CCIPR_I2C1SEL_Msk (0x3UL << RCC_CCIPR_I2C1SEL_Pos)
10060#define RCC_CCIPR_I2C1SEL RCC_CCIPR_I2C1SEL_Msk
10061#define RCC_CCIPR_I2C1SEL_0 (0x1UL << RCC_CCIPR_I2C1SEL_Pos)
10062#define RCC_CCIPR_I2C1SEL_1 (0x2UL << RCC_CCIPR_I2C1SEL_Pos)
10064#define RCC_CCIPR_I2C2SEL_Pos (14U)
10065#define RCC_CCIPR_I2C2SEL_Msk (0x3UL << RCC_CCIPR_I2C2SEL_Pos)
10066#define RCC_CCIPR_I2C2SEL RCC_CCIPR_I2C2SEL_Msk
10067#define RCC_CCIPR_I2C2SEL_0 (0x1UL << RCC_CCIPR_I2C2SEL_Pos)
10068#define RCC_CCIPR_I2C2SEL_1 (0x2UL << RCC_CCIPR_I2C2SEL_Pos)
10070#define RCC_CCIPR_I2C3SEL_Pos (16U)
10071#define RCC_CCIPR_I2C3SEL_Msk (0x3UL << RCC_CCIPR_I2C3SEL_Pos)
10072#define RCC_CCIPR_I2C3SEL RCC_CCIPR_I2C3SEL_Msk
10073#define RCC_CCIPR_I2C3SEL_0 (0x1UL << RCC_CCIPR_I2C3SEL_Pos)
10074#define RCC_CCIPR_I2C3SEL_1 (0x2UL << RCC_CCIPR_I2C3SEL_Pos)
10076#define RCC_CCIPR_LPTIM1SEL_Pos (18U)
10077#define RCC_CCIPR_LPTIM1SEL_Msk (0x3UL << RCC_CCIPR_LPTIM1SEL_Pos)
10078#define RCC_CCIPR_LPTIM1SEL RCC_CCIPR_LPTIM1SEL_Msk
10079#define RCC_CCIPR_LPTIM1SEL_0 (0x1UL << RCC_CCIPR_LPTIM1SEL_Pos)
10080#define RCC_CCIPR_LPTIM1SEL_1 (0x2UL << RCC_CCIPR_LPTIM1SEL_Pos)
10082#define RCC_CCIPR_LPTIM2SEL_Pos (20U)
10083#define RCC_CCIPR_LPTIM2SEL_Msk (0x3UL << RCC_CCIPR_LPTIM2SEL_Pos)
10084#define RCC_CCIPR_LPTIM2SEL RCC_CCIPR_LPTIM2SEL_Msk
10085#define RCC_CCIPR_LPTIM2SEL_0 (0x1UL << RCC_CCIPR_LPTIM2SEL_Pos)
10086#define RCC_CCIPR_LPTIM2SEL_1 (0x2UL << RCC_CCIPR_LPTIM2SEL_Pos)
10088#define RCC_CCIPR_SAI1SEL_Pos (22U)
10089#define RCC_CCIPR_SAI1SEL_Msk (0x3UL << RCC_CCIPR_SAI1SEL_Pos)
10090#define RCC_CCIPR_SAI1SEL RCC_CCIPR_SAI1SEL_Msk
10091#define RCC_CCIPR_SAI1SEL_0 (0x1UL << RCC_CCIPR_SAI1SEL_Pos)
10092#define RCC_CCIPR_SAI1SEL_1 (0x2UL << RCC_CCIPR_SAI1SEL_Pos)
10094#define RCC_CCIPR_CLK48SEL_Pos (26U)
10095#define RCC_CCIPR_CLK48SEL_Msk (0x3UL << RCC_CCIPR_CLK48SEL_Pos)
10096#define RCC_CCIPR_CLK48SEL RCC_CCIPR_CLK48SEL_Msk
10097#define RCC_CCIPR_CLK48SEL_0 (0x1UL << RCC_CCIPR_CLK48SEL_Pos)
10098#define RCC_CCIPR_CLK48SEL_1 (0x2UL << RCC_CCIPR_CLK48SEL_Pos)
10100#define RCC_CCIPR_ADCSEL_Pos (28U)
10101#define RCC_CCIPR_ADCSEL_Msk (0x3UL << RCC_CCIPR_ADCSEL_Pos)
10102#define RCC_CCIPR_ADCSEL RCC_CCIPR_ADCSEL_Msk
10103#define RCC_CCIPR_ADCSEL_0 (0x1UL << RCC_CCIPR_ADCSEL_Pos)
10104#define RCC_CCIPR_ADCSEL_1 (0x2UL << RCC_CCIPR_ADCSEL_Pos)
10106#define RCC_CCIPR_SWPMI1SEL_Pos (30U)
10107#define RCC_CCIPR_SWPMI1SEL_Msk (0x1UL << RCC_CCIPR_SWPMI1SEL_Pos)
10108#define RCC_CCIPR_SWPMI1SEL RCC_CCIPR_SWPMI1SEL_Msk
10109
10110/******************** Bit definition for RCC_BDCR register ******************/
10111#define RCC_BDCR_LSEON_Pos (0U)
10112#define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos)
10113#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
10114#define RCC_BDCR_LSERDY_Pos (1U)
10115#define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos)
10116#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
10117#define RCC_BDCR_LSEBYP_Pos (2U)
10118#define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos)
10119#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
10120
10121#define RCC_BDCR_LSEDRV_Pos (3U)
10122#define RCC_BDCR_LSEDRV_Msk (0x3UL << RCC_BDCR_LSEDRV_Pos)
10123#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk
10124#define RCC_BDCR_LSEDRV_0 (0x1UL << RCC_BDCR_LSEDRV_Pos)
10125#define RCC_BDCR_LSEDRV_1 (0x2UL << RCC_BDCR_LSEDRV_Pos)
10127#define RCC_BDCR_LSECSSON_Pos (5U)
10128#define RCC_BDCR_LSECSSON_Msk (0x1UL << RCC_BDCR_LSECSSON_Pos)
10129#define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk
10130#define RCC_BDCR_LSECSSD_Pos (6U)
10131#define RCC_BDCR_LSECSSD_Msk (0x1UL << RCC_BDCR_LSECSSD_Pos)
10132#define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk
10133
10134#define RCC_BDCR_RTCSEL_Pos (8U)
10135#define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos)
10136#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
10137#define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos)
10138#define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos)
10140#define RCC_BDCR_RTCEN_Pos (15U)
10141#define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos)
10142#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
10143#define RCC_BDCR_BDRST_Pos (16U)
10144#define RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos)
10145#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
10146#define RCC_BDCR_LSCOEN_Pos (24U)
10147#define RCC_BDCR_LSCOEN_Msk (0x1UL << RCC_BDCR_LSCOEN_Pos)
10148#define RCC_BDCR_LSCOEN RCC_BDCR_LSCOEN_Msk
10149#define RCC_BDCR_LSCOSEL_Pos (25U)
10150#define RCC_BDCR_LSCOSEL_Msk (0x1UL << RCC_BDCR_LSCOSEL_Pos)
10151#define RCC_BDCR_LSCOSEL RCC_BDCR_LSCOSEL_Msk
10152
10153/******************** Bit definition for RCC_CSR register *******************/
10154#define RCC_CSR_LSION_Pos (0U)
10155#define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos)
10156#define RCC_CSR_LSION RCC_CSR_LSION_Msk
10157#define RCC_CSR_LSIRDY_Pos (1U)
10158#define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos)
10159#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
10160
10161#define RCC_CSR_MSISRANGE_Pos (8U)
10162#define RCC_CSR_MSISRANGE_Msk (0xFUL << RCC_CSR_MSISRANGE_Pos)
10163#define RCC_CSR_MSISRANGE RCC_CSR_MSISRANGE_Msk
10164#define RCC_CSR_MSISRANGE_1 (0x4UL << RCC_CSR_MSISRANGE_Pos)
10165#define RCC_CSR_MSISRANGE_2 (0x5UL << RCC_CSR_MSISRANGE_Pos)
10166#define RCC_CSR_MSISRANGE_4 (0x6UL << RCC_CSR_MSISRANGE_Pos)
10167#define RCC_CSR_MSISRANGE_8 (0x7UL << RCC_CSR_MSISRANGE_Pos)
10169#define RCC_CSR_RMVF_Pos (23U)
10170#define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos)
10171#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
10172#define RCC_CSR_FWRSTF_Pos (24U)
10173#define RCC_CSR_FWRSTF_Msk (0x1UL << RCC_CSR_FWRSTF_Pos)
10174#define RCC_CSR_FWRSTF RCC_CSR_FWRSTF_Msk
10175#define RCC_CSR_OBLRSTF_Pos (25U)
10176#define RCC_CSR_OBLRSTF_Msk (0x1UL << RCC_CSR_OBLRSTF_Pos)
10177#define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk
10178#define RCC_CSR_PINRSTF_Pos (26U)
10179#define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos)
10180#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
10181#define RCC_CSR_BORRSTF_Pos (27U)
10182#define RCC_CSR_BORRSTF_Msk (0x1UL << RCC_CSR_BORRSTF_Pos)
10183#define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk
10184#define RCC_CSR_SFTRSTF_Pos (28U)
10185#define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos)
10186#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
10187#define RCC_CSR_IWDGRSTF_Pos (29U)
10188#define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos)
10189#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
10190#define RCC_CSR_WWDGRSTF_Pos (30U)
10191#define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos)
10192#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
10193#define RCC_CSR_LPWRRSTF_Pos (31U)
10194#define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos)
10195#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
10196
10197/******************** Bit definition for RCC_CRRCR register *****************/
10198#define RCC_CRRCR_HSI48ON_Pos (0U)
10199#define RCC_CRRCR_HSI48ON_Msk (0x1UL << RCC_CRRCR_HSI48ON_Pos)
10200#define RCC_CRRCR_HSI48ON RCC_CRRCR_HSI48ON_Msk
10201#define RCC_CRRCR_HSI48RDY_Pos (1U)
10202#define RCC_CRRCR_HSI48RDY_Msk (0x1UL << RCC_CRRCR_HSI48RDY_Pos)
10203#define RCC_CRRCR_HSI48RDY RCC_CRRCR_HSI48RDY_Msk
10204
10206#define RCC_CRRCR_HSI48CAL_Pos (7U)
10207#define RCC_CRRCR_HSI48CAL_Msk (0x1FFUL << RCC_CRRCR_HSI48CAL_Pos)
10208#define RCC_CRRCR_HSI48CAL RCC_CRRCR_HSI48CAL_Msk
10209#define RCC_CRRCR_HSI48CAL_0 (0x001UL << RCC_CRRCR_HSI48CAL_Pos)
10210#define RCC_CRRCR_HSI48CAL_1 (0x002UL << RCC_CRRCR_HSI48CAL_Pos)
10211#define RCC_CRRCR_HSI48CAL_2 (0x004UL << RCC_CRRCR_HSI48CAL_Pos)
10212#define RCC_CRRCR_HSI48CAL_3 (0x008UL << RCC_CRRCR_HSI48CAL_Pos)
10213#define RCC_CRRCR_HSI48CAL_4 (0x010UL << RCC_CRRCR_HSI48CAL_Pos)
10214#define RCC_CRRCR_HSI48CAL_5 (0x020UL << RCC_CRRCR_HSI48CAL_Pos)
10215#define RCC_CRRCR_HSI48CAL_6 (0x040UL << RCC_CRRCR_HSI48CAL_Pos)
10216#define RCC_CRRCR_HSI48CAL_7 (0x080UL << RCC_CRRCR_HSI48CAL_Pos)
10217#define RCC_CRRCR_HSI48CAL_8 (0x100UL << RCC_CRRCR_HSI48CAL_Pos)
10219/******************************************************************************/
10220/* */
10221/* RNG */
10222/* */
10223/******************************************************************************/
10224/******************** Bits definition for RNG_CR register *******************/
10225#define RNG_CR_RNGEN_Pos (2U)
10226#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos)
10227#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
10228#define RNG_CR_IE_Pos (3U)
10229#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos)
10230#define RNG_CR_IE RNG_CR_IE_Msk
10231
10232/******************** Bits definition for RNG_SR register *******************/
10233#define RNG_SR_DRDY_Pos (0U)
10234#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos)
10235#define RNG_SR_DRDY RNG_SR_DRDY_Msk
10236#define RNG_SR_CECS_Pos (1U)
10237#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos)
10238#define RNG_SR_CECS RNG_SR_CECS_Msk
10239#define RNG_SR_SECS_Pos (2U)
10240#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos)
10241#define RNG_SR_SECS RNG_SR_SECS_Msk
10242#define RNG_SR_CEIS_Pos (5U)
10243#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos)
10244#define RNG_SR_CEIS RNG_SR_CEIS_Msk
10245#define RNG_SR_SEIS_Pos (6U)
10246#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos)
10247#define RNG_SR_SEIS RNG_SR_SEIS_Msk
10248
10249/******************************************************************************/
10250/* */
10251/* Real-Time Clock (RTC) */
10252/* */
10253/******************************************************************************/
10254/*
10255* @brief Specific device feature definitions
10256*/
10257#define RTC_TAMPER1_SUPPORT
10258#define RTC_TAMPER2_SUPPORT
10259#define RTC_TAMPER3_SUPPORT
10260
10261#define RTC_WAKEUP_SUPPORT
10262#define RTC_BACKUP_SUPPORT
10263/******************** Number of backup registers ******************************/
10264#define RTC_BKP_NUMBER 32U
10265
10266
10267/******************** Bits definition for RTC_TR register *******************/
10268#define RTC_TR_PM_Pos (22U)
10269#define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos)
10270#define RTC_TR_PM RTC_TR_PM_Msk
10271#define RTC_TR_HT_Pos (20U)
10272#define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos)
10273#define RTC_TR_HT RTC_TR_HT_Msk
10274#define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos)
10275#define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos)
10276#define RTC_TR_HU_Pos (16U)
10277#define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos)
10278#define RTC_TR_HU RTC_TR_HU_Msk
10279#define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos)
10280#define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos)
10281#define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos)
10282#define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos)
10283#define RTC_TR_MNT_Pos (12U)
10284#define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos)
10285#define RTC_TR_MNT RTC_TR_MNT_Msk
10286#define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos)
10287#define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos)
10288#define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos)
10289#define RTC_TR_MNU_Pos (8U)
10290#define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos)
10291#define RTC_TR_MNU RTC_TR_MNU_Msk
10292#define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos)
10293#define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos)
10294#define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos)
10295#define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos)
10296#define RTC_TR_ST_Pos (4U)
10297#define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos)
10298#define RTC_TR_ST RTC_TR_ST_Msk
10299#define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos)
10300#define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos)
10301#define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos)
10302#define RTC_TR_SU_Pos (0U)
10303#define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos)
10304#define RTC_TR_SU RTC_TR_SU_Msk
10305#define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos)
10306#define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos)
10307#define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos)
10308#define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos)
10310/******************** Bits definition for RTC_DR register *******************/
10311#define RTC_DR_YT_Pos (20U)
10312#define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos)
10313#define RTC_DR_YT RTC_DR_YT_Msk
10314#define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos)
10315#define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos)
10316#define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos)
10317#define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos)
10318#define RTC_DR_YU_Pos (16U)
10319#define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos)
10320#define RTC_DR_YU RTC_DR_YU_Msk
10321#define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos)
10322#define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos)
10323#define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos)
10324#define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos)
10325#define RTC_DR_WDU_Pos (13U)
10326#define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos)
10327#define RTC_DR_WDU RTC_DR_WDU_Msk
10328#define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos)
10329#define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos)
10330#define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos)
10331#define RTC_DR_MT_Pos (12U)
10332#define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos)
10333#define RTC_DR_MT RTC_DR_MT_Msk
10334#define RTC_DR_MU_Pos (8U)
10335#define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos)
10336#define RTC_DR_MU RTC_DR_MU_Msk
10337#define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos)
10338#define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos)
10339#define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos)
10340#define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos)
10341#define RTC_DR_DT_Pos (4U)
10342#define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos)
10343#define RTC_DR_DT RTC_DR_DT_Msk
10344#define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos)
10345#define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos)
10346#define RTC_DR_DU_Pos (0U)
10347#define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos)
10348#define RTC_DR_DU RTC_DR_DU_Msk
10349#define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos)
10350#define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos)
10351#define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos)
10352#define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos)
10354/******************** Bits definition for RTC_CR register *******************/
10355#define RTC_CR_ITSE_Pos (24U)
10356#define RTC_CR_ITSE_Msk (0x1UL << RTC_CR_ITSE_Pos)
10357#define RTC_CR_ITSE RTC_CR_ITSE_Msk
10358#define RTC_CR_COE_Pos (23U)
10359#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos)
10360#define RTC_CR_COE RTC_CR_COE_Msk
10361#define RTC_CR_OSEL_Pos (21U)
10362#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos)
10363#define RTC_CR_OSEL RTC_CR_OSEL_Msk
10364#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos)
10365#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos)
10366#define RTC_CR_POL_Pos (20U)
10367#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos)
10368#define RTC_CR_POL RTC_CR_POL_Msk
10369#define RTC_CR_COSEL_Pos (19U)
10370#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos)
10371#define RTC_CR_COSEL RTC_CR_COSEL_Msk
10372#define RTC_CR_BKP_Pos (18U)
10373#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos)
10374#define RTC_CR_BKP RTC_CR_BKP_Msk
10375#define RTC_CR_SUB1H_Pos (17U)
10376#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos)
10377#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
10378#define RTC_CR_ADD1H_Pos (16U)
10379#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos)
10380#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
10381#define RTC_CR_TSIE_Pos (15U)
10382#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos)
10383#define RTC_CR_TSIE RTC_CR_TSIE_Msk
10384#define RTC_CR_WUTIE_Pos (14U)
10385#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos)
10386#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
10387#define RTC_CR_ALRBIE_Pos (13U)
10388#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos)
10389#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
10390#define RTC_CR_ALRAIE_Pos (12U)
10391#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos)
10392#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
10393#define RTC_CR_TSE_Pos (11U)
10394#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos)
10395#define RTC_CR_TSE RTC_CR_TSE_Msk
10396#define RTC_CR_WUTE_Pos (10U)
10397#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos)
10398#define RTC_CR_WUTE RTC_CR_WUTE_Msk
10399#define RTC_CR_ALRBE_Pos (9U)
10400#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos)
10401#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
10402#define RTC_CR_ALRAE_Pos (8U)
10403#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos)
10404#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
10405#define RTC_CR_FMT_Pos (6U)
10406#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos)
10407#define RTC_CR_FMT RTC_CR_FMT_Msk
10408#define RTC_CR_BYPSHAD_Pos (5U)
10409#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos)
10410#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
10411#define RTC_CR_REFCKON_Pos (4U)
10412#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos)
10413#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
10414#define RTC_CR_TSEDGE_Pos (3U)
10415#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos)
10416#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
10417#define RTC_CR_WUCKSEL_Pos (0U)
10418#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos)
10419#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
10420#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos)
10421#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos)
10422#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos)
10424/* Legacy defines */
10425#define RTC_CR_BCK_Pos RTC_CR_BKP_Pos
10426#define RTC_CR_BCK_Msk RTC_CR_BKP_Msk
10427#define RTC_CR_BCK RTC_CR_BKP
10428
10429/******************** Bits definition for RTC_ISR register ******************/
10430#define RTC_ISR_ITSF_Pos (17U)
10431#define RTC_ISR_ITSF_Msk (0x1UL << RTC_ISR_ITSF_Pos)
10432#define RTC_ISR_ITSF RTC_ISR_ITSF_Msk
10433#define RTC_ISR_RECALPF_Pos (16U)
10434#define RTC_ISR_RECALPF_Msk (0x1UL << RTC_ISR_RECALPF_Pos)
10435#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
10436#define RTC_ISR_TAMP3F_Pos (15U)
10437#define RTC_ISR_TAMP3F_Msk (0x1UL << RTC_ISR_TAMP3F_Pos)
10438#define RTC_ISR_TAMP3F RTC_ISR_TAMP3F_Msk
10439#define RTC_ISR_TAMP2F_Pos (14U)
10440#define RTC_ISR_TAMP2F_Msk (0x1UL << RTC_ISR_TAMP2F_Pos)
10441#define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
10442#define RTC_ISR_TAMP1F_Pos (13U)
10443#define RTC_ISR_TAMP1F_Msk (0x1UL << RTC_ISR_TAMP1F_Pos)
10444#define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
10445#define RTC_ISR_TSOVF_Pos (12U)
10446#define RTC_ISR_TSOVF_Msk (0x1UL << RTC_ISR_TSOVF_Pos)
10447#define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
10448#define RTC_ISR_TSF_Pos (11U)
10449#define RTC_ISR_TSF_Msk (0x1UL << RTC_ISR_TSF_Pos)
10450#define RTC_ISR_TSF RTC_ISR_TSF_Msk
10451#define RTC_ISR_WUTF_Pos (10U)
10452#define RTC_ISR_WUTF_Msk (0x1UL << RTC_ISR_WUTF_Pos)
10453#define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
10454#define RTC_ISR_ALRBF_Pos (9U)
10455#define RTC_ISR_ALRBF_Msk (0x1UL << RTC_ISR_ALRBF_Pos)
10456#define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
10457#define RTC_ISR_ALRAF_Pos (8U)
10458#define RTC_ISR_ALRAF_Msk (0x1UL << RTC_ISR_ALRAF_Pos)
10459#define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
10460#define RTC_ISR_INIT_Pos (7U)
10461#define RTC_ISR_INIT_Msk (0x1UL << RTC_ISR_INIT_Pos)
10462#define RTC_ISR_INIT RTC_ISR_INIT_Msk
10463#define RTC_ISR_INITF_Pos (6U)
10464#define RTC_ISR_INITF_Msk (0x1UL << RTC_ISR_INITF_Pos)
10465#define RTC_ISR_INITF RTC_ISR_INITF_Msk
10466#define RTC_ISR_RSF_Pos (5U)
10467#define RTC_ISR_RSF_Msk (0x1UL << RTC_ISR_RSF_Pos)
10468#define RTC_ISR_RSF RTC_ISR_RSF_Msk
10469#define RTC_ISR_INITS_Pos (4U)
10470#define RTC_ISR_INITS_Msk (0x1UL << RTC_ISR_INITS_Pos)
10471#define RTC_ISR_INITS RTC_ISR_INITS_Msk
10472#define RTC_ISR_SHPF_Pos (3U)
10473#define RTC_ISR_SHPF_Msk (0x1UL << RTC_ISR_SHPF_Pos)
10474#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
10475#define RTC_ISR_WUTWF_Pos (2U)
10476#define RTC_ISR_WUTWF_Msk (0x1UL << RTC_ISR_WUTWF_Pos)
10477#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
10478#define RTC_ISR_ALRBWF_Pos (1U)
10479#define RTC_ISR_ALRBWF_Msk (0x1UL << RTC_ISR_ALRBWF_Pos)
10480#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
10481#define RTC_ISR_ALRAWF_Pos (0U)
10482#define RTC_ISR_ALRAWF_Msk (0x1UL << RTC_ISR_ALRAWF_Pos)
10483#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
10484
10485/******************** Bits definition for RTC_PRER register *****************/
10486#define RTC_PRER_PREDIV_A_Pos (16U)
10487#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos)
10488#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
10489#define RTC_PRER_PREDIV_S_Pos (0U)
10490#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)
10491#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
10492
10493/******************** Bits definition for RTC_WUTR register *****************/
10494#define RTC_WUTR_WUT_Pos (0U)
10495#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos)
10496#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
10497
10498/******************** Bits definition for RTC_ALRMAR register ***************/
10499#define RTC_ALRMAR_MSK4_Pos (31U)
10500#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos)
10501#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
10502#define RTC_ALRMAR_WDSEL_Pos (30U)
10503#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos)
10504#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
10505#define RTC_ALRMAR_DT_Pos (28U)
10506#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos)
10507#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
10508#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos)
10509#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos)
10510#define RTC_ALRMAR_DU_Pos (24U)
10511#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos)
10512#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
10513#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos)
10514#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos)
10515#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos)
10516#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos)
10517#define RTC_ALRMAR_MSK3_Pos (23U)
10518#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos)
10519#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
10520#define RTC_ALRMAR_PM_Pos (22U)
10521#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos)
10522#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
10523#define RTC_ALRMAR_HT_Pos (20U)
10524#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos)
10525#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
10526#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos)
10527#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos)
10528#define RTC_ALRMAR_HU_Pos (16U)
10529#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos)
10530#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
10531#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos)
10532#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos)
10533#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos)
10534#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos)
10535#define RTC_ALRMAR_MSK2_Pos (15U)
10536#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos)
10537#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
10538#define RTC_ALRMAR_MNT_Pos (12U)
10539#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos)
10540#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
10541#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos)
10542#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos)
10543#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos)
10544#define RTC_ALRMAR_MNU_Pos (8U)
10545#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos)
10546#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
10547#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos)
10548#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos)
10549#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos)
10550#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos)
10551#define RTC_ALRMAR_MSK1_Pos (7U)
10552#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos)
10553#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
10554#define RTC_ALRMAR_ST_Pos (4U)
10555#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos)
10556#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
10557#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos)
10558#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos)
10559#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos)
10560#define RTC_ALRMAR_SU_Pos (0U)
10561#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos)
10562#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
10563#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos)
10564#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos)
10565#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos)
10566#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos)
10568/******************** Bits definition for RTC_ALRMBR register ***************/
10569#define RTC_ALRMBR_MSK4_Pos (31U)
10570#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos)
10571#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
10572#define RTC_ALRMBR_WDSEL_Pos (30U)
10573#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos)
10574#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
10575#define RTC_ALRMBR_DT_Pos (28U)
10576#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos)
10577#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
10578#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos)
10579#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos)
10580#define RTC_ALRMBR_DU_Pos (24U)
10581#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos)
10582#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
10583#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos)
10584#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos)
10585#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos)
10586#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos)
10587#define RTC_ALRMBR_MSK3_Pos (23U)
10588#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos)
10589#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
10590#define RTC_ALRMBR_PM_Pos (22U)
10591#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos)
10592#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
10593#define RTC_ALRMBR_HT_Pos (20U)
10594#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos)
10595#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
10596#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos)
10597#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos)
10598#define RTC_ALRMBR_HU_Pos (16U)
10599#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos)
10600#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
10601#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos)
10602#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos)
10603#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos)
10604#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos)
10605#define RTC_ALRMBR_MSK2_Pos (15U)
10606#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos)
10607#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
10608#define RTC_ALRMBR_MNT_Pos (12U)
10609#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos)
10610#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
10611#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos)
10612#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos)
10613#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos)
10614#define RTC_ALRMBR_MNU_Pos (8U)
10615#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos)
10616#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
10617#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos)
10618#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos)
10619#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos)
10620#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos)
10621#define RTC_ALRMBR_MSK1_Pos (7U)
10622#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos)
10623#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
10624#define RTC_ALRMBR_ST_Pos (4U)
10625#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos)
10626#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
10627#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos)
10628#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos)
10629#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos)
10630#define RTC_ALRMBR_SU_Pos (0U)
10631#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos)
10632#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
10633#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos)
10634#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos)
10635#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos)
10636#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos)
10638/******************** Bits definition for RTC_WPR register ******************/
10639#define RTC_WPR_KEY_Pos (0U)
10640#define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos)
10641#define RTC_WPR_KEY RTC_WPR_KEY_Msk
10642
10643/******************** Bits definition for RTC_SSR register ******************/
10644#define RTC_SSR_SS_Pos (0U)
10645#define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos)
10646#define RTC_SSR_SS RTC_SSR_SS_Msk
10647
10648/******************** Bits definition for RTC_SHIFTR register ***************/
10649#define RTC_SHIFTR_SUBFS_Pos (0U)
10650#define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)
10651#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
10652#define RTC_SHIFTR_ADD1S_Pos (31U)
10653#define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos)
10654#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
10655
10656/******************** Bits definition for RTC_TSTR register *****************/
10657#define RTC_TSTR_PM_Pos (22U)
10658#define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos)
10659#define RTC_TSTR_PM RTC_TSTR_PM_Msk
10660#define RTC_TSTR_HT_Pos (20U)
10661#define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos)
10662#define RTC_TSTR_HT RTC_TSTR_HT_Msk
10663#define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos)
10664#define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos)
10665#define RTC_TSTR_HU_Pos (16U)
10666#define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos)
10667#define RTC_TSTR_HU RTC_TSTR_HU_Msk
10668#define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos)
10669#define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos)
10670#define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos)
10671#define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos)
10672#define RTC_TSTR_MNT_Pos (12U)
10673#define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos)
10674#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
10675#define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos)
10676#define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos)
10677#define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos)
10678#define RTC_TSTR_MNU_Pos (8U)
10679#define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos)
10680#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
10681#define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos)
10682#define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos)
10683#define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos)
10684#define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos)
10685#define RTC_TSTR_ST_Pos (4U)
10686#define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos)
10687#define RTC_TSTR_ST RTC_TSTR_ST_Msk
10688#define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos)
10689#define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos)
10690#define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos)
10691#define RTC_TSTR_SU_Pos (0U)
10692#define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos)
10693#define RTC_TSTR_SU RTC_TSTR_SU_Msk
10694#define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos)
10695#define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos)
10696#define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos)
10697#define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos)
10699/******************** Bits definition for RTC_TSDR register *****************/
10700#define RTC_TSDR_WDU_Pos (13U)
10701#define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos)
10702#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
10703#define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos)
10704#define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos)
10705#define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos)
10706#define RTC_TSDR_MT_Pos (12U)
10707#define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos)
10708#define RTC_TSDR_MT RTC_TSDR_MT_Msk
10709#define RTC_TSDR_MU_Pos (8U)
10710#define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos)
10711#define RTC_TSDR_MU RTC_TSDR_MU_Msk
10712#define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos)
10713#define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos)
10714#define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos)
10715#define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos)
10716#define RTC_TSDR_DT_Pos (4U)
10717#define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos)
10718#define RTC_TSDR_DT RTC_TSDR_DT_Msk
10719#define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos)
10720#define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos)
10721#define RTC_TSDR_DU_Pos (0U)
10722#define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos)
10723#define RTC_TSDR_DU RTC_TSDR_DU_Msk
10724#define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos)
10725#define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos)
10726#define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos)
10727#define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos)
10729/******************** Bits definition for RTC_TSSSR register ****************/
10730#define RTC_TSSSR_SS_Pos (0U)
10731#define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos)
10732#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
10733
10734/******************** Bits definition for RTC_CAL register *****************/
10735#define RTC_CALR_CALP_Pos (15U)
10736#define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos)
10737#define RTC_CALR_CALP RTC_CALR_CALP_Msk
10738#define RTC_CALR_CALW8_Pos (14U)
10739#define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos)
10740#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
10741#define RTC_CALR_CALW16_Pos (13U)
10742#define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos)
10743#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
10744#define RTC_CALR_CALM_Pos (0U)
10745#define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos)
10746#define RTC_CALR_CALM RTC_CALR_CALM_Msk
10747#define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos)
10748#define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos)
10749#define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos)
10750#define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos)
10751#define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos)
10752#define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos)
10753#define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos)
10754#define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos)
10755#define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos)
10757/******************** Bits definition for RTC_TAMPCR register ***************/
10758#define RTC_TAMPCR_TAMP3MF_Pos (24U)
10759#define RTC_TAMPCR_TAMP3MF_Msk (0x1UL << RTC_TAMPCR_TAMP3MF_Pos)
10760#define RTC_TAMPCR_TAMP3MF RTC_TAMPCR_TAMP3MF_Msk
10761#define RTC_TAMPCR_TAMP3NOERASE_Pos (23U)
10762#define RTC_TAMPCR_TAMP3NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP3NOERASE_Pos)
10763#define RTC_TAMPCR_TAMP3NOERASE RTC_TAMPCR_TAMP3NOERASE_Msk
10764#define RTC_TAMPCR_TAMP3IE_Pos (22U)
10765#define RTC_TAMPCR_TAMP3IE_Msk (0x1UL << RTC_TAMPCR_TAMP3IE_Pos)
10766#define RTC_TAMPCR_TAMP3IE RTC_TAMPCR_TAMP3IE_Msk
10767#define RTC_TAMPCR_TAMP2MF_Pos (21U)
10768#define RTC_TAMPCR_TAMP2MF_Msk (0x1UL << RTC_TAMPCR_TAMP2MF_Pos)
10769#define RTC_TAMPCR_TAMP2MF RTC_TAMPCR_TAMP2MF_Msk
10770#define RTC_TAMPCR_TAMP2NOERASE_Pos (20U)
10771#define RTC_TAMPCR_TAMP2NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP2NOERASE_Pos)
10772#define RTC_TAMPCR_TAMP2NOERASE RTC_TAMPCR_TAMP2NOERASE_Msk
10773#define RTC_TAMPCR_TAMP2IE_Pos (19U)
10774#define RTC_TAMPCR_TAMP2IE_Msk (0x1UL << RTC_TAMPCR_TAMP2IE_Pos)
10775#define RTC_TAMPCR_TAMP2IE RTC_TAMPCR_TAMP2IE_Msk
10776#define RTC_TAMPCR_TAMP1MF_Pos (18U)
10777#define RTC_TAMPCR_TAMP1MF_Msk (0x1UL << RTC_TAMPCR_TAMP1MF_Pos)
10778#define RTC_TAMPCR_TAMP1MF RTC_TAMPCR_TAMP1MF_Msk
10779#define RTC_TAMPCR_TAMP1NOERASE_Pos (17U)
10780#define RTC_TAMPCR_TAMP1NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP1NOERASE_Pos)
10781#define RTC_TAMPCR_TAMP1NOERASE RTC_TAMPCR_TAMP1NOERASE_Msk
10782#define RTC_TAMPCR_TAMP1IE_Pos (16U)
10783#define RTC_TAMPCR_TAMP1IE_Msk (0x1UL << RTC_TAMPCR_TAMP1IE_Pos)
10784#define RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE_Msk
10785#define RTC_TAMPCR_TAMPPUDIS_Pos (15U)
10786#define RTC_TAMPCR_TAMPPUDIS_Msk (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos)
10787#define RTC_TAMPCR_TAMPPUDIS RTC_TAMPCR_TAMPPUDIS_Msk
10788#define RTC_TAMPCR_TAMPPRCH_Pos (13U)
10789#define RTC_TAMPCR_TAMPPRCH_Msk (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos)
10790#define RTC_TAMPCR_TAMPPRCH RTC_TAMPCR_TAMPPRCH_Msk
10791#define RTC_TAMPCR_TAMPPRCH_0 (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos)
10792#define RTC_TAMPCR_TAMPPRCH_1 (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos)
10793#define RTC_TAMPCR_TAMPFLT_Pos (11U)
10794#define RTC_TAMPCR_TAMPFLT_Msk (0x3UL << RTC_TAMPCR_TAMPFLT_Pos)
10795#define RTC_TAMPCR_TAMPFLT RTC_TAMPCR_TAMPFLT_Msk
10796#define RTC_TAMPCR_TAMPFLT_0 (0x1UL << RTC_TAMPCR_TAMPFLT_Pos)
10797#define RTC_TAMPCR_TAMPFLT_1 (0x2UL << RTC_TAMPCR_TAMPFLT_Pos)
10798#define RTC_TAMPCR_TAMPFREQ_Pos (8U)
10799#define RTC_TAMPCR_TAMPFREQ_Msk (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos)
10800#define RTC_TAMPCR_TAMPFREQ RTC_TAMPCR_TAMPFREQ_Msk
10801#define RTC_TAMPCR_TAMPFREQ_0 (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos)
10802#define RTC_TAMPCR_TAMPFREQ_1 (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos)
10803#define RTC_TAMPCR_TAMPFREQ_2 (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos)
10804#define RTC_TAMPCR_TAMPTS_Pos (7U)
10805#define RTC_TAMPCR_TAMPTS_Msk (0x1UL << RTC_TAMPCR_TAMPTS_Pos)
10806#define RTC_TAMPCR_TAMPTS RTC_TAMPCR_TAMPTS_Msk
10807#define RTC_TAMPCR_TAMP3TRG_Pos (6U)
10808#define RTC_TAMPCR_TAMP3TRG_Msk (0x1UL << RTC_TAMPCR_TAMP3TRG_Pos)
10809#define RTC_TAMPCR_TAMP3TRG RTC_TAMPCR_TAMP3TRG_Msk
10810#define RTC_TAMPCR_TAMP3E_Pos (5U)
10811#define RTC_TAMPCR_TAMP3E_Msk (0x1UL << RTC_TAMPCR_TAMP3E_Pos)
10812#define RTC_TAMPCR_TAMP3E RTC_TAMPCR_TAMP3E_Msk
10813#define RTC_TAMPCR_TAMP2TRG_Pos (4U)
10814#define RTC_TAMPCR_TAMP2TRG_Msk (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos)
10815#define RTC_TAMPCR_TAMP2TRG RTC_TAMPCR_TAMP2TRG_Msk
10816#define RTC_TAMPCR_TAMP2E_Pos (3U)
10817#define RTC_TAMPCR_TAMP2E_Msk (0x1UL << RTC_TAMPCR_TAMP2E_Pos)
10818#define RTC_TAMPCR_TAMP2E RTC_TAMPCR_TAMP2E_Msk
10819#define RTC_TAMPCR_TAMPIE_Pos (2U)
10820#define RTC_TAMPCR_TAMPIE_Msk (0x1UL << RTC_TAMPCR_TAMPIE_Pos)
10821#define RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE_Msk
10822#define RTC_TAMPCR_TAMP1TRG_Pos (1U)
10823#define RTC_TAMPCR_TAMP1TRG_Msk (0x1UL << RTC_TAMPCR_TAMP1TRG_Pos)
10824#define RTC_TAMPCR_TAMP1TRG RTC_TAMPCR_TAMP1TRG_Msk
10825#define RTC_TAMPCR_TAMP1E_Pos (0U)
10826#define RTC_TAMPCR_TAMP1E_Msk (0x1UL << RTC_TAMPCR_TAMP1E_Pos)
10827#define RTC_TAMPCR_TAMP1E RTC_TAMPCR_TAMP1E_Msk
10828
10829/******************** Bits definition for RTC_ALRMASSR register *************/
10830#define RTC_ALRMASSR_MASKSS_Pos (24U)
10831#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos)
10832#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
10833#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos)
10834#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos)
10835#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos)
10836#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos)
10837#define RTC_ALRMASSR_SS_Pos (0U)
10838#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos)
10839#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
10840
10841/******************** Bits definition for RTC_ALRMBSSR register *************/
10842#define RTC_ALRMBSSR_MASKSS_Pos (24U)
10843#define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)
10844#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
10845#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)
10846#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)
10847#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)
10848#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)
10849#define RTC_ALRMBSSR_SS_Pos (0U)
10850#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)
10851#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
10852
10853/******************** Bits definition for RTC_0R register *******************/
10854#define RTC_OR_OUT_RMP_Pos (1U)
10855#define RTC_OR_OUT_RMP_Msk (0x1UL << RTC_OR_OUT_RMP_Pos)
10856#define RTC_OR_OUT_RMP RTC_OR_OUT_RMP_Msk
10857#define RTC_OR_ALARMOUTTYPE_Pos (0U)
10858#define RTC_OR_ALARMOUTTYPE_Msk (0x1UL << RTC_OR_ALARMOUTTYPE_Pos)
10859#define RTC_OR_ALARMOUTTYPE RTC_OR_ALARMOUTTYPE_Msk
10860
10861
10862/******************** Bits definition for RTC_BKP0R register ****************/
10863#define RTC_BKP0R_Pos (0U)
10864#define RTC_BKP0R_Msk (0xFFFFFFFFUL << RTC_BKP0R_Pos)
10865#define RTC_BKP0R RTC_BKP0R_Msk
10866
10867/******************** Bits definition for RTC_BKP1R register ****************/
10868#define RTC_BKP1R_Pos (0U)
10869#define RTC_BKP1R_Msk (0xFFFFFFFFUL << RTC_BKP1R_Pos)
10870#define RTC_BKP1R RTC_BKP1R_Msk
10871
10872/******************** Bits definition for RTC_BKP2R register ****************/
10873#define RTC_BKP2R_Pos (0U)
10874#define RTC_BKP2R_Msk (0xFFFFFFFFUL << RTC_BKP2R_Pos)
10875#define RTC_BKP2R RTC_BKP2R_Msk
10876
10877/******************** Bits definition for RTC_BKP3R register ****************/
10878#define RTC_BKP3R_Pos (0U)
10879#define RTC_BKP3R_Msk (0xFFFFFFFFUL << RTC_BKP3R_Pos)
10880#define RTC_BKP3R RTC_BKP3R_Msk
10881
10882/******************** Bits definition for RTC_BKP4R register ****************/
10883#define RTC_BKP4R_Pos (0U)
10884#define RTC_BKP4R_Msk (0xFFFFFFFFUL << RTC_BKP4R_Pos)
10885#define RTC_BKP4R RTC_BKP4R_Msk
10886
10887/******************** Bits definition for RTC_BKP5R register ****************/
10888#define RTC_BKP5R_Pos (0U)
10889#define RTC_BKP5R_Msk (0xFFFFFFFFUL << RTC_BKP5R_Pos)
10890#define RTC_BKP5R RTC_BKP5R_Msk
10891
10892/******************** Bits definition for RTC_BKP6R register ****************/
10893#define RTC_BKP6R_Pos (0U)
10894#define RTC_BKP6R_Msk (0xFFFFFFFFUL << RTC_BKP6R_Pos)
10895#define RTC_BKP6R RTC_BKP6R_Msk
10896
10897/******************** Bits definition for RTC_BKP7R register ****************/
10898#define RTC_BKP7R_Pos (0U)
10899#define RTC_BKP7R_Msk (0xFFFFFFFFUL << RTC_BKP7R_Pos)
10900#define RTC_BKP7R RTC_BKP7R_Msk
10901
10902/******************** Bits definition for RTC_BKP8R register ****************/
10903#define RTC_BKP8R_Pos (0U)
10904#define RTC_BKP8R_Msk (0xFFFFFFFFUL << RTC_BKP8R_Pos)
10905#define RTC_BKP8R RTC_BKP8R_Msk
10906
10907/******************** Bits definition for RTC_BKP9R register ****************/
10908#define RTC_BKP9R_Pos (0U)
10909#define RTC_BKP9R_Msk (0xFFFFFFFFUL << RTC_BKP9R_Pos)
10910#define RTC_BKP9R RTC_BKP9R_Msk
10911
10912/******************** Bits definition for RTC_BKP10R register ***************/
10913#define RTC_BKP10R_Pos (0U)
10914#define RTC_BKP10R_Msk (0xFFFFFFFFUL << RTC_BKP10R_Pos)
10915#define RTC_BKP10R RTC_BKP10R_Msk
10916
10917/******************** Bits definition for RTC_BKP11R register ***************/
10918#define RTC_BKP11R_Pos (0U)
10919#define RTC_BKP11R_Msk (0xFFFFFFFFUL << RTC_BKP11R_Pos)
10920#define RTC_BKP11R RTC_BKP11R_Msk
10921
10922/******************** Bits definition for RTC_BKP12R register ***************/
10923#define RTC_BKP12R_Pos (0U)
10924#define RTC_BKP12R_Msk (0xFFFFFFFFUL << RTC_BKP12R_Pos)
10925#define RTC_BKP12R RTC_BKP12R_Msk
10926
10927/******************** Bits definition for RTC_BKP13R register ***************/
10928#define RTC_BKP13R_Pos (0U)
10929#define RTC_BKP13R_Msk (0xFFFFFFFFUL << RTC_BKP13R_Pos)
10930#define RTC_BKP13R RTC_BKP13R_Msk
10931
10932/******************** Bits definition for RTC_BKP14R register ***************/
10933#define RTC_BKP14R_Pos (0U)
10934#define RTC_BKP14R_Msk (0xFFFFFFFFUL << RTC_BKP14R_Pos)
10935#define RTC_BKP14R RTC_BKP14R_Msk
10936
10937/******************** Bits definition for RTC_BKP15R register ***************/
10938#define RTC_BKP15R_Pos (0U)
10939#define RTC_BKP15R_Msk (0xFFFFFFFFUL << RTC_BKP15R_Pos)
10940#define RTC_BKP15R RTC_BKP15R_Msk
10941
10942/******************** Bits definition for RTC_BKP16R register ***************/
10943#define RTC_BKP16R_Pos (0U)
10944#define RTC_BKP16R_Msk (0xFFFFFFFFUL << RTC_BKP16R_Pos)
10945#define RTC_BKP16R RTC_BKP16R_Msk
10946
10947/******************** Bits definition for RTC_BKP17R register ***************/
10948#define RTC_BKP17R_Pos (0U)
10949#define RTC_BKP17R_Msk (0xFFFFFFFFUL << RTC_BKP17R_Pos)
10950#define RTC_BKP17R RTC_BKP17R_Msk
10951
10952/******************** Bits definition for RTC_BKP18R register ***************/
10953#define RTC_BKP18R_Pos (0U)
10954#define RTC_BKP18R_Msk (0xFFFFFFFFUL << RTC_BKP18R_Pos)
10955#define RTC_BKP18R RTC_BKP18R_Msk
10956
10957/******************** Bits definition for RTC_BKP19R register ***************/
10958#define RTC_BKP19R_Pos (0U)
10959#define RTC_BKP19R_Msk (0xFFFFFFFFUL << RTC_BKP19R_Pos)
10960#define RTC_BKP19R RTC_BKP19R_Msk
10961
10962/******************** Bits definition for RTC_BKP20R register ***************/
10963#define RTC_BKP20R_Pos (0U)
10964#define RTC_BKP20R_Msk (0xFFFFFFFFUL << RTC_BKP20R_Pos)
10965#define RTC_BKP20R RTC_BKP20R_Msk
10966
10967/******************** Bits definition for RTC_BKP21R register ***************/
10968#define RTC_BKP21R_Pos (0U)
10969#define RTC_BKP21R_Msk (0xFFFFFFFFUL << RTC_BKP21R_Pos)
10970#define RTC_BKP21R RTC_BKP21R_Msk
10971
10972/******************** Bits definition for RTC_BKP22R register ***************/
10973#define RTC_BKP22R_Pos (0U)
10974#define RTC_BKP22R_Msk (0xFFFFFFFFUL << RTC_BKP22R_Pos)
10975#define RTC_BKP22R RTC_BKP22R_Msk
10976
10977/******************** Bits definition for RTC_BKP23R register ***************/
10978#define RTC_BKP23R_Pos (0U)
10979#define RTC_BKP23R_Msk (0xFFFFFFFFUL << RTC_BKP23R_Pos)
10980#define RTC_BKP23R RTC_BKP23R_Msk
10981
10982/******************** Bits definition for RTC_BKP24R register ***************/
10983#define RTC_BKP24R_Pos (0U)
10984#define RTC_BKP24R_Msk (0xFFFFFFFFUL << RTC_BKP24R_Pos)
10985#define RTC_BKP24R RTC_BKP24R_Msk
10986
10987/******************** Bits definition for RTC_BKP25R register ***************/
10988#define RTC_BKP25R_Pos (0U)
10989#define RTC_BKP25R_Msk (0xFFFFFFFFUL << RTC_BKP25R_Pos)
10990#define RTC_BKP25R RTC_BKP25R_Msk
10991
10992/******************** Bits definition for RTC_BKP26R register ***************/
10993#define RTC_BKP26R_Pos (0U)
10994#define RTC_BKP26R_Msk (0xFFFFFFFFUL << RTC_BKP26R_Pos)
10995#define RTC_BKP26R RTC_BKP26R_Msk
10996
10997/******************** Bits definition for RTC_BKP27R register ***************/
10998#define RTC_BKP27R_Pos (0U)
10999#define RTC_BKP27R_Msk (0xFFFFFFFFUL << RTC_BKP27R_Pos)
11000#define RTC_BKP27R RTC_BKP27R_Msk
11001
11002/******************** Bits definition for RTC_BKP28R register ***************/
11003#define RTC_BKP28R_Pos (0U)
11004#define RTC_BKP28R_Msk (0xFFFFFFFFUL << RTC_BKP28R_Pos)
11005#define RTC_BKP28R RTC_BKP28R_Msk
11006
11007/******************** Bits definition for RTC_BKP29R register ***************/
11008#define RTC_BKP29R_Pos (0U)
11009#define RTC_BKP29R_Msk (0xFFFFFFFFUL << RTC_BKP29R_Pos)
11010#define RTC_BKP29R RTC_BKP29R_Msk
11011
11012/******************** Bits definition for RTC_BKP30R register ***************/
11013#define RTC_BKP30R_Pos (0U)
11014#define RTC_BKP30R_Msk (0xFFFFFFFFUL << RTC_BKP30R_Pos)
11015#define RTC_BKP30R RTC_BKP30R_Msk
11016
11017/******************** Bits definition for RTC_BKP31R register ***************/
11018#define RTC_BKP31R_Pos (0U)
11019#define RTC_BKP31R_Msk (0xFFFFFFFFUL << RTC_BKP31R_Pos)
11020#define RTC_BKP31R RTC_BKP31R_Msk
11021
11022/******************************************************************************/
11023/* */
11024/* Serial Audio Interface */
11025/* */
11026/******************************************************************************/
11027/******************** Bit definition for SAI_GCR register *******************/
11028#define SAI_GCR_SYNCIN_Pos (0U)
11029#define SAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos)
11030#define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk
11031#define SAI_GCR_SYNCIN_0 (0x1UL << SAI_GCR_SYNCIN_Pos)
11032#define SAI_GCR_SYNCIN_1 (0x2UL << SAI_GCR_SYNCIN_Pos)
11034#define SAI_GCR_SYNCOUT_Pos (4U)
11035#define SAI_GCR_SYNCOUT_Msk (0x3UL << SAI_GCR_SYNCOUT_Pos)
11036#define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk
11037#define SAI_GCR_SYNCOUT_0 (0x1UL << SAI_GCR_SYNCOUT_Pos)
11038#define SAI_GCR_SYNCOUT_1 (0x2UL << SAI_GCR_SYNCOUT_Pos)
11040/******************* Bit definition for SAI_xCR1 register *******************/
11041#define SAI_xCR1_MODE_Pos (0U)
11042#define SAI_xCR1_MODE_Msk (0x3UL << SAI_xCR1_MODE_Pos)
11043#define SAI_xCR1_MODE SAI_xCR1_MODE_Msk
11044#define SAI_xCR1_MODE_0 (0x1UL << SAI_xCR1_MODE_Pos)
11045#define SAI_xCR1_MODE_1 (0x2UL << SAI_xCR1_MODE_Pos)
11047#define SAI_xCR1_PRTCFG_Pos (2U)
11048#define SAI_xCR1_PRTCFG_Msk (0x3UL << SAI_xCR1_PRTCFG_Pos)
11049#define SAI_xCR1_PRTCFG SAI_xCR1_PRTCFG_Msk
11050#define SAI_xCR1_PRTCFG_0 (0x1UL << SAI_xCR1_PRTCFG_Pos)
11051#define SAI_xCR1_PRTCFG_1 (0x2UL << SAI_xCR1_PRTCFG_Pos)
11053#define SAI_xCR1_DS_Pos (5U)
11054#define SAI_xCR1_DS_Msk (0x7UL << SAI_xCR1_DS_Pos)
11055#define SAI_xCR1_DS SAI_xCR1_DS_Msk
11056#define SAI_xCR1_DS_0 (0x1UL << SAI_xCR1_DS_Pos)
11057#define SAI_xCR1_DS_1 (0x2UL << SAI_xCR1_DS_Pos)
11058#define SAI_xCR1_DS_2 (0x4UL << SAI_xCR1_DS_Pos)
11060#define SAI_xCR1_LSBFIRST_Pos (8U)
11061#define SAI_xCR1_LSBFIRST_Msk (0x1UL << SAI_xCR1_LSBFIRST_Pos)
11062#define SAI_xCR1_LSBFIRST SAI_xCR1_LSBFIRST_Msk
11063#define SAI_xCR1_CKSTR_Pos (9U)
11064#define SAI_xCR1_CKSTR_Msk (0x1UL << SAI_xCR1_CKSTR_Pos)
11065#define SAI_xCR1_CKSTR SAI_xCR1_CKSTR_Msk
11067#define SAI_xCR1_SYNCEN_Pos (10U)
11068#define SAI_xCR1_SYNCEN_Msk (0x3UL << SAI_xCR1_SYNCEN_Pos)
11069#define SAI_xCR1_SYNCEN SAI_xCR1_SYNCEN_Msk
11070#define SAI_xCR1_SYNCEN_0 (0x1UL << SAI_xCR1_SYNCEN_Pos)
11071#define SAI_xCR1_SYNCEN_1 (0x2UL << SAI_xCR1_SYNCEN_Pos)
11073#define SAI_xCR1_MONO_Pos (12U)
11074#define SAI_xCR1_MONO_Msk (0x1UL << SAI_xCR1_MONO_Pos)
11075#define SAI_xCR1_MONO SAI_xCR1_MONO_Msk
11076#define SAI_xCR1_OUTDRIV_Pos (13U)
11077#define SAI_xCR1_OUTDRIV_Msk (0x1UL << SAI_xCR1_OUTDRIV_Pos)
11078#define SAI_xCR1_OUTDRIV SAI_xCR1_OUTDRIV_Msk
11079#define SAI_xCR1_SAIEN_Pos (16U)
11080#define SAI_xCR1_SAIEN_Msk (0x1UL << SAI_xCR1_SAIEN_Pos)
11081#define SAI_xCR1_SAIEN SAI_xCR1_SAIEN_Msk
11082#define SAI_xCR1_DMAEN_Pos (17U)
11083#define SAI_xCR1_DMAEN_Msk (0x1UL << SAI_xCR1_DMAEN_Pos)
11084#define SAI_xCR1_DMAEN SAI_xCR1_DMAEN_Msk
11085#define SAI_xCR1_NODIV_Pos (19U)
11086#define SAI_xCR1_NODIV_Msk (0x1UL << SAI_xCR1_NODIV_Pos)
11087#define SAI_xCR1_NODIV SAI_xCR1_NODIV_Msk
11089#define SAI_xCR1_MCKDIV_Pos (20U)
11090#define SAI_xCR1_MCKDIV_Msk (0xFUL << SAI_xCR1_MCKDIV_Pos)
11091#define SAI_xCR1_MCKDIV SAI_xCR1_MCKDIV_Msk
11092#define SAI_xCR1_MCKDIV_0 (0x1UL << SAI_xCR1_MCKDIV_Pos)
11093#define SAI_xCR1_MCKDIV_1 (0x2UL << SAI_xCR1_MCKDIV_Pos)
11094#define SAI_xCR1_MCKDIV_2 (0x4UL << SAI_xCR1_MCKDIV_Pos)
11095#define SAI_xCR1_MCKDIV_3 (0x8UL << SAI_xCR1_MCKDIV_Pos)
11097/******************* Bit definition for SAI_xCR2 register *******************/
11098#define SAI_xCR2_FTH_Pos (0U)
11099#define SAI_xCR2_FTH_Msk (0x7UL << SAI_xCR2_FTH_Pos)
11100#define SAI_xCR2_FTH SAI_xCR2_FTH_Msk
11101#define SAI_xCR2_FTH_0 (0x1UL << SAI_xCR2_FTH_Pos)
11102#define SAI_xCR2_FTH_1 (0x2UL << SAI_xCR2_FTH_Pos)
11103#define SAI_xCR2_FTH_2 (0x4UL << SAI_xCR2_FTH_Pos)
11105#define SAI_xCR2_FFLUSH_Pos (3U)
11106#define SAI_xCR2_FFLUSH_Msk (0x1UL << SAI_xCR2_FFLUSH_Pos)
11107#define SAI_xCR2_FFLUSH SAI_xCR2_FFLUSH_Msk
11108#define SAI_xCR2_TRIS_Pos (4U)
11109#define SAI_xCR2_TRIS_Msk (0x1UL << SAI_xCR2_TRIS_Pos)
11110#define SAI_xCR2_TRIS SAI_xCR2_TRIS_Msk
11111#define SAI_xCR2_MUTE_Pos (5U)
11112#define SAI_xCR2_MUTE_Msk (0x1UL << SAI_xCR2_MUTE_Pos)
11113#define SAI_xCR2_MUTE SAI_xCR2_MUTE_Msk
11114#define SAI_xCR2_MUTEVAL_Pos (6U)
11115#define SAI_xCR2_MUTEVAL_Msk (0x1UL << SAI_xCR2_MUTEVAL_Pos)
11116#define SAI_xCR2_MUTEVAL SAI_xCR2_MUTEVAL_Msk
11119#define SAI_xCR2_MUTECNT_Pos (7U)
11120#define SAI_xCR2_MUTECNT_Msk (0x3FUL << SAI_xCR2_MUTECNT_Pos)
11121#define SAI_xCR2_MUTECNT SAI_xCR2_MUTECNT_Msk
11122#define SAI_xCR2_MUTECNT_0 (0x01UL << SAI_xCR2_MUTECNT_Pos)
11123#define SAI_xCR2_MUTECNT_1 (0x02UL << SAI_xCR2_MUTECNT_Pos)
11124#define SAI_xCR2_MUTECNT_2 (0x04UL << SAI_xCR2_MUTECNT_Pos)
11125#define SAI_xCR2_MUTECNT_3 (0x08UL << SAI_xCR2_MUTECNT_Pos)
11126#define SAI_xCR2_MUTECNT_4 (0x10UL << SAI_xCR2_MUTECNT_Pos)
11127#define SAI_xCR2_MUTECNT_5 (0x20UL << SAI_xCR2_MUTECNT_Pos)
11129#define SAI_xCR2_CPL_Pos (13U)
11130#define SAI_xCR2_CPL_Msk (0x1UL << SAI_xCR2_CPL_Pos)
11131#define SAI_xCR2_CPL SAI_xCR2_CPL_Msk
11132#define SAI_xCR2_COMP_Pos (14U)
11133#define SAI_xCR2_COMP_Msk (0x3UL << SAI_xCR2_COMP_Pos)
11134#define SAI_xCR2_COMP SAI_xCR2_COMP_Msk
11135#define SAI_xCR2_COMP_0 (0x1UL << SAI_xCR2_COMP_Pos)
11136#define SAI_xCR2_COMP_1 (0x2UL << SAI_xCR2_COMP_Pos)
11139/****************** Bit definition for SAI_xFRCR register *******************/
11140#define SAI_xFRCR_FRL_Pos (0U)
11141#define SAI_xFRCR_FRL_Msk (0xFFUL << SAI_xFRCR_FRL_Pos)
11142#define SAI_xFRCR_FRL SAI_xFRCR_FRL_Msk
11143#define SAI_xFRCR_FRL_0 (0x01UL << SAI_xFRCR_FRL_Pos)
11144#define SAI_xFRCR_FRL_1 (0x02UL << SAI_xFRCR_FRL_Pos)
11145#define SAI_xFRCR_FRL_2 (0x04UL << SAI_xFRCR_FRL_Pos)
11146#define SAI_xFRCR_FRL_3 (0x08UL << SAI_xFRCR_FRL_Pos)
11147#define SAI_xFRCR_FRL_4 (0x10UL << SAI_xFRCR_FRL_Pos)
11148#define SAI_xFRCR_FRL_5 (0x20UL << SAI_xFRCR_FRL_Pos)
11149#define SAI_xFRCR_FRL_6 (0x40UL << SAI_xFRCR_FRL_Pos)
11150#define SAI_xFRCR_FRL_7 (0x80UL << SAI_xFRCR_FRL_Pos)
11152#define SAI_xFRCR_FSALL_Pos (8U)
11153#define SAI_xFRCR_FSALL_Msk (0x7FUL << SAI_xFRCR_FSALL_Pos)
11154#define SAI_xFRCR_FSALL SAI_xFRCR_FSALL_Msk
11155#define SAI_xFRCR_FSALL_0 (0x01UL << SAI_xFRCR_FSALL_Pos)
11156#define SAI_xFRCR_FSALL_1 (0x02UL << SAI_xFRCR_FSALL_Pos)
11157#define SAI_xFRCR_FSALL_2 (0x04UL << SAI_xFRCR_FSALL_Pos)
11158#define SAI_xFRCR_FSALL_3 (0x08UL << SAI_xFRCR_FSALL_Pos)
11159#define SAI_xFRCR_FSALL_4 (0x10UL << SAI_xFRCR_FSALL_Pos)
11160#define SAI_xFRCR_FSALL_5 (0x20UL << SAI_xFRCR_FSALL_Pos)
11161#define SAI_xFRCR_FSALL_6 (0x40UL << SAI_xFRCR_FSALL_Pos)
11163#define SAI_xFRCR_FSDEF_Pos (16U)
11164#define SAI_xFRCR_FSDEF_Msk (0x1UL << SAI_xFRCR_FSDEF_Pos)
11165#define SAI_xFRCR_FSDEF SAI_xFRCR_FSDEF_Msk
11166#define SAI_xFRCR_FSPOL_Pos (17U)
11167#define SAI_xFRCR_FSPOL_Msk (0x1UL << SAI_xFRCR_FSPOL_Pos)
11168#define SAI_xFRCR_FSPOL SAI_xFRCR_FSPOL_Msk
11169#define SAI_xFRCR_FSOFF_Pos (18U)
11170#define SAI_xFRCR_FSOFF_Msk (0x1UL << SAI_xFRCR_FSOFF_Pos)
11171#define SAI_xFRCR_FSOFF SAI_xFRCR_FSOFF_Msk
11173/****************** Bit definition for SAI_xSLOTR register *******************/
11174#define SAI_xSLOTR_FBOFF_Pos (0U)
11175#define SAI_xSLOTR_FBOFF_Msk (0x1FUL << SAI_xSLOTR_FBOFF_Pos)
11176#define SAI_xSLOTR_FBOFF SAI_xSLOTR_FBOFF_Msk
11177#define SAI_xSLOTR_FBOFF_0 (0x01UL << SAI_xSLOTR_FBOFF_Pos)
11178#define SAI_xSLOTR_FBOFF_1 (0x02UL << SAI_xSLOTR_FBOFF_Pos)
11179#define SAI_xSLOTR_FBOFF_2 (0x04UL << SAI_xSLOTR_FBOFF_Pos)
11180#define SAI_xSLOTR_FBOFF_3 (0x08UL << SAI_xSLOTR_FBOFF_Pos)
11181#define SAI_xSLOTR_FBOFF_4 (0x10UL << SAI_xSLOTR_FBOFF_Pos)
11183#define SAI_xSLOTR_SLOTSZ_Pos (6U)
11184#define SAI_xSLOTR_SLOTSZ_Msk (0x3UL << SAI_xSLOTR_SLOTSZ_Pos)
11185#define SAI_xSLOTR_SLOTSZ SAI_xSLOTR_SLOTSZ_Msk
11186#define SAI_xSLOTR_SLOTSZ_0 (0x1UL << SAI_xSLOTR_SLOTSZ_Pos)
11187#define SAI_xSLOTR_SLOTSZ_1 (0x2UL << SAI_xSLOTR_SLOTSZ_Pos)
11189#define SAI_xSLOTR_NBSLOT_Pos (8U)
11190#define SAI_xSLOTR_NBSLOT_Msk (0xFUL << SAI_xSLOTR_NBSLOT_Pos)
11191#define SAI_xSLOTR_NBSLOT SAI_xSLOTR_NBSLOT_Msk
11192#define SAI_xSLOTR_NBSLOT_0 (0x1UL << SAI_xSLOTR_NBSLOT_Pos)
11193#define SAI_xSLOTR_NBSLOT_1 (0x2UL << SAI_xSLOTR_NBSLOT_Pos)
11194#define SAI_xSLOTR_NBSLOT_2 (0x4UL << SAI_xSLOTR_NBSLOT_Pos)
11195#define SAI_xSLOTR_NBSLOT_3 (0x8UL << SAI_xSLOTR_NBSLOT_Pos)
11197#define SAI_xSLOTR_SLOTEN_Pos (16U)
11198#define SAI_xSLOTR_SLOTEN_Msk (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos)
11199#define SAI_xSLOTR_SLOTEN SAI_xSLOTR_SLOTEN_Msk
11201/******************* Bit definition for SAI_xIMR register *******************/
11202#define SAI_xIMR_OVRUDRIE_Pos (0U)
11203#define SAI_xIMR_OVRUDRIE_Msk (0x1UL << SAI_xIMR_OVRUDRIE_Pos)
11204#define SAI_xIMR_OVRUDRIE SAI_xIMR_OVRUDRIE_Msk
11205#define SAI_xIMR_MUTEDETIE_Pos (1U)
11206#define SAI_xIMR_MUTEDETIE_Msk (0x1UL << SAI_xIMR_MUTEDETIE_Pos)
11207#define SAI_xIMR_MUTEDETIE SAI_xIMR_MUTEDETIE_Msk
11208#define SAI_xIMR_WCKCFGIE_Pos (2U)
11209#define SAI_xIMR_WCKCFGIE_Msk (0x1UL << SAI_xIMR_WCKCFGIE_Pos)
11210#define SAI_xIMR_WCKCFGIE SAI_xIMR_WCKCFGIE_Msk
11211#define SAI_xIMR_FREQIE_Pos (3U)
11212#define SAI_xIMR_FREQIE_Msk (0x1UL << SAI_xIMR_FREQIE_Pos)
11213#define SAI_xIMR_FREQIE SAI_xIMR_FREQIE_Msk
11214#define SAI_xIMR_CNRDYIE_Pos (4U)
11215#define SAI_xIMR_CNRDYIE_Msk (0x1UL << SAI_xIMR_CNRDYIE_Pos)
11216#define SAI_xIMR_CNRDYIE SAI_xIMR_CNRDYIE_Msk
11217#define SAI_xIMR_AFSDETIE_Pos (5U)
11218#define SAI_xIMR_AFSDETIE_Msk (0x1UL << SAI_xIMR_AFSDETIE_Pos)
11219#define SAI_xIMR_AFSDETIE SAI_xIMR_AFSDETIE_Msk
11220#define SAI_xIMR_LFSDETIE_Pos (6U)
11221#define SAI_xIMR_LFSDETIE_Msk (0x1UL << SAI_xIMR_LFSDETIE_Pos)
11222#define SAI_xIMR_LFSDETIE SAI_xIMR_LFSDETIE_Msk
11224/******************** Bit definition for SAI_xSR register *******************/
11225#define SAI_xSR_OVRUDR_Pos (0U)
11226#define SAI_xSR_OVRUDR_Msk (0x1UL << SAI_xSR_OVRUDR_Pos)
11227#define SAI_xSR_OVRUDR SAI_xSR_OVRUDR_Msk
11228#define SAI_xSR_MUTEDET_Pos (1U)
11229#define SAI_xSR_MUTEDET_Msk (0x1UL << SAI_xSR_MUTEDET_Pos)
11230#define SAI_xSR_MUTEDET SAI_xSR_MUTEDET_Msk
11231#define SAI_xSR_WCKCFG_Pos (2U)
11232#define SAI_xSR_WCKCFG_Msk (0x1UL << SAI_xSR_WCKCFG_Pos)
11233#define SAI_xSR_WCKCFG SAI_xSR_WCKCFG_Msk
11234#define SAI_xSR_FREQ_Pos (3U)
11235#define SAI_xSR_FREQ_Msk (0x1UL << SAI_xSR_FREQ_Pos)
11236#define SAI_xSR_FREQ SAI_xSR_FREQ_Msk
11237#define SAI_xSR_CNRDY_Pos (4U)
11238#define SAI_xSR_CNRDY_Msk (0x1UL << SAI_xSR_CNRDY_Pos)
11239#define SAI_xSR_CNRDY SAI_xSR_CNRDY_Msk
11240#define SAI_xSR_AFSDET_Pos (5U)
11241#define SAI_xSR_AFSDET_Msk (0x1UL << SAI_xSR_AFSDET_Pos)
11242#define SAI_xSR_AFSDET SAI_xSR_AFSDET_Msk
11243#define SAI_xSR_LFSDET_Pos (6U)
11244#define SAI_xSR_LFSDET_Msk (0x1UL << SAI_xSR_LFSDET_Pos)
11245#define SAI_xSR_LFSDET SAI_xSR_LFSDET_Msk
11247#define SAI_xSR_FLVL_Pos (16U)
11248#define SAI_xSR_FLVL_Msk (0x7UL << SAI_xSR_FLVL_Pos)
11249#define SAI_xSR_FLVL SAI_xSR_FLVL_Msk
11250#define SAI_xSR_FLVL_0 (0x1UL << SAI_xSR_FLVL_Pos)
11251#define SAI_xSR_FLVL_1 (0x2UL << SAI_xSR_FLVL_Pos)
11252#define SAI_xSR_FLVL_2 (0x4UL << SAI_xSR_FLVL_Pos)
11254/****************** Bit definition for SAI_xCLRFR register ******************/
11255#define SAI_xCLRFR_COVRUDR_Pos (0U)
11256#define SAI_xCLRFR_COVRUDR_Msk (0x1UL << SAI_xCLRFR_COVRUDR_Pos)
11257#define SAI_xCLRFR_COVRUDR SAI_xCLRFR_COVRUDR_Msk
11258#define SAI_xCLRFR_CMUTEDET_Pos (1U)
11259#define SAI_xCLRFR_CMUTEDET_Msk (0x1UL << SAI_xCLRFR_CMUTEDET_Pos)
11260#define SAI_xCLRFR_CMUTEDET SAI_xCLRFR_CMUTEDET_Msk
11261#define SAI_xCLRFR_CWCKCFG_Pos (2U)
11262#define SAI_xCLRFR_CWCKCFG_Msk (0x1UL << SAI_xCLRFR_CWCKCFG_Pos)
11263#define SAI_xCLRFR_CWCKCFG SAI_xCLRFR_CWCKCFG_Msk
11264#define SAI_xCLRFR_CFREQ_Pos (3U)
11265#define SAI_xCLRFR_CFREQ_Msk (0x1UL << SAI_xCLRFR_CFREQ_Pos)
11266#define SAI_xCLRFR_CFREQ SAI_xCLRFR_CFREQ_Msk
11267#define SAI_xCLRFR_CCNRDY_Pos (4U)
11268#define SAI_xCLRFR_CCNRDY_Msk (0x1UL << SAI_xCLRFR_CCNRDY_Pos)
11269#define SAI_xCLRFR_CCNRDY SAI_xCLRFR_CCNRDY_Msk
11270#define SAI_xCLRFR_CAFSDET_Pos (5U)
11271#define SAI_xCLRFR_CAFSDET_Msk (0x1UL << SAI_xCLRFR_CAFSDET_Pos)
11272#define SAI_xCLRFR_CAFSDET SAI_xCLRFR_CAFSDET_Msk
11273#define SAI_xCLRFR_CLFSDET_Pos (6U)
11274#define SAI_xCLRFR_CLFSDET_Msk (0x1UL << SAI_xCLRFR_CLFSDET_Pos)
11275#define SAI_xCLRFR_CLFSDET SAI_xCLRFR_CLFSDET_Msk
11277/****************** Bit definition for SAI_xDR register ******************/
11278#define SAI_xDR_DATA_Pos (0U)
11279#define SAI_xDR_DATA_Msk (0xFFFFFFFFUL << SAI_xDR_DATA_Pos)
11280#define SAI_xDR_DATA SAI_xDR_DATA_Msk
11281
11282/******************************************************************************/
11283/* */
11284/* SDMMC Interface */
11285/* */
11286/******************************************************************************/
11287/****************** Bit definition for SDMMC_POWER register ******************/
11288#define SDMMC_POWER_PWRCTRL_Pos (0U)
11289#define SDMMC_POWER_PWRCTRL_Msk (0x3UL << SDMMC_POWER_PWRCTRL_Pos)
11290#define SDMMC_POWER_PWRCTRL SDMMC_POWER_PWRCTRL_Msk
11291#define SDMMC_POWER_PWRCTRL_0 (0x1UL << SDMMC_POWER_PWRCTRL_Pos)
11292#define SDMMC_POWER_PWRCTRL_1 (0x2UL << SDMMC_POWER_PWRCTRL_Pos)
11294/****************** Bit definition for SDMMC_CLKCR register ******************/
11295#define SDMMC_CLKCR_CLKDIV_Pos (0U)
11296#define SDMMC_CLKCR_CLKDIV_Msk (0xFFUL << SDMMC_CLKCR_CLKDIV_Pos)
11297#define SDMMC_CLKCR_CLKDIV SDMMC_CLKCR_CLKDIV_Msk
11298#define SDMMC_CLKCR_CLKEN_Pos (8U)
11299#define SDMMC_CLKCR_CLKEN_Msk (0x1UL << SDMMC_CLKCR_CLKEN_Pos)
11300#define SDMMC_CLKCR_CLKEN SDMMC_CLKCR_CLKEN_Msk
11301#define SDMMC_CLKCR_PWRSAV_Pos (9U)
11302#define SDMMC_CLKCR_PWRSAV_Msk (0x1UL << SDMMC_CLKCR_PWRSAV_Pos)
11303#define SDMMC_CLKCR_PWRSAV SDMMC_CLKCR_PWRSAV_Msk
11304#define SDMMC_CLKCR_BYPASS_Pos (10U)
11305#define SDMMC_CLKCR_BYPASS_Msk (0x1UL << SDMMC_CLKCR_BYPASS_Pos)
11306#define SDMMC_CLKCR_BYPASS SDMMC_CLKCR_BYPASS_Msk
11308#define SDMMC_CLKCR_WIDBUS_Pos (11U)
11309#define SDMMC_CLKCR_WIDBUS_Msk (0x3UL << SDMMC_CLKCR_WIDBUS_Pos)
11310#define SDMMC_CLKCR_WIDBUS SDMMC_CLKCR_WIDBUS_Msk
11311#define SDMMC_CLKCR_WIDBUS_0 (0x1UL << SDMMC_CLKCR_WIDBUS_Pos)
11312#define SDMMC_CLKCR_WIDBUS_1 (0x2UL << SDMMC_CLKCR_WIDBUS_Pos)
11314#define SDMMC_CLKCR_NEGEDGE_Pos (13U)
11315#define SDMMC_CLKCR_NEGEDGE_Msk (0x1UL << SDMMC_CLKCR_NEGEDGE_Pos)
11316#define SDMMC_CLKCR_NEGEDGE SDMMC_CLKCR_NEGEDGE_Msk
11317#define SDMMC_CLKCR_HWFC_EN_Pos (14U)
11318#define SDMMC_CLKCR_HWFC_EN_Msk (0x1UL << SDMMC_CLKCR_HWFC_EN_Pos)
11319#define SDMMC_CLKCR_HWFC_EN SDMMC_CLKCR_HWFC_EN_Msk
11321/******************* Bit definition for SDMMC_ARG register *******************/
11322#define SDMMC_ARG_CMDARG_Pos (0U)
11323#define SDMMC_ARG_CMDARG_Msk (0xFFFFFFFFUL << SDMMC_ARG_CMDARG_Pos)
11324#define SDMMC_ARG_CMDARG SDMMC_ARG_CMDARG_Msk
11326/******************* Bit definition for SDMMC_CMD register *******************/
11327#define SDMMC_CMD_CMDINDEX_Pos (0U)
11328#define SDMMC_CMD_CMDINDEX_Msk (0x3FUL << SDMMC_CMD_CMDINDEX_Pos)
11329#define SDMMC_CMD_CMDINDEX SDMMC_CMD_CMDINDEX_Msk
11331#define SDMMC_CMD_WAITRESP_Pos (6U)
11332#define SDMMC_CMD_WAITRESP_Msk (0x3UL << SDMMC_CMD_WAITRESP_Pos)
11333#define SDMMC_CMD_WAITRESP SDMMC_CMD_WAITRESP_Msk
11334#define SDMMC_CMD_WAITRESP_0 (0x1UL << SDMMC_CMD_WAITRESP_Pos)
11335#define SDMMC_CMD_WAITRESP_1 (0x2UL << SDMMC_CMD_WAITRESP_Pos)
11337#define SDMMC_CMD_WAITINT_Pos (8U)
11338#define SDMMC_CMD_WAITINT_Msk (0x1UL << SDMMC_CMD_WAITINT_Pos)
11339#define SDMMC_CMD_WAITINT SDMMC_CMD_WAITINT_Msk
11340#define SDMMC_CMD_WAITPEND_Pos (9U)
11341#define SDMMC_CMD_WAITPEND_Msk (0x1UL << SDMMC_CMD_WAITPEND_Pos)
11342#define SDMMC_CMD_WAITPEND SDMMC_CMD_WAITPEND_Msk
11343#define SDMMC_CMD_CPSMEN_Pos (10U)
11344#define SDMMC_CMD_CPSMEN_Msk (0x1UL << SDMMC_CMD_CPSMEN_Pos)
11345#define SDMMC_CMD_CPSMEN SDMMC_CMD_CPSMEN_Msk
11346#define SDMMC_CMD_SDIOSUSPEND_Pos (11U)
11347#define SDMMC_CMD_SDIOSUSPEND_Msk (0x1UL << SDMMC_CMD_SDIOSUSPEND_Pos)
11348#define SDMMC_CMD_SDIOSUSPEND SDMMC_CMD_SDIOSUSPEND_Msk
11350/***************** Bit definition for SDMMC_RESPCMD register *****************/
11351#define SDMMC_RESPCMD_RESPCMD_Pos (0U)
11352#define SDMMC_RESPCMD_RESPCMD_Msk (0x3FUL << SDMMC_RESPCMD_RESPCMD_Pos)
11353#define SDMMC_RESPCMD_RESPCMD SDMMC_RESPCMD_RESPCMD_Msk
11355/****************** Bit definition for SDMMC_RESP1 register ******************/
11356#define SDMMC_RESP1_CARDSTATUS1_Pos (0U)
11357#define SDMMC_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFUL << SDMMC_RESP1_CARDSTATUS1_Pos)
11358#define SDMMC_RESP1_CARDSTATUS1 SDMMC_RESP1_CARDSTATUS1_Msk
11360/****************** Bit definition for SDMMC_RESP2 register ******************/
11361#define SDMMC_RESP2_CARDSTATUS2_Pos (0U)
11362#define SDMMC_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFUL << SDMMC_RESP2_CARDSTATUS2_Pos)
11363#define SDMMC_RESP2_CARDSTATUS2 SDMMC_RESP2_CARDSTATUS2_Msk
11365/****************** Bit definition for SDMMC_RESP3 register ******************/
11366#define SDMMC_RESP3_CARDSTATUS3_Pos (0U)
11367#define SDMMC_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFUL << SDMMC_RESP3_CARDSTATUS3_Pos)
11368#define SDMMC_RESP3_CARDSTATUS3 SDMMC_RESP3_CARDSTATUS3_Msk
11370/****************** Bit definition for SDMMC_RESP4 register ******************/
11371#define SDMMC_RESP4_CARDSTATUS4_Pos (0U)
11372#define SDMMC_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFUL << SDMMC_RESP4_CARDSTATUS4_Pos)
11373#define SDMMC_RESP4_CARDSTATUS4 SDMMC_RESP4_CARDSTATUS4_Msk
11375/****************** Bit definition for SDMMC_DTIMER register *****************/
11376#define SDMMC_DTIMER_DATATIME_Pos (0U)
11377#define SDMMC_DTIMER_DATATIME_Msk (0xFFFFFFFFUL << SDMMC_DTIMER_DATATIME_Pos)
11378#define SDMMC_DTIMER_DATATIME SDMMC_DTIMER_DATATIME_Msk
11380/****************** Bit definition for SDMMC_DLEN register *******************/
11381#define SDMMC_DLEN_DATALENGTH_Pos (0U)
11382#define SDMMC_DLEN_DATALENGTH_Msk (0x1FFFFFFUL << SDMMC_DLEN_DATALENGTH_Pos)
11383#define SDMMC_DLEN_DATALENGTH SDMMC_DLEN_DATALENGTH_Msk
11385/****************** Bit definition for SDMMC_DCTRL register ******************/
11386#define SDMMC_DCTRL_DTEN_Pos (0U)
11387#define SDMMC_DCTRL_DTEN_Msk (0x1UL << SDMMC_DCTRL_DTEN_Pos)
11388#define SDMMC_DCTRL_DTEN SDMMC_DCTRL_DTEN_Msk
11389#define SDMMC_DCTRL_DTDIR_Pos (1U)
11390#define SDMMC_DCTRL_DTDIR_Msk (0x1UL << SDMMC_DCTRL_DTDIR_Pos)
11391#define SDMMC_DCTRL_DTDIR SDMMC_DCTRL_DTDIR_Msk
11392#define SDMMC_DCTRL_DTMODE_Pos (2U)
11393#define SDMMC_DCTRL_DTMODE_Msk (0x1UL << SDMMC_DCTRL_DTMODE_Pos)
11394#define SDMMC_DCTRL_DTMODE SDMMC_DCTRL_DTMODE_Msk
11395#define SDMMC_DCTRL_DMAEN_Pos (3U)
11396#define SDMMC_DCTRL_DMAEN_Msk (0x1UL << SDMMC_DCTRL_DMAEN_Pos)
11397#define SDMMC_DCTRL_DMAEN SDMMC_DCTRL_DMAEN_Msk
11399#define SDMMC_DCTRL_DBLOCKSIZE_Pos (4U)
11400#define SDMMC_DCTRL_DBLOCKSIZE_Msk (0xFUL << SDMMC_DCTRL_DBLOCKSIZE_Pos)
11401#define SDMMC_DCTRL_DBLOCKSIZE SDMMC_DCTRL_DBLOCKSIZE_Msk
11402#define SDMMC_DCTRL_DBLOCKSIZE_0 (0x1UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)
11403#define SDMMC_DCTRL_DBLOCKSIZE_1 (0x2UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)
11404#define SDMMC_DCTRL_DBLOCKSIZE_2 (0x4UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)
11405#define SDMMC_DCTRL_DBLOCKSIZE_3 (0x8UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)
11407#define SDMMC_DCTRL_RWSTART_Pos (8U)
11408#define SDMMC_DCTRL_RWSTART_Msk (0x1UL << SDMMC_DCTRL_RWSTART_Pos)
11409#define SDMMC_DCTRL_RWSTART SDMMC_DCTRL_RWSTART_Msk
11410#define SDMMC_DCTRL_RWSTOP_Pos (9U)
11411#define SDMMC_DCTRL_RWSTOP_Msk (0x1UL << SDMMC_DCTRL_RWSTOP_Pos)
11412#define SDMMC_DCTRL_RWSTOP SDMMC_DCTRL_RWSTOP_Msk
11413#define SDMMC_DCTRL_RWMOD_Pos (10U)
11414#define SDMMC_DCTRL_RWMOD_Msk (0x1UL << SDMMC_DCTRL_RWMOD_Pos)
11415#define SDMMC_DCTRL_RWMOD SDMMC_DCTRL_RWMOD_Msk
11416#define SDMMC_DCTRL_SDIOEN_Pos (11U)
11417#define SDMMC_DCTRL_SDIOEN_Msk (0x1UL << SDMMC_DCTRL_SDIOEN_Pos)
11418#define SDMMC_DCTRL_SDIOEN SDMMC_DCTRL_SDIOEN_Msk
11420/****************** Bit definition for SDMMC_DCOUNT register *****************/
11421#define SDMMC_DCOUNT_DATACOUNT_Pos (0U)
11422#define SDMMC_DCOUNT_DATACOUNT_Msk (0x1FFFFFFUL << SDMMC_DCOUNT_DATACOUNT_Pos)
11423#define SDMMC_DCOUNT_DATACOUNT SDMMC_DCOUNT_DATACOUNT_Msk
11425/****************** Bit definition for SDMMC_STA register ********************/
11426#define SDMMC_STA_CCRCFAIL_Pos (0U)
11427#define SDMMC_STA_CCRCFAIL_Msk (0x1UL << SDMMC_STA_CCRCFAIL_Pos)
11428#define SDMMC_STA_CCRCFAIL SDMMC_STA_CCRCFAIL_Msk
11429#define SDMMC_STA_DCRCFAIL_Pos (1U)
11430#define SDMMC_STA_DCRCFAIL_Msk (0x1UL << SDMMC_STA_DCRCFAIL_Pos)
11431#define SDMMC_STA_DCRCFAIL SDMMC_STA_DCRCFAIL_Msk
11432#define SDMMC_STA_CTIMEOUT_Pos (2U)
11433#define SDMMC_STA_CTIMEOUT_Msk (0x1UL << SDMMC_STA_CTIMEOUT_Pos)
11434#define SDMMC_STA_CTIMEOUT SDMMC_STA_CTIMEOUT_Msk
11435#define SDMMC_STA_DTIMEOUT_Pos (3U)
11436#define SDMMC_STA_DTIMEOUT_Msk (0x1UL << SDMMC_STA_DTIMEOUT_Pos)
11437#define SDMMC_STA_DTIMEOUT SDMMC_STA_DTIMEOUT_Msk
11438#define SDMMC_STA_TXUNDERR_Pos (4U)
11439#define SDMMC_STA_TXUNDERR_Msk (0x1UL << SDMMC_STA_TXUNDERR_Pos)
11440#define SDMMC_STA_TXUNDERR SDMMC_STA_TXUNDERR_Msk
11441#define SDMMC_STA_RXOVERR_Pos (5U)
11442#define SDMMC_STA_RXOVERR_Msk (0x1UL << SDMMC_STA_RXOVERR_Pos)
11443#define SDMMC_STA_RXOVERR SDMMC_STA_RXOVERR_Msk
11444#define SDMMC_STA_CMDREND_Pos (6U)
11445#define SDMMC_STA_CMDREND_Msk (0x1UL << SDMMC_STA_CMDREND_Pos)
11446#define SDMMC_STA_CMDREND SDMMC_STA_CMDREND_Msk
11447#define SDMMC_STA_CMDSENT_Pos (7U)
11448#define SDMMC_STA_CMDSENT_Msk (0x1UL << SDMMC_STA_CMDSENT_Pos)
11449#define SDMMC_STA_CMDSENT SDMMC_STA_CMDSENT_Msk
11450#define SDMMC_STA_DATAEND_Pos (8U)
11451#define SDMMC_STA_DATAEND_Msk (0x1UL << SDMMC_STA_DATAEND_Pos)
11452#define SDMMC_STA_DATAEND SDMMC_STA_DATAEND_Msk
11453#define SDMMC_STA_STBITERR_Pos (9U)
11454#define SDMMC_STA_STBITERR_Msk (0x1UL << SDMMC_STA_STBITERR_Pos)
11455#define SDMMC_STA_STBITERR SDMMC_STA_STBITERR_Msk
11456#define SDMMC_STA_DBCKEND_Pos (10U)
11457#define SDMMC_STA_DBCKEND_Msk (0x1UL << SDMMC_STA_DBCKEND_Pos)
11458#define SDMMC_STA_DBCKEND SDMMC_STA_DBCKEND_Msk
11459#define SDMMC_STA_CMDACT_Pos (11U)
11460#define SDMMC_STA_CMDACT_Msk (0x1UL << SDMMC_STA_CMDACT_Pos)
11461#define SDMMC_STA_CMDACT SDMMC_STA_CMDACT_Msk
11462#define SDMMC_STA_TXACT_Pos (12U)
11463#define SDMMC_STA_TXACT_Msk (0x1UL << SDMMC_STA_TXACT_Pos)
11464#define SDMMC_STA_TXACT SDMMC_STA_TXACT_Msk
11465#define SDMMC_STA_RXACT_Pos (13U)
11466#define SDMMC_STA_RXACT_Msk (0x1UL << SDMMC_STA_RXACT_Pos)
11467#define SDMMC_STA_RXACT SDMMC_STA_RXACT_Msk
11468#define SDMMC_STA_TXFIFOHE_Pos (14U)
11469#define SDMMC_STA_TXFIFOHE_Msk (0x1UL << SDMMC_STA_TXFIFOHE_Pos)
11470#define SDMMC_STA_TXFIFOHE SDMMC_STA_TXFIFOHE_Msk
11471#define SDMMC_STA_RXFIFOHF_Pos (15U)
11472#define SDMMC_STA_RXFIFOHF_Msk (0x1UL << SDMMC_STA_RXFIFOHF_Pos)
11473#define SDMMC_STA_RXFIFOHF SDMMC_STA_RXFIFOHF_Msk
11474#define SDMMC_STA_TXFIFOF_Pos (16U)
11475#define SDMMC_STA_TXFIFOF_Msk (0x1UL << SDMMC_STA_TXFIFOF_Pos)
11476#define SDMMC_STA_TXFIFOF SDMMC_STA_TXFIFOF_Msk
11477#define SDMMC_STA_RXFIFOF_Pos (17U)
11478#define SDMMC_STA_RXFIFOF_Msk (0x1UL << SDMMC_STA_RXFIFOF_Pos)
11479#define SDMMC_STA_RXFIFOF SDMMC_STA_RXFIFOF_Msk
11480#define SDMMC_STA_TXFIFOE_Pos (18U)
11481#define SDMMC_STA_TXFIFOE_Msk (0x1UL << SDMMC_STA_TXFIFOE_Pos)
11482#define SDMMC_STA_TXFIFOE SDMMC_STA_TXFIFOE_Msk
11483#define SDMMC_STA_RXFIFOE_Pos (19U)
11484#define SDMMC_STA_RXFIFOE_Msk (0x1UL << SDMMC_STA_RXFIFOE_Pos)
11485#define SDMMC_STA_RXFIFOE SDMMC_STA_RXFIFOE_Msk
11486#define SDMMC_STA_TXDAVL_Pos (20U)
11487#define SDMMC_STA_TXDAVL_Msk (0x1UL << SDMMC_STA_TXDAVL_Pos)
11488#define SDMMC_STA_TXDAVL SDMMC_STA_TXDAVL_Msk
11489#define SDMMC_STA_RXDAVL_Pos (21U)
11490#define SDMMC_STA_RXDAVL_Msk (0x1UL << SDMMC_STA_RXDAVL_Pos)
11491#define SDMMC_STA_RXDAVL SDMMC_STA_RXDAVL_Msk
11492#define SDMMC_STA_SDIOIT_Pos (22U)
11493#define SDMMC_STA_SDIOIT_Msk (0x1UL << SDMMC_STA_SDIOIT_Pos)
11494#define SDMMC_STA_SDIOIT SDMMC_STA_SDIOIT_Msk
11496/******************* Bit definition for SDMMC_ICR register *******************/
11497#define SDMMC_ICR_CCRCFAILC_Pos (0U)
11498#define SDMMC_ICR_CCRCFAILC_Msk (0x1UL << SDMMC_ICR_CCRCFAILC_Pos)
11499#define SDMMC_ICR_CCRCFAILC SDMMC_ICR_CCRCFAILC_Msk
11500#define SDMMC_ICR_DCRCFAILC_Pos (1U)
11501#define SDMMC_ICR_DCRCFAILC_Msk (0x1UL << SDMMC_ICR_DCRCFAILC_Pos)
11502#define SDMMC_ICR_DCRCFAILC SDMMC_ICR_DCRCFAILC_Msk
11503#define SDMMC_ICR_CTIMEOUTC_Pos (2U)
11504#define SDMMC_ICR_CTIMEOUTC_Msk (0x1UL << SDMMC_ICR_CTIMEOUTC_Pos)
11505#define SDMMC_ICR_CTIMEOUTC SDMMC_ICR_CTIMEOUTC_Msk
11506#define SDMMC_ICR_DTIMEOUTC_Pos (3U)
11507#define SDMMC_ICR_DTIMEOUTC_Msk (0x1UL << SDMMC_ICR_DTIMEOUTC_Pos)
11508#define SDMMC_ICR_DTIMEOUTC SDMMC_ICR_DTIMEOUTC_Msk
11509#define SDMMC_ICR_TXUNDERRC_Pos (4U)
11510#define SDMMC_ICR_TXUNDERRC_Msk (0x1UL << SDMMC_ICR_TXUNDERRC_Pos)
11511#define SDMMC_ICR_TXUNDERRC SDMMC_ICR_TXUNDERRC_Msk
11512#define SDMMC_ICR_RXOVERRC_Pos (5U)
11513#define SDMMC_ICR_RXOVERRC_Msk (0x1UL << SDMMC_ICR_RXOVERRC_Pos)
11514#define SDMMC_ICR_RXOVERRC SDMMC_ICR_RXOVERRC_Msk
11515#define SDMMC_ICR_CMDRENDC_Pos (6U)
11516#define SDMMC_ICR_CMDRENDC_Msk (0x1UL << SDMMC_ICR_CMDRENDC_Pos)
11517#define SDMMC_ICR_CMDRENDC SDMMC_ICR_CMDRENDC_Msk
11518#define SDMMC_ICR_CMDSENTC_Pos (7U)
11519#define SDMMC_ICR_CMDSENTC_Msk (0x1UL << SDMMC_ICR_CMDSENTC_Pos)
11520#define SDMMC_ICR_CMDSENTC SDMMC_ICR_CMDSENTC_Msk
11521#define SDMMC_ICR_DATAENDC_Pos (8U)
11522#define SDMMC_ICR_DATAENDC_Msk (0x1UL << SDMMC_ICR_DATAENDC_Pos)
11523#define SDMMC_ICR_DATAENDC SDMMC_ICR_DATAENDC_Msk
11524#define SDMMC_ICR_STBITERRC_Pos (9U)
11525#define SDMMC_ICR_STBITERRC_Msk (0x1UL << SDMMC_ICR_STBITERRC_Pos)
11526#define SDMMC_ICR_STBITERRC SDMMC_ICR_STBITERRC_Msk
11527#define SDMMC_ICR_DBCKENDC_Pos (10U)
11528#define SDMMC_ICR_DBCKENDC_Msk (0x1UL << SDMMC_ICR_DBCKENDC_Pos)
11529#define SDMMC_ICR_DBCKENDC SDMMC_ICR_DBCKENDC_Msk
11530#define SDMMC_ICR_SDIOITC_Pos (22U)
11531#define SDMMC_ICR_SDIOITC_Msk (0x1UL << SDMMC_ICR_SDIOITC_Pos)
11532#define SDMMC_ICR_SDIOITC SDMMC_ICR_SDIOITC_Msk
11534/****************** Bit definition for SDMMC_MASK register *******************/
11535#define SDMMC_MASK_CCRCFAILIE_Pos (0U)
11536#define SDMMC_MASK_CCRCFAILIE_Msk (0x1UL << SDMMC_MASK_CCRCFAILIE_Pos)
11537#define SDMMC_MASK_CCRCFAILIE SDMMC_MASK_CCRCFAILIE_Msk
11538#define SDMMC_MASK_DCRCFAILIE_Pos (1U)
11539#define SDMMC_MASK_DCRCFAILIE_Msk (0x1UL << SDMMC_MASK_DCRCFAILIE_Pos)
11540#define SDMMC_MASK_DCRCFAILIE SDMMC_MASK_DCRCFAILIE_Msk
11541#define SDMMC_MASK_CTIMEOUTIE_Pos (2U)
11542#define SDMMC_MASK_CTIMEOUTIE_Msk (0x1UL << SDMMC_MASK_CTIMEOUTIE_Pos)
11543#define SDMMC_MASK_CTIMEOUTIE SDMMC_MASK_CTIMEOUTIE_Msk
11544#define SDMMC_MASK_DTIMEOUTIE_Pos (3U)
11545#define SDMMC_MASK_DTIMEOUTIE_Msk (0x1UL << SDMMC_MASK_DTIMEOUTIE_Pos)
11546#define SDMMC_MASK_DTIMEOUTIE SDMMC_MASK_DTIMEOUTIE_Msk
11547#define SDMMC_MASK_TXUNDERRIE_Pos (4U)
11548#define SDMMC_MASK_TXUNDERRIE_Msk (0x1UL << SDMMC_MASK_TXUNDERRIE_Pos)
11549#define SDMMC_MASK_TXUNDERRIE SDMMC_MASK_TXUNDERRIE_Msk
11550#define SDMMC_MASK_RXOVERRIE_Pos (5U)
11551#define SDMMC_MASK_RXOVERRIE_Msk (0x1UL << SDMMC_MASK_RXOVERRIE_Pos)
11552#define SDMMC_MASK_RXOVERRIE SDMMC_MASK_RXOVERRIE_Msk
11553#define SDMMC_MASK_CMDRENDIE_Pos (6U)
11554#define SDMMC_MASK_CMDRENDIE_Msk (0x1UL << SDMMC_MASK_CMDRENDIE_Pos)
11555#define SDMMC_MASK_CMDRENDIE SDMMC_MASK_CMDRENDIE_Msk
11556#define SDMMC_MASK_CMDSENTIE_Pos (7U)
11557#define SDMMC_MASK_CMDSENTIE_Msk (0x1UL << SDMMC_MASK_CMDSENTIE_Pos)
11558#define SDMMC_MASK_CMDSENTIE SDMMC_MASK_CMDSENTIE_Msk
11559#define SDMMC_MASK_DATAENDIE_Pos (8U)
11560#define SDMMC_MASK_DATAENDIE_Msk (0x1UL << SDMMC_MASK_DATAENDIE_Pos)
11561#define SDMMC_MASK_DATAENDIE SDMMC_MASK_DATAENDIE_Msk
11562#define SDMMC_MASK_DBCKENDIE_Pos (10U)
11563#define SDMMC_MASK_DBCKENDIE_Msk (0x1UL << SDMMC_MASK_DBCKENDIE_Pos)
11564#define SDMMC_MASK_DBCKENDIE SDMMC_MASK_DBCKENDIE_Msk
11565#define SDMMC_MASK_CMDACTIE_Pos (11U)
11566#define SDMMC_MASK_CMDACTIE_Msk (0x1UL << SDMMC_MASK_CMDACTIE_Pos)
11567#define SDMMC_MASK_CMDACTIE SDMMC_MASK_CMDACTIE_Msk
11568#define SDMMC_MASK_TXACTIE_Pos (12U)
11569#define SDMMC_MASK_TXACTIE_Msk (0x1UL << SDMMC_MASK_TXACTIE_Pos)
11570#define SDMMC_MASK_TXACTIE SDMMC_MASK_TXACTIE_Msk
11571#define SDMMC_MASK_RXACTIE_Pos (13U)
11572#define SDMMC_MASK_RXACTIE_Msk (0x1UL << SDMMC_MASK_RXACTIE_Pos)
11573#define SDMMC_MASK_RXACTIE SDMMC_MASK_RXACTIE_Msk
11574#define SDMMC_MASK_TXFIFOHEIE_Pos (14U)
11575#define SDMMC_MASK_TXFIFOHEIE_Msk (0x1UL << SDMMC_MASK_TXFIFOHEIE_Pos)
11576#define SDMMC_MASK_TXFIFOHEIE SDMMC_MASK_TXFIFOHEIE_Msk
11577#define SDMMC_MASK_RXFIFOHFIE_Pos (15U)
11578#define SDMMC_MASK_RXFIFOHFIE_Msk (0x1UL << SDMMC_MASK_RXFIFOHFIE_Pos)
11579#define SDMMC_MASK_RXFIFOHFIE SDMMC_MASK_RXFIFOHFIE_Msk
11580#define SDMMC_MASK_TXFIFOFIE_Pos (16U)
11581#define SDMMC_MASK_TXFIFOFIE_Msk (0x1UL << SDMMC_MASK_TXFIFOFIE_Pos)
11582#define SDMMC_MASK_TXFIFOFIE SDMMC_MASK_TXFIFOFIE_Msk
11583#define SDMMC_MASK_RXFIFOFIE_Pos (17U)
11584#define SDMMC_MASK_RXFIFOFIE_Msk (0x1UL << SDMMC_MASK_RXFIFOFIE_Pos)
11585#define SDMMC_MASK_RXFIFOFIE SDMMC_MASK_RXFIFOFIE_Msk
11586#define SDMMC_MASK_TXFIFOEIE_Pos (18U)
11587#define SDMMC_MASK_TXFIFOEIE_Msk (0x1UL << SDMMC_MASK_TXFIFOEIE_Pos)
11588#define SDMMC_MASK_TXFIFOEIE SDMMC_MASK_TXFIFOEIE_Msk
11589#define SDMMC_MASK_RXFIFOEIE_Pos (19U)
11590#define SDMMC_MASK_RXFIFOEIE_Msk (0x1UL << SDMMC_MASK_RXFIFOEIE_Pos)
11591#define SDMMC_MASK_RXFIFOEIE SDMMC_MASK_RXFIFOEIE_Msk
11592#define SDMMC_MASK_TXDAVLIE_Pos (20U)
11593#define SDMMC_MASK_TXDAVLIE_Msk (0x1UL << SDMMC_MASK_TXDAVLIE_Pos)
11594#define SDMMC_MASK_TXDAVLIE SDMMC_MASK_TXDAVLIE_Msk
11595#define SDMMC_MASK_RXDAVLIE_Pos (21U)
11596#define SDMMC_MASK_RXDAVLIE_Msk (0x1UL << SDMMC_MASK_RXDAVLIE_Pos)
11597#define SDMMC_MASK_RXDAVLIE SDMMC_MASK_RXDAVLIE_Msk
11598#define SDMMC_MASK_SDIOITIE_Pos (22U)
11599#define SDMMC_MASK_SDIOITIE_Msk (0x1UL << SDMMC_MASK_SDIOITIE_Pos)
11600#define SDMMC_MASK_SDIOITIE SDMMC_MASK_SDIOITIE_Msk
11602/***************** Bit definition for SDMMC_FIFOCNT register *****************/
11603#define SDMMC_FIFOCNT_FIFOCOUNT_Pos (0U)
11604#define SDMMC_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFUL << SDMMC_FIFOCNT_FIFOCOUNT_Pos)
11605#define SDMMC_FIFOCNT_FIFOCOUNT SDMMC_FIFOCNT_FIFOCOUNT_Msk
11607/****************** Bit definition for SDMMC_FIFO register *******************/
11608#define SDMMC_FIFO_FIFODATA_Pos (0U)
11609#define SDMMC_FIFO_FIFODATA_Msk (0xFFFFFFFFUL << SDMMC_FIFO_FIFODATA_Pos)
11610#define SDMMC_FIFO_FIFODATA SDMMC_FIFO_FIFODATA_Msk
11612/******************************************************************************/
11613/* */
11614/* Serial Peripheral Interface (SPI) */
11615/* */
11616/******************************************************************************/
11617/******************* Bit definition for SPI_CR1 register ********************/
11618#define SPI_CR1_CPHA_Pos (0U)
11619#define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos)
11620#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk
11621#define SPI_CR1_CPOL_Pos (1U)
11622#define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos)
11623#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk
11624#define SPI_CR1_MSTR_Pos (2U)
11625#define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos)
11626#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk
11628#define SPI_CR1_BR_Pos (3U)
11629#define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos)
11630#define SPI_CR1_BR SPI_CR1_BR_Msk
11631#define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos)
11632#define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos)
11633#define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos)
11635#define SPI_CR1_SPE_Pos (6U)
11636#define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos)
11637#define SPI_CR1_SPE SPI_CR1_SPE_Msk
11638#define SPI_CR1_LSBFIRST_Pos (7U)
11639#define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos)
11640#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk
11641#define SPI_CR1_SSI_Pos (8U)
11642#define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos)
11643#define SPI_CR1_SSI SPI_CR1_SSI_Msk
11644#define SPI_CR1_SSM_Pos (9U)
11645#define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos)
11646#define SPI_CR1_SSM SPI_CR1_SSM_Msk
11647#define SPI_CR1_RXONLY_Pos (10U)
11648#define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos)
11649#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk
11650#define SPI_CR1_CRCL_Pos (11U)
11651#define SPI_CR1_CRCL_Msk (0x1UL << SPI_CR1_CRCL_Pos)
11652#define SPI_CR1_CRCL SPI_CR1_CRCL_Msk
11653#define SPI_CR1_CRCNEXT_Pos (12U)
11654#define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos)
11655#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk
11656#define SPI_CR1_CRCEN_Pos (13U)
11657#define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos)
11658#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk
11659#define SPI_CR1_BIDIOE_Pos (14U)
11660#define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos)
11661#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk
11662#define SPI_CR1_BIDIMODE_Pos (15U)
11663#define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos)
11664#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk
11666/******************* Bit definition for SPI_CR2 register ********************/
11667#define SPI_CR2_RXDMAEN_Pos (0U)
11668#define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos)
11669#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk
11670#define SPI_CR2_TXDMAEN_Pos (1U)
11671#define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos)
11672#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk
11673#define SPI_CR2_SSOE_Pos (2U)
11674#define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos)
11675#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk
11676#define SPI_CR2_NSSP_Pos (3U)
11677#define SPI_CR2_NSSP_Msk (0x1UL << SPI_CR2_NSSP_Pos)
11678#define SPI_CR2_NSSP SPI_CR2_NSSP_Msk
11679#define SPI_CR2_FRF_Pos (4U)
11680#define SPI_CR2_FRF_Msk (0x1UL << SPI_CR2_FRF_Pos)
11681#define SPI_CR2_FRF SPI_CR2_FRF_Msk
11682#define SPI_CR2_ERRIE_Pos (5U)
11683#define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos)
11684#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk
11685#define SPI_CR2_RXNEIE_Pos (6U)
11686#define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos)
11687#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk
11688#define SPI_CR2_TXEIE_Pos (7U)
11689#define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos)
11690#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk
11691#define SPI_CR2_DS_Pos (8U)
11692#define SPI_CR2_DS_Msk (0xFUL << SPI_CR2_DS_Pos)
11693#define SPI_CR2_DS SPI_CR2_DS_Msk
11694#define SPI_CR2_DS_0 (0x1UL << SPI_CR2_DS_Pos)
11695#define SPI_CR2_DS_1 (0x2UL << SPI_CR2_DS_Pos)
11696#define SPI_CR2_DS_2 (0x4UL << SPI_CR2_DS_Pos)
11697#define SPI_CR2_DS_3 (0x8UL << SPI_CR2_DS_Pos)
11698#define SPI_CR2_FRXTH_Pos (12U)
11699#define SPI_CR2_FRXTH_Msk (0x1UL << SPI_CR2_FRXTH_Pos)
11700#define SPI_CR2_FRXTH SPI_CR2_FRXTH_Msk
11701#define SPI_CR2_LDMARX_Pos (13U)
11702#define SPI_CR2_LDMARX_Msk (0x1UL << SPI_CR2_LDMARX_Pos)
11703#define SPI_CR2_LDMARX SPI_CR2_LDMARX_Msk
11704#define SPI_CR2_LDMATX_Pos (14U)
11705#define SPI_CR2_LDMATX_Msk (0x1UL << SPI_CR2_LDMATX_Pos)
11706#define SPI_CR2_LDMATX SPI_CR2_LDMATX_Msk
11708/******************** Bit definition for SPI_SR register ********************/
11709#define SPI_SR_RXNE_Pos (0U)
11710#define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos)
11711#define SPI_SR_RXNE SPI_SR_RXNE_Msk
11712#define SPI_SR_TXE_Pos (1U)
11713#define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos)
11714#define SPI_SR_TXE SPI_SR_TXE_Msk
11715#define SPI_SR_CHSIDE_Pos (2U)
11716#define SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos)
11717#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk
11718#define SPI_SR_UDR_Pos (3U)
11719#define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos)
11720#define SPI_SR_UDR SPI_SR_UDR_Msk
11721#define SPI_SR_CRCERR_Pos (4U)
11722#define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos)
11723#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk
11724#define SPI_SR_MODF_Pos (5U)
11725#define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos)
11726#define SPI_SR_MODF SPI_SR_MODF_Msk
11727#define SPI_SR_OVR_Pos (6U)
11728#define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos)
11729#define SPI_SR_OVR SPI_SR_OVR_Msk
11730#define SPI_SR_BSY_Pos (7U)
11731#define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos)
11732#define SPI_SR_BSY SPI_SR_BSY_Msk
11733#define SPI_SR_FRE_Pos (8U)
11734#define SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos)
11735#define SPI_SR_FRE SPI_SR_FRE_Msk
11736#define SPI_SR_FRLVL_Pos (9U)
11737#define SPI_SR_FRLVL_Msk (0x3UL << SPI_SR_FRLVL_Pos)
11738#define SPI_SR_FRLVL SPI_SR_FRLVL_Msk
11739#define SPI_SR_FRLVL_0 (0x1UL << SPI_SR_FRLVL_Pos)
11740#define SPI_SR_FRLVL_1 (0x2UL << SPI_SR_FRLVL_Pos)
11741#define SPI_SR_FTLVL_Pos (11U)
11742#define SPI_SR_FTLVL_Msk (0x3UL << SPI_SR_FTLVL_Pos)
11743#define SPI_SR_FTLVL SPI_SR_FTLVL_Msk
11744#define SPI_SR_FTLVL_0 (0x1UL << SPI_SR_FTLVL_Pos)
11745#define SPI_SR_FTLVL_1 (0x2UL << SPI_SR_FTLVL_Pos)
11747/******************** Bit definition for SPI_DR register ********************/
11748#define SPI_DR_DR_Pos (0U)
11749#define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos)
11750#define SPI_DR_DR SPI_DR_DR_Msk
11752/******************* Bit definition for SPI_CRCPR register ******************/
11753#define SPI_CRCPR_CRCPOLY_Pos (0U)
11754#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)
11755#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk
11757/****************** Bit definition for SPI_RXCRCR register ******************/
11758#define SPI_RXCRCR_RXCRC_Pos (0U)
11759#define SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)
11760#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk
11762/****************** Bit definition for SPI_TXCRCR register ******************/
11763#define SPI_TXCRCR_TXCRC_Pos (0U)
11764#define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)
11765#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk
11767/******************************************************************************/
11768/* */
11769/* QUADSPI */
11770/* */
11771/******************************************************************************/
11772/***************** Bit definition for QUADSPI_CR register *******************/
11773#define QUADSPI_CR_EN_Pos (0U)
11774#define QUADSPI_CR_EN_Msk (0x1UL << QUADSPI_CR_EN_Pos)
11775#define QUADSPI_CR_EN QUADSPI_CR_EN_Msk
11776#define QUADSPI_CR_ABORT_Pos (1U)
11777#define QUADSPI_CR_ABORT_Msk (0x1UL << QUADSPI_CR_ABORT_Pos)
11778#define QUADSPI_CR_ABORT QUADSPI_CR_ABORT_Msk
11779#define QUADSPI_CR_DMAEN_Pos (2U)
11780#define QUADSPI_CR_DMAEN_Msk (0x1UL << QUADSPI_CR_DMAEN_Pos)
11781#define QUADSPI_CR_DMAEN QUADSPI_CR_DMAEN_Msk
11782#define QUADSPI_CR_TCEN_Pos (3U)
11783#define QUADSPI_CR_TCEN_Msk (0x1UL << QUADSPI_CR_TCEN_Pos)
11784#define QUADSPI_CR_TCEN QUADSPI_CR_TCEN_Msk
11785#define QUADSPI_CR_SSHIFT_Pos (4U)
11786#define QUADSPI_CR_SSHIFT_Msk (0x1UL << QUADSPI_CR_SSHIFT_Pos)
11787#define QUADSPI_CR_SSHIFT QUADSPI_CR_SSHIFT_Msk
11788#define QUADSPI_CR_DFM_Pos (6U)
11789#define QUADSPI_CR_DFM_Msk (0x1UL << QUADSPI_CR_DFM_Pos)
11790#define QUADSPI_CR_DFM QUADSPI_CR_DFM_Msk
11791#define QUADSPI_CR_FSEL_Pos (7U)
11792#define QUADSPI_CR_FSEL_Msk (0x1UL << QUADSPI_CR_FSEL_Pos)
11793#define QUADSPI_CR_FSEL QUADSPI_CR_FSEL_Msk
11794#define QUADSPI_CR_FTHRES_Pos (8U)
11795#define QUADSPI_CR_FTHRES_Msk (0xFUL << QUADSPI_CR_FTHRES_Pos)
11796#define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk
11797#define QUADSPI_CR_TEIE_Pos (16U)
11798#define QUADSPI_CR_TEIE_Msk (0x1UL << QUADSPI_CR_TEIE_Pos)
11799#define QUADSPI_CR_TEIE QUADSPI_CR_TEIE_Msk
11800#define QUADSPI_CR_TCIE_Pos (17U)
11801#define QUADSPI_CR_TCIE_Msk (0x1UL << QUADSPI_CR_TCIE_Pos)
11802#define QUADSPI_CR_TCIE QUADSPI_CR_TCIE_Msk
11803#define QUADSPI_CR_FTIE_Pos (18U)
11804#define QUADSPI_CR_FTIE_Msk (0x1UL << QUADSPI_CR_FTIE_Pos)
11805#define QUADSPI_CR_FTIE QUADSPI_CR_FTIE_Msk
11806#define QUADSPI_CR_SMIE_Pos (19U)
11807#define QUADSPI_CR_SMIE_Msk (0x1UL << QUADSPI_CR_SMIE_Pos)
11808#define QUADSPI_CR_SMIE QUADSPI_CR_SMIE_Msk
11809#define QUADSPI_CR_TOIE_Pos (20U)
11810#define QUADSPI_CR_TOIE_Msk (0x1UL << QUADSPI_CR_TOIE_Pos)
11811#define QUADSPI_CR_TOIE QUADSPI_CR_TOIE_Msk
11812#define QUADSPI_CR_APMS_Pos (22U)
11813#define QUADSPI_CR_APMS_Msk (0x1UL << QUADSPI_CR_APMS_Pos)
11814#define QUADSPI_CR_APMS QUADSPI_CR_APMS_Msk
11815#define QUADSPI_CR_PMM_Pos (23U)
11816#define QUADSPI_CR_PMM_Msk (0x1UL << QUADSPI_CR_PMM_Pos)
11817#define QUADSPI_CR_PMM QUADSPI_CR_PMM_Msk
11818#define QUADSPI_CR_PRESCALER_Pos (24U)
11819#define QUADSPI_CR_PRESCALER_Msk (0xFFUL << QUADSPI_CR_PRESCALER_Pos)
11820#define QUADSPI_CR_PRESCALER QUADSPI_CR_PRESCALER_Msk
11822/***************** Bit definition for QUADSPI_DCR register ******************/
11823#define QUADSPI_DCR_CKMODE_Pos (0U)
11824#define QUADSPI_DCR_CKMODE_Msk (0x1UL << QUADSPI_DCR_CKMODE_Pos)
11825#define QUADSPI_DCR_CKMODE QUADSPI_DCR_CKMODE_Msk
11826#define QUADSPI_DCR_CSHT_Pos (8U)
11827#define QUADSPI_DCR_CSHT_Msk (0x7UL << QUADSPI_DCR_CSHT_Pos)
11828#define QUADSPI_DCR_CSHT QUADSPI_DCR_CSHT_Msk
11829#define QUADSPI_DCR_CSHT_0 (0x1UL << QUADSPI_DCR_CSHT_Pos)
11830#define QUADSPI_DCR_CSHT_1 (0x2UL << QUADSPI_DCR_CSHT_Pos)
11831#define QUADSPI_DCR_CSHT_2 (0x4UL << QUADSPI_DCR_CSHT_Pos)
11832#define QUADSPI_DCR_FSIZE_Pos (16U)
11833#define QUADSPI_DCR_FSIZE_Msk (0x1FUL << QUADSPI_DCR_FSIZE_Pos)
11834#define QUADSPI_DCR_FSIZE QUADSPI_DCR_FSIZE_Msk
11836/****************** Bit definition for QUADSPI_SR register *******************/
11837#define QUADSPI_SR_TEF_Pos (0U)
11838#define QUADSPI_SR_TEF_Msk (0x1UL << QUADSPI_SR_TEF_Pos)
11839#define QUADSPI_SR_TEF QUADSPI_SR_TEF_Msk
11840#define QUADSPI_SR_TCF_Pos (1U)
11841#define QUADSPI_SR_TCF_Msk (0x1UL << QUADSPI_SR_TCF_Pos)
11842#define QUADSPI_SR_TCF QUADSPI_SR_TCF_Msk
11843#define QUADSPI_SR_FTF_Pos (2U)
11844#define QUADSPI_SR_FTF_Msk (0x1UL << QUADSPI_SR_FTF_Pos)
11845#define QUADSPI_SR_FTF QUADSPI_SR_FTF_Msk
11846#define QUADSPI_SR_SMF_Pos (3U)
11847#define QUADSPI_SR_SMF_Msk (0x1UL << QUADSPI_SR_SMF_Pos)
11848#define QUADSPI_SR_SMF QUADSPI_SR_SMF_Msk
11849#define QUADSPI_SR_TOF_Pos (4U)
11850#define QUADSPI_SR_TOF_Msk (0x1UL << QUADSPI_SR_TOF_Pos)
11851#define QUADSPI_SR_TOF QUADSPI_SR_TOF_Msk
11852#define QUADSPI_SR_BUSY_Pos (5U)
11853#define QUADSPI_SR_BUSY_Msk (0x1UL << QUADSPI_SR_BUSY_Pos)
11854#define QUADSPI_SR_BUSY QUADSPI_SR_BUSY_Msk
11855#define QUADSPI_SR_FLEVEL_Pos (8U)
11856#define QUADSPI_SR_FLEVEL_Msk (0x1FUL << QUADSPI_SR_FLEVEL_Pos)
11857#define QUADSPI_SR_FLEVEL QUADSPI_SR_FLEVEL_Msk
11859/****************** Bit definition for QUADSPI_FCR register ******************/
11860#define QUADSPI_FCR_CTEF_Pos (0U)
11861#define QUADSPI_FCR_CTEF_Msk (0x1UL << QUADSPI_FCR_CTEF_Pos)
11862#define QUADSPI_FCR_CTEF QUADSPI_FCR_CTEF_Msk
11863#define QUADSPI_FCR_CTCF_Pos (1U)
11864#define QUADSPI_FCR_CTCF_Msk (0x1UL << QUADSPI_FCR_CTCF_Pos)
11865#define QUADSPI_FCR_CTCF QUADSPI_FCR_CTCF_Msk
11866#define QUADSPI_FCR_CSMF_Pos (3U)
11867#define QUADSPI_FCR_CSMF_Msk (0x1UL << QUADSPI_FCR_CSMF_Pos)
11868#define QUADSPI_FCR_CSMF QUADSPI_FCR_CSMF_Msk
11869#define QUADSPI_FCR_CTOF_Pos (4U)
11870#define QUADSPI_FCR_CTOF_Msk (0x1UL << QUADSPI_FCR_CTOF_Pos)
11871#define QUADSPI_FCR_CTOF QUADSPI_FCR_CTOF_Msk
11873/****************** Bit definition for QUADSPI_DLR register ******************/
11874#define QUADSPI_DLR_DL_Pos (0U)
11875#define QUADSPI_DLR_DL_Msk (0xFFFFFFFFUL << QUADSPI_DLR_DL_Pos)
11876#define QUADSPI_DLR_DL QUADSPI_DLR_DL_Msk
11878/****************** Bit definition for QUADSPI_CCR register ******************/
11879#define QUADSPI_CCR_INSTRUCTION_Pos (0U)
11880#define QUADSPI_CCR_INSTRUCTION_Msk (0xFFUL << QUADSPI_CCR_INSTRUCTION_Pos)
11881#define QUADSPI_CCR_INSTRUCTION QUADSPI_CCR_INSTRUCTION_Msk
11882#define QUADSPI_CCR_IMODE_Pos (8U)
11883#define QUADSPI_CCR_IMODE_Msk (0x3UL << QUADSPI_CCR_IMODE_Pos)
11884#define QUADSPI_CCR_IMODE QUADSPI_CCR_IMODE_Msk
11885#define QUADSPI_CCR_IMODE_0 (0x1UL << QUADSPI_CCR_IMODE_Pos)
11886#define QUADSPI_CCR_IMODE_1 (0x2UL << QUADSPI_CCR_IMODE_Pos)
11887#define QUADSPI_CCR_ADMODE_Pos (10U)
11888#define QUADSPI_CCR_ADMODE_Msk (0x3UL << QUADSPI_CCR_ADMODE_Pos)
11889#define QUADSPI_CCR_ADMODE QUADSPI_CCR_ADMODE_Msk
11890#define QUADSPI_CCR_ADMODE_0 (0x1UL << QUADSPI_CCR_ADMODE_Pos)
11891#define QUADSPI_CCR_ADMODE_1 (0x2UL << QUADSPI_CCR_ADMODE_Pos)
11892#define QUADSPI_CCR_ADSIZE_Pos (12U)
11893#define QUADSPI_CCR_ADSIZE_Msk (0x3UL << QUADSPI_CCR_ADSIZE_Pos)
11894#define QUADSPI_CCR_ADSIZE QUADSPI_CCR_ADSIZE_Msk
11895#define QUADSPI_CCR_ADSIZE_0 (0x1UL << QUADSPI_CCR_ADSIZE_Pos)
11896#define QUADSPI_CCR_ADSIZE_1 (0x2UL << QUADSPI_CCR_ADSIZE_Pos)
11897#define QUADSPI_CCR_ABMODE_Pos (14U)
11898#define QUADSPI_CCR_ABMODE_Msk (0x3UL << QUADSPI_CCR_ABMODE_Pos)
11899#define QUADSPI_CCR_ABMODE QUADSPI_CCR_ABMODE_Msk
11900#define QUADSPI_CCR_ABMODE_0 (0x1UL << QUADSPI_CCR_ABMODE_Pos)
11901#define QUADSPI_CCR_ABMODE_1 (0x2UL << QUADSPI_CCR_ABMODE_Pos)
11902#define QUADSPI_CCR_ABSIZE_Pos (16U)
11903#define QUADSPI_CCR_ABSIZE_Msk (0x3UL << QUADSPI_CCR_ABSIZE_Pos)
11904#define QUADSPI_CCR_ABSIZE QUADSPI_CCR_ABSIZE_Msk
11905#define QUADSPI_CCR_ABSIZE_0 (0x1UL << QUADSPI_CCR_ABSIZE_Pos)
11906#define QUADSPI_CCR_ABSIZE_1 (0x2UL << QUADSPI_CCR_ABSIZE_Pos)
11907#define QUADSPI_CCR_DCYC_Pos (18U)
11908#define QUADSPI_CCR_DCYC_Msk (0x1FUL << QUADSPI_CCR_DCYC_Pos)
11909#define QUADSPI_CCR_DCYC QUADSPI_CCR_DCYC_Msk
11910#define QUADSPI_CCR_DMODE_Pos (24U)
11911#define QUADSPI_CCR_DMODE_Msk (0x3UL << QUADSPI_CCR_DMODE_Pos)
11912#define QUADSPI_CCR_DMODE QUADSPI_CCR_DMODE_Msk
11913#define QUADSPI_CCR_DMODE_0 (0x1UL << QUADSPI_CCR_DMODE_Pos)
11914#define QUADSPI_CCR_DMODE_1 (0x2UL << QUADSPI_CCR_DMODE_Pos)
11915#define QUADSPI_CCR_FMODE_Pos (26U)
11916#define QUADSPI_CCR_FMODE_Msk (0x3UL << QUADSPI_CCR_FMODE_Pos)
11917#define QUADSPI_CCR_FMODE QUADSPI_CCR_FMODE_Msk
11918#define QUADSPI_CCR_FMODE_0 (0x1UL << QUADSPI_CCR_FMODE_Pos)
11919#define QUADSPI_CCR_FMODE_1 (0x2UL << QUADSPI_CCR_FMODE_Pos)
11920#define QUADSPI_CCR_SIOO_Pos (28U)
11921#define QUADSPI_CCR_SIOO_Msk (0x1UL << QUADSPI_CCR_SIOO_Pos)
11922#define QUADSPI_CCR_SIOO QUADSPI_CCR_SIOO_Msk
11923#define QUADSPI_CCR_DHHC_Pos (30U)
11924#define QUADSPI_CCR_DHHC_Msk (0x1UL << QUADSPI_CCR_DHHC_Pos)
11925#define QUADSPI_CCR_DHHC QUADSPI_CCR_DHHC_Msk
11926#define QUADSPI_CCR_DDRM_Pos (31U)
11927#define QUADSPI_CCR_DDRM_Msk (0x1UL << QUADSPI_CCR_DDRM_Pos)
11928#define QUADSPI_CCR_DDRM QUADSPI_CCR_DDRM_Msk
11930/****************** Bit definition for QUADSPI_AR register *******************/
11931#define QUADSPI_AR_ADDRESS_Pos (0U)
11932#define QUADSPI_AR_ADDRESS_Msk (0xFFFFFFFFUL << QUADSPI_AR_ADDRESS_Pos)
11933#define QUADSPI_AR_ADDRESS QUADSPI_AR_ADDRESS_Msk
11935/****************** Bit definition for QUADSPI_ABR register ******************/
11936#define QUADSPI_ABR_ALTERNATE_Pos (0U)
11937#define QUADSPI_ABR_ALTERNATE_Msk (0xFFFFFFFFUL << QUADSPI_ABR_ALTERNATE_Pos)
11938#define QUADSPI_ABR_ALTERNATE QUADSPI_ABR_ALTERNATE_Msk
11940/****************** Bit definition for QUADSPI_DR register *******************/
11941#define QUADSPI_DR_DATA_Pos (0U)
11942#define QUADSPI_DR_DATA_Msk (0xFFFFFFFFUL << QUADSPI_DR_DATA_Pos)
11943#define QUADSPI_DR_DATA QUADSPI_DR_DATA_Msk
11945/****************** Bit definition for QUADSPI_PSMKR register ****************/
11946#define QUADSPI_PSMKR_MASK_Pos (0U)
11947#define QUADSPI_PSMKR_MASK_Msk (0xFFFFFFFFUL << QUADSPI_PSMKR_MASK_Pos)
11948#define QUADSPI_PSMKR_MASK QUADSPI_PSMKR_MASK_Msk
11950/****************** Bit definition for QUADSPI_PSMAR register ****************/
11951#define QUADSPI_PSMAR_MATCH_Pos (0U)
11952#define QUADSPI_PSMAR_MATCH_Msk (0xFFFFFFFFUL << QUADSPI_PSMAR_MATCH_Pos)
11953#define QUADSPI_PSMAR_MATCH QUADSPI_PSMAR_MATCH_Msk
11955/****************** Bit definition for QUADSPI_PIR register *****************/
11956#define QUADSPI_PIR_INTERVAL_Pos (0U)
11957#define QUADSPI_PIR_INTERVAL_Msk (0xFFFFUL << QUADSPI_PIR_INTERVAL_Pos)
11958#define QUADSPI_PIR_INTERVAL QUADSPI_PIR_INTERVAL_Msk
11960/****************** Bit definition for QUADSPI_LPTR register *****************/
11961#define QUADSPI_LPTR_TIMEOUT_Pos (0U)
11962#define QUADSPI_LPTR_TIMEOUT_Msk (0xFFFFUL << QUADSPI_LPTR_TIMEOUT_Pos)
11963#define QUADSPI_LPTR_TIMEOUT QUADSPI_LPTR_TIMEOUT_Msk
11965/******************************************************************************/
11966/* */
11967/* SYSCFG */
11968/* */
11969/******************************************************************************/
11970/****************** Bit definition for SYSCFG_MEMRMP register ***************/
11971#define SYSCFG_MEMRMP_MEM_MODE_Pos (0U)
11972#define SYSCFG_MEMRMP_MEM_MODE_Msk (0x7UL << SYSCFG_MEMRMP_MEM_MODE_Pos)
11973#define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk
11974#define SYSCFG_MEMRMP_MEM_MODE_0 (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos)
11975#define SYSCFG_MEMRMP_MEM_MODE_1 (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos)
11976#define SYSCFG_MEMRMP_MEM_MODE_2 (0x4UL << SYSCFG_MEMRMP_MEM_MODE_Pos)
11978/****************** Bit definition for SYSCFG_CFGR1 register ******************/
11979#define SYSCFG_CFGR1_FWDIS_Pos (0U)
11980#define SYSCFG_CFGR1_FWDIS_Msk (0x1UL << SYSCFG_CFGR1_FWDIS_Pos)
11981#define SYSCFG_CFGR1_FWDIS SYSCFG_CFGR1_FWDIS_Msk
11982#define SYSCFG_CFGR1_BOOSTEN_Pos (8U)
11983#define SYSCFG_CFGR1_BOOSTEN_Msk (0x1UL << SYSCFG_CFGR1_BOOSTEN_Pos)
11984#define SYSCFG_CFGR1_BOOSTEN SYSCFG_CFGR1_BOOSTEN_Msk
11985#define SYSCFG_CFGR1_I2C_PB6_FMP_Pos (16U)
11986#define SYSCFG_CFGR1_I2C_PB6_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB6_FMP_Pos)
11987#define SYSCFG_CFGR1_I2C_PB6_FMP SYSCFG_CFGR1_I2C_PB6_FMP_Msk
11988#define SYSCFG_CFGR1_I2C_PB7_FMP_Pos (17U)
11989#define SYSCFG_CFGR1_I2C_PB7_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB7_FMP_Pos)
11990#define SYSCFG_CFGR1_I2C_PB7_FMP SYSCFG_CFGR1_I2C_PB7_FMP_Msk
11991#define SYSCFG_CFGR1_I2C_PB8_FMP_Pos (18U)
11992#define SYSCFG_CFGR1_I2C_PB8_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB8_FMP_Pos)
11993#define SYSCFG_CFGR1_I2C_PB8_FMP SYSCFG_CFGR1_I2C_PB8_FMP_Msk
11994#define SYSCFG_CFGR1_I2C_PB9_FMP_Pos (19U)
11995#define SYSCFG_CFGR1_I2C_PB9_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB9_FMP_Pos)
11996#define SYSCFG_CFGR1_I2C_PB9_FMP SYSCFG_CFGR1_I2C_PB9_FMP_Msk
11997#define SYSCFG_CFGR1_I2C1_FMP_Pos (20U)
11998#define SYSCFG_CFGR1_I2C1_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C1_FMP_Pos)
11999#define SYSCFG_CFGR1_I2C1_FMP SYSCFG_CFGR1_I2C1_FMP_Msk
12000#define SYSCFG_CFGR1_I2C2_FMP_Pos (21U)
12001#define SYSCFG_CFGR1_I2C2_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C2_FMP_Pos)
12002#define SYSCFG_CFGR1_I2C2_FMP SYSCFG_CFGR1_I2C2_FMP_Msk
12003#define SYSCFG_CFGR1_I2C3_FMP_Pos (22U)
12004#define SYSCFG_CFGR1_I2C3_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C3_FMP_Pos)
12005#define SYSCFG_CFGR1_I2C3_FMP SYSCFG_CFGR1_I2C3_FMP_Msk
12006#define SYSCFG_CFGR1_FPU_IE_0 (0x04000000UL)
12007#define SYSCFG_CFGR1_FPU_IE_1 (0x08000000UL)
12008#define SYSCFG_CFGR1_FPU_IE_2 (0x10000000UL)
12009#define SYSCFG_CFGR1_FPU_IE_3 (0x20000000UL)
12010#define SYSCFG_CFGR1_FPU_IE_4 (0x40000000UL)
12011#define SYSCFG_CFGR1_FPU_IE_5 (0x80000000UL)
12013/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
12014#define SYSCFG_EXTICR1_EXTI0_Pos (0U)
12015#define SYSCFG_EXTICR1_EXTI0_Msk (0x7UL << SYSCFG_EXTICR1_EXTI0_Pos)
12016#define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk
12017#define SYSCFG_EXTICR1_EXTI1_Pos (4U)
12018#define SYSCFG_EXTICR1_EXTI1_Msk (0x7UL << SYSCFG_EXTICR1_EXTI1_Pos)
12019#define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk
12020#define SYSCFG_EXTICR1_EXTI2_Pos (8U)
12021#define SYSCFG_EXTICR1_EXTI2_Msk (0x7UL << SYSCFG_EXTICR1_EXTI2_Pos)
12022#define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk
12023#define SYSCFG_EXTICR1_EXTI3_Pos (12U)
12024#define SYSCFG_EXTICR1_EXTI3_Msk (0x7UL << SYSCFG_EXTICR1_EXTI3_Pos)
12025#define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk
12030#define SYSCFG_EXTICR1_EXTI0_PA (0x00000000UL)
12031#define SYSCFG_EXTICR1_EXTI0_PB (0x00000001UL)
12032#define SYSCFG_EXTICR1_EXTI0_PC (0x00000002UL)
12033#define SYSCFG_EXTICR1_EXTI0_PD (0x00000003UL)
12034#define SYSCFG_EXTICR1_EXTI0_PE (0x00000004UL)
12035#define SYSCFG_EXTICR1_EXTI0_PH (0x00000007UL)
12040#define SYSCFG_EXTICR1_EXTI1_PA (0x00000000UL)
12041#define SYSCFG_EXTICR1_EXTI1_PB (0x00000010UL)
12042#define SYSCFG_EXTICR1_EXTI1_PC (0x00000020UL)
12043#define SYSCFG_EXTICR1_EXTI1_PD (0x00000030UL)
12044#define SYSCFG_EXTICR1_EXTI1_PE (0x00000040UL)
12045#define SYSCFG_EXTICR1_EXTI1_PH (0x00000070UL)
12050#define SYSCFG_EXTICR1_EXTI2_PA (0x00000000UL)
12051#define SYSCFG_EXTICR1_EXTI2_PB (0x00000100UL)
12052#define SYSCFG_EXTICR1_EXTI2_PC (0x00000200UL)
12053#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300UL)
12054#define SYSCFG_EXTICR1_EXTI2_PE (0x00000400UL)
12059#define SYSCFG_EXTICR1_EXTI3_PA (0x00000000UL)
12060#define SYSCFG_EXTICR1_EXTI3_PB (0x00001000UL)
12061#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000UL)
12062#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000UL)
12063#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000UL)
12064#define SYSCFG_EXTICR1_EXTI3_PG (0x00006000UL)
12066/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
12067#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
12068#define SYSCFG_EXTICR2_EXTI4_Msk (0x7UL << SYSCFG_EXTICR2_EXTI4_Pos)
12069#define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk
12070#define SYSCFG_EXTICR2_EXTI5_Pos (4U)
12071#define SYSCFG_EXTICR2_EXTI5_Msk (0x7UL << SYSCFG_EXTICR2_EXTI5_Pos)
12072#define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk
12073#define SYSCFG_EXTICR2_EXTI6_Pos (8U)
12074#define SYSCFG_EXTICR2_EXTI6_Msk (0x7UL << SYSCFG_EXTICR2_EXTI6_Pos)
12075#define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk
12076#define SYSCFG_EXTICR2_EXTI7_Pos (12U)
12077#define SYSCFG_EXTICR2_EXTI7_Msk (0x7UL << SYSCFG_EXTICR2_EXTI7_Pos)
12078#define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk
12082#define SYSCFG_EXTICR2_EXTI4_PA (0x00000000UL)
12083#define SYSCFG_EXTICR2_EXTI4_PB (0x00000001UL)
12084#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002UL)
12085#define SYSCFG_EXTICR2_EXTI4_PD (0x00000003UL)
12086#define SYSCFG_EXTICR2_EXTI4_PE (0x00000004UL)
12091#define SYSCFG_EXTICR2_EXTI5_PA (0x00000000UL)
12092#define SYSCFG_EXTICR2_EXTI5_PB (0x00000010UL)
12093#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020UL)
12094#define SYSCFG_EXTICR2_EXTI5_PD (0x00000030UL)
12095#define SYSCFG_EXTICR2_EXTI5_PE (0x00000040UL)
12100#define SYSCFG_EXTICR2_EXTI6_PA (0x00000000UL)
12101#define SYSCFG_EXTICR2_EXTI6_PB (0x00000100UL)
12102#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200UL)
12103#define SYSCFG_EXTICR2_EXTI6_PD (0x00000300UL)
12104#define SYSCFG_EXTICR2_EXTI6_PE (0x00000400UL)
12109#define SYSCFG_EXTICR2_EXTI7_PA (0x00000000UL)
12110#define SYSCFG_EXTICR2_EXTI7_PB (0x00001000UL)
12111#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000UL)
12112#define SYSCFG_EXTICR2_EXTI7_PD (0x00003000UL)
12113#define SYSCFG_EXTICR2_EXTI7_PE (0x00004000UL)
12115/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
12116#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
12117#define SYSCFG_EXTICR3_EXTI8_Msk (0x7UL << SYSCFG_EXTICR3_EXTI8_Pos)
12118#define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk
12119#define SYSCFG_EXTICR3_EXTI9_Pos (4U)
12120#define SYSCFG_EXTICR3_EXTI9_Msk (0x7UL << SYSCFG_EXTICR3_EXTI9_Pos)
12121#define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk
12122#define SYSCFG_EXTICR3_EXTI10_Pos (8U)
12123#define SYSCFG_EXTICR3_EXTI10_Msk (0x7UL << SYSCFG_EXTICR3_EXTI10_Pos)
12124#define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk
12125#define SYSCFG_EXTICR3_EXTI11_Pos (12U)
12126#define SYSCFG_EXTICR3_EXTI11_Msk (0x7UL << SYSCFG_EXTICR3_EXTI11_Pos)
12127#define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk
12132#define SYSCFG_EXTICR3_EXTI8_PA (0x00000000UL)
12133#define SYSCFG_EXTICR3_EXTI8_PB (0x00000001UL)
12134#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002UL)
12135#define SYSCFG_EXTICR3_EXTI8_PD (0x00000003UL)
12136#define SYSCFG_EXTICR3_EXTI8_PE (0x00000004UL)
12141#define SYSCFG_EXTICR3_EXTI9_PA (0x00000000UL)
12142#define SYSCFG_EXTICR3_EXTI9_PB (0x00000010UL)
12143#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020UL)
12144#define SYSCFG_EXTICR3_EXTI9_PD (0x00000030UL)
12145#define SYSCFG_EXTICR3_EXTI9_PE (0x00000040UL)
12150#define SYSCFG_EXTICR3_EXTI10_PA (0x00000000UL)
12151#define SYSCFG_EXTICR3_EXTI10_PB (0x00000100UL)
12152#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200UL)
12153#define SYSCFG_EXTICR3_EXTI10_PD (0x00000300UL)
12154#define SYSCFG_EXTICR3_EXTI10_PE (0x00000400UL)
12159#define SYSCFG_EXTICR3_EXTI11_PA (0x00000000UL)
12160#define SYSCFG_EXTICR3_EXTI11_PB (0x00001000UL)
12161#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000UL)
12162#define SYSCFG_EXTICR3_EXTI11_PD (0x00003000UL)
12163#define SYSCFG_EXTICR3_EXTI11_PE (0x00004000UL)
12165/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
12166#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
12167#define SYSCFG_EXTICR4_EXTI12_Msk (0x7UL << SYSCFG_EXTICR4_EXTI12_Pos)
12168#define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk
12169#define SYSCFG_EXTICR4_EXTI13_Pos (4U)
12170#define SYSCFG_EXTICR4_EXTI13_Msk (0x7UL << SYSCFG_EXTICR4_EXTI13_Pos)
12171#define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk
12172#define SYSCFG_EXTICR4_EXTI14_Pos (8U)
12173#define SYSCFG_EXTICR4_EXTI14_Msk (0x7UL << SYSCFG_EXTICR4_EXTI14_Pos)
12174#define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk
12175#define SYSCFG_EXTICR4_EXTI15_Pos (12U)
12176#define SYSCFG_EXTICR4_EXTI15_Msk (0x7UL << SYSCFG_EXTICR4_EXTI15_Pos)
12177#define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk
12182#define SYSCFG_EXTICR4_EXTI12_PA (0x00000000UL)
12183#define SYSCFG_EXTICR4_EXTI12_PB (0x00000001UL)
12184#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002UL)
12185#define SYSCFG_EXTICR4_EXTI12_PD (0x00000003UL)
12186#define SYSCFG_EXTICR4_EXTI12_PE (0x00000004UL)
12191#define SYSCFG_EXTICR4_EXTI13_PA (0x00000000UL)
12192#define SYSCFG_EXTICR4_EXTI13_PB (0x00000010UL)
12193#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020UL)
12194#define SYSCFG_EXTICR4_EXTI13_PD (0x00000030UL)
12195#define SYSCFG_EXTICR4_EXTI13_PE (0x00000040UL)
12200#define SYSCFG_EXTICR4_EXTI14_PA (0x00000000UL)
12201#define SYSCFG_EXTICR4_EXTI14_PB (0x00000100UL)
12202#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200UL)
12203#define SYSCFG_EXTICR4_EXTI14_PD (0x00000300UL)
12204#define SYSCFG_EXTICR4_EXTI14_PE (0x00000400UL)
12209#define SYSCFG_EXTICR4_EXTI15_PA (0x00000000UL)
12210#define SYSCFG_EXTICR4_EXTI15_PB (0x00001000UL)
12211#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000UL)
12212#define SYSCFG_EXTICR4_EXTI15_PD (0x00003000UL)
12213#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000UL)
12215/****************** Bit definition for SYSCFG_SCSR register ****************/
12216#define SYSCFG_SCSR_SRAM2ER_Pos (0U)
12217#define SYSCFG_SCSR_SRAM2ER_Msk (0x1UL << SYSCFG_SCSR_SRAM2ER_Pos)
12218#define SYSCFG_SCSR_SRAM2ER SYSCFG_SCSR_SRAM2ER_Msk
12219#define SYSCFG_SCSR_SRAM2BSY_Pos (1U)
12220#define SYSCFG_SCSR_SRAM2BSY_Msk (0x1UL << SYSCFG_SCSR_SRAM2BSY_Pos)
12221#define SYSCFG_SCSR_SRAM2BSY SYSCFG_SCSR_SRAM2BSY_Msk
12223/****************** Bit definition for SYSCFG_CFGR2 register ****************/
12224#define SYSCFG_CFGR2_CLL_Pos (0U)
12225#define SYSCFG_CFGR2_CLL_Msk (0x1UL << SYSCFG_CFGR2_CLL_Pos)
12226#define SYSCFG_CFGR2_CLL SYSCFG_CFGR2_CLL_Msk
12227#define SYSCFG_CFGR2_SPL_Pos (1U)
12228#define SYSCFG_CFGR2_SPL_Msk (0x1UL << SYSCFG_CFGR2_SPL_Pos)
12229#define SYSCFG_CFGR2_SPL SYSCFG_CFGR2_SPL_Msk
12230#define SYSCFG_CFGR2_PVDL_Pos (2U)
12231#define SYSCFG_CFGR2_PVDL_Msk (0x1UL << SYSCFG_CFGR2_PVDL_Pos)
12232#define SYSCFG_CFGR2_PVDL SYSCFG_CFGR2_PVDL_Msk
12233#define SYSCFG_CFGR2_ECCL_Pos (3U)
12234#define SYSCFG_CFGR2_ECCL_Msk (0x1UL << SYSCFG_CFGR2_ECCL_Pos)
12235#define SYSCFG_CFGR2_ECCL SYSCFG_CFGR2_ECCL_Msk
12236#define SYSCFG_CFGR2_SPF_Pos (8U)
12237#define SYSCFG_CFGR2_SPF_Msk (0x1UL << SYSCFG_CFGR2_SPF_Pos)
12238#define SYSCFG_CFGR2_SPF SYSCFG_CFGR2_SPF_Msk
12240/****************** Bit definition for SYSCFG_SWPR register ****************/
12241#define SYSCFG_SWPR_PAGE0_Pos (0U)
12242#define SYSCFG_SWPR_PAGE0_Msk (0x1UL << SYSCFG_SWPR_PAGE0_Pos)
12243#define SYSCFG_SWPR_PAGE0 SYSCFG_SWPR_PAGE0_Msk
12244#define SYSCFG_SWPR_PAGE1_Pos (1U)
12245#define SYSCFG_SWPR_PAGE1_Msk (0x1UL << SYSCFG_SWPR_PAGE1_Pos)
12246#define SYSCFG_SWPR_PAGE1 SYSCFG_SWPR_PAGE1_Msk
12247#define SYSCFG_SWPR_PAGE2_Pos (2U)
12248#define SYSCFG_SWPR_PAGE2_Msk (0x1UL << SYSCFG_SWPR_PAGE2_Pos)
12249#define SYSCFG_SWPR_PAGE2 SYSCFG_SWPR_PAGE2_Msk
12250#define SYSCFG_SWPR_PAGE3_Pos (3U)
12251#define SYSCFG_SWPR_PAGE3_Msk (0x1UL << SYSCFG_SWPR_PAGE3_Pos)
12252#define SYSCFG_SWPR_PAGE3 SYSCFG_SWPR_PAGE3_Msk
12253#define SYSCFG_SWPR_PAGE4_Pos (4U)
12254#define SYSCFG_SWPR_PAGE4_Msk (0x1UL << SYSCFG_SWPR_PAGE4_Pos)
12255#define SYSCFG_SWPR_PAGE4 SYSCFG_SWPR_PAGE4_Msk
12256#define SYSCFG_SWPR_PAGE5_Pos (5U)
12257#define SYSCFG_SWPR_PAGE5_Msk (0x1UL << SYSCFG_SWPR_PAGE5_Pos)
12258#define SYSCFG_SWPR_PAGE5 SYSCFG_SWPR_PAGE5_Msk
12259#define SYSCFG_SWPR_PAGE6_Pos (6U)
12260#define SYSCFG_SWPR_PAGE6_Msk (0x1UL << SYSCFG_SWPR_PAGE6_Pos)
12261#define SYSCFG_SWPR_PAGE6 SYSCFG_SWPR_PAGE6_Msk
12262#define SYSCFG_SWPR_PAGE7_Pos (7U)
12263#define SYSCFG_SWPR_PAGE7_Msk (0x1UL << SYSCFG_SWPR_PAGE7_Pos)
12264#define SYSCFG_SWPR_PAGE7 SYSCFG_SWPR_PAGE7_Msk
12265#define SYSCFG_SWPR_PAGE8_Pos (8U)
12266#define SYSCFG_SWPR_PAGE8_Msk (0x1UL << SYSCFG_SWPR_PAGE8_Pos)
12267#define SYSCFG_SWPR_PAGE8 SYSCFG_SWPR_PAGE8_Msk
12268#define SYSCFG_SWPR_PAGE9_Pos (9U)
12269#define SYSCFG_SWPR_PAGE9_Msk (0x1UL << SYSCFG_SWPR_PAGE9_Pos)
12270#define SYSCFG_SWPR_PAGE9 SYSCFG_SWPR_PAGE9_Msk
12271#define SYSCFG_SWPR_PAGE10_Pos (10U)
12272#define SYSCFG_SWPR_PAGE10_Msk (0x1UL << SYSCFG_SWPR_PAGE10_Pos)
12273#define SYSCFG_SWPR_PAGE10 SYSCFG_SWPR_PAGE10_Msk
12274#define SYSCFG_SWPR_PAGE11_Pos (11U)
12275#define SYSCFG_SWPR_PAGE11_Msk (0x1UL << SYSCFG_SWPR_PAGE11_Pos)
12276#define SYSCFG_SWPR_PAGE11 SYSCFG_SWPR_PAGE11_Msk
12277#define SYSCFG_SWPR_PAGE12_Pos (12U)
12278#define SYSCFG_SWPR_PAGE12_Msk (0x1UL << SYSCFG_SWPR_PAGE12_Pos)
12279#define SYSCFG_SWPR_PAGE12 SYSCFG_SWPR_PAGE12_Msk
12280#define SYSCFG_SWPR_PAGE13_Pos (13U)
12281#define SYSCFG_SWPR_PAGE13_Msk (0x1UL << SYSCFG_SWPR_PAGE13_Pos)
12282#define SYSCFG_SWPR_PAGE13 SYSCFG_SWPR_PAGE13_Msk
12283#define SYSCFG_SWPR_PAGE14_Pos (14U)
12284#define SYSCFG_SWPR_PAGE14_Msk (0x1UL << SYSCFG_SWPR_PAGE14_Pos)
12285#define SYSCFG_SWPR_PAGE14 SYSCFG_SWPR_PAGE14_Msk
12286#define SYSCFG_SWPR_PAGE15_Pos (15U)
12287#define SYSCFG_SWPR_PAGE15_Msk (0x1UL << SYSCFG_SWPR_PAGE15_Pos)
12288#define SYSCFG_SWPR_PAGE15 SYSCFG_SWPR_PAGE15_Msk
12290/****************** Bit definition for SYSCFG_SKR register ****************/
12291#define SYSCFG_SKR_KEY_Pos (0U)
12292#define SYSCFG_SKR_KEY_Msk (0xFFUL << SYSCFG_SKR_KEY_Pos)
12293#define SYSCFG_SKR_KEY SYSCFG_SKR_KEY_Msk
12298/******************************************************************************/
12299/* */
12300/* TIM */
12301/* */
12302/******************************************************************************/
12303/******************* Bit definition for TIM_CR1 register ********************/
12304#define TIM_CR1_CEN_Pos (0U)
12305#define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos)
12306#define TIM_CR1_CEN TIM_CR1_CEN_Msk
12307#define TIM_CR1_UDIS_Pos (1U)
12308#define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos)
12309#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk
12310#define TIM_CR1_URS_Pos (2U)
12311#define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos)
12312#define TIM_CR1_URS TIM_CR1_URS_Msk
12313#define TIM_CR1_OPM_Pos (3U)
12314#define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos)
12315#define TIM_CR1_OPM TIM_CR1_OPM_Msk
12316#define TIM_CR1_DIR_Pos (4U)
12317#define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos)
12318#define TIM_CR1_DIR TIM_CR1_DIR_Msk
12320#define TIM_CR1_CMS_Pos (5U)
12321#define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos)
12322#define TIM_CR1_CMS TIM_CR1_CMS_Msk
12323#define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos)
12324#define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos)
12326#define TIM_CR1_ARPE_Pos (7U)
12327#define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos)
12328#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk
12330#define TIM_CR1_CKD_Pos (8U)
12331#define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos)
12332#define TIM_CR1_CKD TIM_CR1_CKD_Msk
12333#define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos)
12334#define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos)
12336#define TIM_CR1_UIFREMAP_Pos (11U)
12337#define TIM_CR1_UIFREMAP_Msk (0x1UL << TIM_CR1_UIFREMAP_Pos)
12338#define TIM_CR1_UIFREMAP TIM_CR1_UIFREMAP_Msk
12340/******************* Bit definition for TIM_CR2 register ********************/
12341#define TIM_CR2_CCPC_Pos (0U)
12342#define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos)
12343#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk
12344#define TIM_CR2_CCUS_Pos (2U)
12345#define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos)
12346#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk
12347#define TIM_CR2_CCDS_Pos (3U)
12348#define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos)
12349#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk
12351#define TIM_CR2_MMS_Pos (4U)
12352#define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos)
12353#define TIM_CR2_MMS TIM_CR2_MMS_Msk
12354#define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos)
12355#define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos)
12356#define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos)
12358#define TIM_CR2_TI1S_Pos (7U)
12359#define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos)
12360#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk
12361#define TIM_CR2_OIS1_Pos (8U)
12362#define TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos)
12363#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk
12364#define TIM_CR2_OIS1N_Pos (9U)
12365#define TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos)
12366#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk
12367#define TIM_CR2_OIS2_Pos (10U)
12368#define TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos)
12369#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk
12370#define TIM_CR2_OIS2N_Pos (11U)
12371#define TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos)
12372#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk
12373#define TIM_CR2_OIS3_Pos (12U)
12374#define TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos)
12375#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk
12376#define TIM_CR2_OIS3N_Pos (13U)
12377#define TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos)
12378#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk
12379#define TIM_CR2_OIS4_Pos (14U)
12380#define TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos)
12381#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk
12382#define TIM_CR2_OIS5_Pos (16U)
12383#define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos)
12384#define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk
12385#define TIM_CR2_OIS6_Pos (18U)
12386#define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos)
12387#define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk
12389#define TIM_CR2_MMS2_Pos (20U)
12390#define TIM_CR2_MMS2_Msk (0xFUL << TIM_CR2_MMS2_Pos)
12391#define TIM_CR2_MMS2 TIM_CR2_MMS2_Msk
12392#define TIM_CR2_MMS2_0 (0x1UL << TIM_CR2_MMS2_Pos)
12393#define TIM_CR2_MMS2_1 (0x2UL << TIM_CR2_MMS2_Pos)
12394#define TIM_CR2_MMS2_2 (0x4UL << TIM_CR2_MMS2_Pos)
12395#define TIM_CR2_MMS2_3 (0x8UL << TIM_CR2_MMS2_Pos)
12397/******************* Bit definition for TIM_SMCR register *******************/
12398#define TIM_SMCR_SMS_Pos (0U)
12399#define TIM_SMCR_SMS_Msk (0x10007UL << TIM_SMCR_SMS_Pos)
12400#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk
12401#define TIM_SMCR_SMS_0 (0x00001UL << TIM_SMCR_SMS_Pos)
12402#define TIM_SMCR_SMS_1 (0x00002UL << TIM_SMCR_SMS_Pos)
12403#define TIM_SMCR_SMS_2 (0x00004UL << TIM_SMCR_SMS_Pos)
12404#define TIM_SMCR_SMS_3 (0x10000UL << TIM_SMCR_SMS_Pos)
12406#define TIM_SMCR_OCCS_Pos (3U)
12407#define TIM_SMCR_OCCS_Msk (0x1UL << TIM_SMCR_OCCS_Pos)
12408#define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk
12410#define TIM_SMCR_TS_Pos (4U)
12411#define TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos)
12412#define TIM_SMCR_TS TIM_SMCR_TS_Msk
12413#define TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos)
12414#define TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos)
12415#define TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos)
12417#define TIM_SMCR_MSM_Pos (7U)
12418#define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos)
12419#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk
12421#define TIM_SMCR_ETF_Pos (8U)
12422#define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos)
12423#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk
12424#define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos)
12425#define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos)
12426#define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos)
12427#define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos)
12429#define TIM_SMCR_ETPS_Pos (12U)
12430#define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos)
12431#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk
12432#define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos)
12433#define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos)
12435#define TIM_SMCR_ECE_Pos (14U)
12436#define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos)
12437#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk
12438#define TIM_SMCR_ETP_Pos (15U)
12439#define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos)
12440#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk
12442/******************* Bit definition for TIM_DIER register *******************/
12443#define TIM_DIER_UIE_Pos (0U)
12444#define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos)
12445#define TIM_DIER_UIE TIM_DIER_UIE_Msk
12446#define TIM_DIER_CC1IE_Pos (1U)
12447#define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos)
12448#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk
12449#define TIM_DIER_CC2IE_Pos (2U)
12450#define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos)
12451#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk
12452#define TIM_DIER_CC3IE_Pos (3U)
12453#define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos)
12454#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk
12455#define TIM_DIER_CC4IE_Pos (4U)
12456#define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos)
12457#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk
12458#define TIM_DIER_COMIE_Pos (5U)
12459#define TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos)
12460#define TIM_DIER_COMIE TIM_DIER_COMIE_Msk
12461#define TIM_DIER_TIE_Pos (6U)
12462#define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos)
12463#define TIM_DIER_TIE TIM_DIER_TIE_Msk
12464#define TIM_DIER_BIE_Pos (7U)
12465#define TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos)
12466#define TIM_DIER_BIE TIM_DIER_BIE_Msk
12467#define TIM_DIER_UDE_Pos (8U)
12468#define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos)
12469#define TIM_DIER_UDE TIM_DIER_UDE_Msk
12470#define TIM_DIER_CC1DE_Pos (9U)
12471#define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos)
12472#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk
12473#define TIM_DIER_CC2DE_Pos (10U)
12474#define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos)
12475#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk
12476#define TIM_DIER_CC3DE_Pos (11U)
12477#define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos)
12478#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk
12479#define TIM_DIER_CC4DE_Pos (12U)
12480#define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos)
12481#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk
12482#define TIM_DIER_COMDE_Pos (13U)
12483#define TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos)
12484#define TIM_DIER_COMDE TIM_DIER_COMDE_Msk
12485#define TIM_DIER_TDE_Pos (14U)
12486#define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos)
12487#define TIM_DIER_TDE TIM_DIER_TDE_Msk
12489/******************** Bit definition for TIM_SR register ********************/
12490#define TIM_SR_UIF_Pos (0U)
12491#define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos)
12492#define TIM_SR_UIF TIM_SR_UIF_Msk
12493#define TIM_SR_CC1IF_Pos (1U)
12494#define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos)
12495#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk
12496#define TIM_SR_CC2IF_Pos (2U)
12497#define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos)
12498#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk
12499#define TIM_SR_CC3IF_Pos (3U)
12500#define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos)
12501#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk
12502#define TIM_SR_CC4IF_Pos (4U)
12503#define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos)
12504#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk
12505#define TIM_SR_COMIF_Pos (5U)
12506#define TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos)
12507#define TIM_SR_COMIF TIM_SR_COMIF_Msk
12508#define TIM_SR_TIF_Pos (6U)
12509#define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos)
12510#define TIM_SR_TIF TIM_SR_TIF_Msk
12511#define TIM_SR_BIF_Pos (7U)
12512#define TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos)
12513#define TIM_SR_BIF TIM_SR_BIF_Msk
12514#define TIM_SR_B2IF_Pos (8U)
12515#define TIM_SR_B2IF_Msk (0x1UL << TIM_SR_B2IF_Pos)
12516#define TIM_SR_B2IF TIM_SR_B2IF_Msk
12517#define TIM_SR_CC1OF_Pos (9U)
12518#define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos)
12519#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk
12520#define TIM_SR_CC2OF_Pos (10U)
12521#define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos)
12522#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk
12523#define TIM_SR_CC3OF_Pos (11U)
12524#define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos)
12525#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk
12526#define TIM_SR_CC4OF_Pos (12U)
12527#define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos)
12528#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk
12529#define TIM_SR_SBIF_Pos (13U)
12530#define TIM_SR_SBIF_Msk (0x1UL << TIM_SR_SBIF_Pos)
12531#define TIM_SR_SBIF TIM_SR_SBIF_Msk
12532#define TIM_SR_CC5IF_Pos (16U)
12533#define TIM_SR_CC5IF_Msk (0x1UL << TIM_SR_CC5IF_Pos)
12534#define TIM_SR_CC5IF TIM_SR_CC5IF_Msk
12535#define TIM_SR_CC6IF_Pos (17U)
12536#define TIM_SR_CC6IF_Msk (0x1UL << TIM_SR_CC6IF_Pos)
12537#define TIM_SR_CC6IF TIM_SR_CC6IF_Msk
12540/******************* Bit definition for TIM_EGR register ********************/
12541#define TIM_EGR_UG_Pos (0U)
12542#define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos)
12543#define TIM_EGR_UG TIM_EGR_UG_Msk
12544#define TIM_EGR_CC1G_Pos (1U)
12545#define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos)
12546#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk
12547#define TIM_EGR_CC2G_Pos (2U)
12548#define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos)
12549#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk
12550#define TIM_EGR_CC3G_Pos (3U)
12551#define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos)
12552#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk
12553#define TIM_EGR_CC4G_Pos (4U)
12554#define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos)
12555#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk
12556#define TIM_EGR_COMG_Pos (5U)
12557#define TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos)
12558#define TIM_EGR_COMG TIM_EGR_COMG_Msk
12559#define TIM_EGR_TG_Pos (6U)
12560#define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos)
12561#define TIM_EGR_TG TIM_EGR_TG_Msk
12562#define TIM_EGR_BG_Pos (7U)
12563#define TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos)
12564#define TIM_EGR_BG TIM_EGR_BG_Msk
12565#define TIM_EGR_B2G_Pos (8U)
12566#define TIM_EGR_B2G_Msk (0x1UL << TIM_EGR_B2G_Pos)
12567#define TIM_EGR_B2G TIM_EGR_B2G_Msk
12570/****************** Bit definition for TIM_CCMR1 register *******************/
12571#define TIM_CCMR1_CC1S_Pos (0U)
12572#define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos)
12573#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk
12574#define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos)
12575#define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos)
12577#define TIM_CCMR1_OC1FE_Pos (2U)
12578#define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos)
12579#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk
12580#define TIM_CCMR1_OC1PE_Pos (3U)
12581#define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos)
12582#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk
12584#define TIM_CCMR1_OC1M_Pos (4U)
12585#define TIM_CCMR1_OC1M_Msk (0x1007UL << TIM_CCMR1_OC1M_Pos)
12586#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk
12587#define TIM_CCMR1_OC1M_0 (0x0001UL << TIM_CCMR1_OC1M_Pos)
12588#define TIM_CCMR1_OC1M_1 (0x0002UL << TIM_CCMR1_OC1M_Pos)
12589#define TIM_CCMR1_OC1M_2 (0x0004UL << TIM_CCMR1_OC1M_Pos)
12590#define TIM_CCMR1_OC1M_3 (0x1000UL << TIM_CCMR1_OC1M_Pos)
12592#define TIM_CCMR1_OC1CE_Pos (7U)
12593#define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos)
12594#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk
12596#define TIM_CCMR1_CC2S_Pos (8U)
12597#define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos)
12598#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk
12599#define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos)
12600#define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos)
12602#define TIM_CCMR1_OC2FE_Pos (10U)
12603#define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos)
12604#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk
12605#define TIM_CCMR1_OC2PE_Pos (11U)
12606#define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos)
12607#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk
12609#define TIM_CCMR1_OC2M_Pos (12U)
12610#define TIM_CCMR1_OC2M_Msk (0x1007UL << TIM_CCMR1_OC2M_Pos)
12611#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk
12612#define TIM_CCMR1_OC2M_0 (0x0001UL << TIM_CCMR1_OC2M_Pos)
12613#define TIM_CCMR1_OC2M_1 (0x0002UL << TIM_CCMR1_OC2M_Pos)
12614#define TIM_CCMR1_OC2M_2 (0x0004UL << TIM_CCMR1_OC2M_Pos)
12615#define TIM_CCMR1_OC2M_3 (0x1000UL << TIM_CCMR1_OC2M_Pos)
12617#define TIM_CCMR1_OC2CE_Pos (15U)
12618#define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos)
12619#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk
12621/*----------------------------------------------------------------------------*/
12622#define TIM_CCMR1_IC1PSC_Pos (2U)
12623#define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos)
12624#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk
12625#define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos)
12626#define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos)
12628#define TIM_CCMR1_IC1F_Pos (4U)
12629#define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos)
12630#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk
12631#define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos)
12632#define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos)
12633#define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos)
12634#define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos)
12636#define TIM_CCMR1_IC2PSC_Pos (10U)
12637#define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos)
12638#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk
12639#define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos)
12640#define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos)
12642#define TIM_CCMR1_IC2F_Pos (12U)
12643#define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos)
12644#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk
12645#define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos)
12646#define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos)
12647#define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos)
12648#define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos)
12650/****************** Bit definition for TIM_CCMR2 register *******************/
12651#define TIM_CCMR2_CC3S_Pos (0U)
12652#define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos)
12653#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk
12654#define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos)
12655#define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos)
12657#define TIM_CCMR2_OC3FE_Pos (2U)
12658#define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos)
12659#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk
12660#define TIM_CCMR2_OC3PE_Pos (3U)
12661#define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos)
12662#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk
12664#define TIM_CCMR2_OC3M_Pos (4U)
12665#define TIM_CCMR2_OC3M_Msk (0x1007UL << TIM_CCMR2_OC3M_Pos)
12666#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk
12667#define TIM_CCMR2_OC3M_0 (0x0001UL << TIM_CCMR2_OC3M_Pos)
12668#define TIM_CCMR2_OC3M_1 (0x0002UL << TIM_CCMR2_OC3M_Pos)
12669#define TIM_CCMR2_OC3M_2 (0x0004UL << TIM_CCMR2_OC3M_Pos)
12670#define TIM_CCMR2_OC3M_3 (0x1000UL << TIM_CCMR2_OC3M_Pos)
12672#define TIM_CCMR2_OC3CE_Pos (7U)
12673#define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos)
12674#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk
12676#define TIM_CCMR2_CC4S_Pos (8U)
12677#define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos)
12678#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk
12679#define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos)
12680#define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos)
12682#define TIM_CCMR2_OC4FE_Pos (10U)
12683#define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos)
12684#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk
12685#define TIM_CCMR2_OC4PE_Pos (11U)
12686#define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos)
12687#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk
12689#define TIM_CCMR2_OC4M_Pos (12U)
12690#define TIM_CCMR2_OC4M_Msk (0x1007UL << TIM_CCMR2_OC4M_Pos)
12691#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk
12692#define TIM_CCMR2_OC4M_0 (0x0001UL << TIM_CCMR2_OC4M_Pos)
12693#define TIM_CCMR2_OC4M_1 (0x0002UL << TIM_CCMR2_OC4M_Pos)
12694#define TIM_CCMR2_OC4M_2 (0x0004UL << TIM_CCMR2_OC4M_Pos)
12695#define TIM_CCMR2_OC4M_3 (0x1000UL << TIM_CCMR2_OC4M_Pos)
12697#define TIM_CCMR2_OC4CE_Pos (15U)
12698#define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos)
12699#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk
12701/*----------------------------------------------------------------------------*/
12702#define TIM_CCMR2_IC3PSC_Pos (2U)
12703#define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos)
12704#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk
12705#define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos)
12706#define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos)
12708#define TIM_CCMR2_IC3F_Pos (4U)
12709#define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos)
12710#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk
12711#define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos)
12712#define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos)
12713#define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos)
12714#define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos)
12716#define TIM_CCMR2_IC4PSC_Pos (10U)
12717#define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos)
12718#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk
12719#define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos)
12720#define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos)
12722#define TIM_CCMR2_IC4F_Pos (12U)
12723#define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos)
12724#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk
12725#define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos)
12726#define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos)
12727#define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos)
12728#define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos)
12730/****************** Bit definition for TIM_CCMR3 register *******************/
12731#define TIM_CCMR3_OC5FE_Pos (2U)
12732#define TIM_CCMR3_OC5FE_Msk (0x1UL << TIM_CCMR3_OC5FE_Pos)
12733#define TIM_CCMR3_OC5FE TIM_CCMR3_OC5FE_Msk
12734#define TIM_CCMR3_OC5PE_Pos (3U)
12735#define TIM_CCMR3_OC5PE_Msk (0x1UL << TIM_CCMR3_OC5PE_Pos)
12736#define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk
12738#define TIM_CCMR3_OC5M_Pos (4U)
12739#define TIM_CCMR3_OC5M_Msk (0x1007UL << TIM_CCMR3_OC5M_Pos)
12740#define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk
12741#define TIM_CCMR3_OC5M_0 (0x0001UL << TIM_CCMR3_OC5M_Pos)
12742#define TIM_CCMR3_OC5M_1 (0x0002UL << TIM_CCMR3_OC5M_Pos)
12743#define TIM_CCMR3_OC5M_2 (0x0004UL << TIM_CCMR3_OC5M_Pos)
12744#define TIM_CCMR3_OC5M_3 (0x1000UL << TIM_CCMR3_OC5M_Pos)
12746#define TIM_CCMR3_OC5CE_Pos (7U)
12747#define TIM_CCMR3_OC5CE_Msk (0x1UL << TIM_CCMR3_OC5CE_Pos)
12748#define TIM_CCMR3_OC5CE TIM_CCMR3_OC5CE_Msk
12750#define TIM_CCMR3_OC6FE_Pos (10U)
12751#define TIM_CCMR3_OC6FE_Msk (0x1UL << TIM_CCMR3_OC6FE_Pos)
12752#define TIM_CCMR3_OC6FE TIM_CCMR3_OC6FE_Msk
12753#define TIM_CCMR3_OC6PE_Pos (11U)
12754#define TIM_CCMR3_OC6PE_Msk (0x1UL << TIM_CCMR3_OC6PE_Pos)
12755#define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk
12757#define TIM_CCMR3_OC6M_Pos (12U)
12758#define TIM_CCMR3_OC6M_Msk (0x1007UL << TIM_CCMR3_OC6M_Pos)
12759#define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk
12760#define TIM_CCMR3_OC6M_0 (0x0001UL << TIM_CCMR3_OC6M_Pos)
12761#define TIM_CCMR3_OC6M_1 (0x0002UL << TIM_CCMR3_OC6M_Pos)
12762#define TIM_CCMR3_OC6M_2 (0x0004UL << TIM_CCMR3_OC6M_Pos)
12763#define TIM_CCMR3_OC6M_3 (0x1000UL << TIM_CCMR3_OC6M_Pos)
12765#define TIM_CCMR3_OC6CE_Pos (15U)
12766#define TIM_CCMR3_OC6CE_Msk (0x1UL << TIM_CCMR3_OC6CE_Pos)
12767#define TIM_CCMR3_OC6CE TIM_CCMR3_OC6CE_Msk
12769/******************* Bit definition for TIM_CCER register *******************/
12770#define TIM_CCER_CC1E_Pos (0U)
12771#define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos)
12772#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk
12773#define TIM_CCER_CC1P_Pos (1U)
12774#define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos)
12775#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk
12776#define TIM_CCER_CC1NE_Pos (2U)
12777#define TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos)
12778#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk
12779#define TIM_CCER_CC1NP_Pos (3U)
12780#define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos)
12781#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk
12782#define TIM_CCER_CC2E_Pos (4U)
12783#define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos)
12784#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk
12785#define TIM_CCER_CC2P_Pos (5U)
12786#define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos)
12787#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk
12788#define TIM_CCER_CC2NE_Pos (6U)
12789#define TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos)
12790#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk
12791#define TIM_CCER_CC2NP_Pos (7U)
12792#define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos)
12793#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk
12794#define TIM_CCER_CC3E_Pos (8U)
12795#define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos)
12796#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk
12797#define TIM_CCER_CC3P_Pos (9U)
12798#define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos)
12799#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk
12800#define TIM_CCER_CC3NE_Pos (10U)
12801#define TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos)
12802#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk
12803#define TIM_CCER_CC3NP_Pos (11U)
12804#define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos)
12805#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk
12806#define TIM_CCER_CC4E_Pos (12U)
12807#define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos)
12808#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk
12809#define TIM_CCER_CC4P_Pos (13U)
12810#define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos)
12811#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk
12812#define TIM_CCER_CC4NP_Pos (15U)
12813#define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos)
12814#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk
12815#define TIM_CCER_CC5E_Pos (16U)
12816#define TIM_CCER_CC5E_Msk (0x1UL << TIM_CCER_CC5E_Pos)
12817#define TIM_CCER_CC5E TIM_CCER_CC5E_Msk
12818#define TIM_CCER_CC5P_Pos (17U)
12819#define TIM_CCER_CC5P_Msk (0x1UL << TIM_CCER_CC5P_Pos)
12820#define TIM_CCER_CC5P TIM_CCER_CC5P_Msk
12821#define TIM_CCER_CC6E_Pos (20U)
12822#define TIM_CCER_CC6E_Msk (0x1UL << TIM_CCER_CC6E_Pos)
12823#define TIM_CCER_CC6E TIM_CCER_CC6E_Msk
12824#define TIM_CCER_CC6P_Pos (21U)
12825#define TIM_CCER_CC6P_Msk (0x1UL << TIM_CCER_CC6P_Pos)
12826#define TIM_CCER_CC6P TIM_CCER_CC6P_Msk
12828/******************* Bit definition for TIM_CNT register ********************/
12829#define TIM_CNT_CNT_Pos (0U)
12830#define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)
12831#define TIM_CNT_CNT TIM_CNT_CNT_Msk
12832#define TIM_CNT_UIFCPY_Pos (31U)
12833#define TIM_CNT_UIFCPY_Msk (0x1UL << TIM_CNT_UIFCPY_Pos)
12834#define TIM_CNT_UIFCPY TIM_CNT_UIFCPY_Msk
12836/******************* Bit definition for TIM_PSC register ********************/
12837#define TIM_PSC_PSC_Pos (0U)
12838#define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos)
12839#define TIM_PSC_PSC TIM_PSC_PSC_Msk
12841/******************* Bit definition for TIM_ARR register ********************/
12842#define TIM_ARR_ARR_Pos (0U)
12843#define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)
12844#define TIM_ARR_ARR TIM_ARR_ARR_Msk
12846/******************* Bit definition for TIM_RCR register ********************/
12847#define TIM_RCR_REP_Pos (0U)
12848#define TIM_RCR_REP_Msk (0xFFFFUL << TIM_RCR_REP_Pos)
12849#define TIM_RCR_REP TIM_RCR_REP_Msk
12851/******************* Bit definition for TIM_CCR1 register *******************/
12852#define TIM_CCR1_CCR1_Pos (0U)
12853#define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos)
12854#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk
12856/******************* Bit definition for TIM_CCR2 register *******************/
12857#define TIM_CCR2_CCR2_Pos (0U)
12858#define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos)
12859#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk
12861/******************* Bit definition for TIM_CCR3 register *******************/
12862#define TIM_CCR3_CCR3_Pos (0U)
12863#define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos)
12864#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk
12866/******************* Bit definition for TIM_CCR4 register *******************/
12867#define TIM_CCR4_CCR4_Pos (0U)
12868#define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos)
12869#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk
12871/******************* Bit definition for TIM_CCR5 register *******************/
12872#define TIM_CCR5_CCR5_Pos (0U)
12873#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos)
12874#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk
12875#define TIM_CCR5_GC5C1_Pos (29U)
12876#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos)
12877#define TIM_CCR5_GC5C1 TIM_CCR5_GC5C1_Msk
12878#define TIM_CCR5_GC5C2_Pos (30U)
12879#define TIM_CCR5_GC5C2_Msk (0x1UL << TIM_CCR5_GC5C2_Pos)
12880#define TIM_CCR5_GC5C2 TIM_CCR5_GC5C2_Msk
12881#define TIM_CCR5_GC5C3_Pos (31U)
12882#define TIM_CCR5_GC5C3_Msk (0x1UL << TIM_CCR5_GC5C3_Pos)
12883#define TIM_CCR5_GC5C3 TIM_CCR5_GC5C3_Msk
12885/******************* Bit definition for TIM_CCR6 register *******************/
12886#define TIM_CCR6_CCR6_Pos (0U)
12887#define TIM_CCR6_CCR6_Msk (0xFFFFUL << TIM_CCR6_CCR6_Pos)
12888#define TIM_CCR6_CCR6 TIM_CCR6_CCR6_Msk
12890/******************* Bit definition for TIM_BDTR register *******************/
12891#define TIM_BDTR_DTG_Pos (0U)
12892#define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos)
12893#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk
12894#define TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos)
12895#define TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos)
12896#define TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos)
12897#define TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos)
12898#define TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos)
12899#define TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos)
12900#define TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos)
12901#define TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos)
12903#define TIM_BDTR_LOCK_Pos (8U)
12904#define TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos)
12905#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk
12906#define TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos)
12907#define TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos)
12909#define TIM_BDTR_OSSI_Pos (10U)
12910#define TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos)
12911#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk
12912#define TIM_BDTR_OSSR_Pos (11U)
12913#define TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos)
12914#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk
12915#define TIM_BDTR_BKE_Pos (12U)
12916#define TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos)
12917#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk
12918#define TIM_BDTR_BKP_Pos (13U)
12919#define TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos)
12920#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk
12921#define TIM_BDTR_AOE_Pos (14U)
12922#define TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos)
12923#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk
12924#define TIM_BDTR_MOE_Pos (15U)
12925#define TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos)
12926#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk
12928#define TIM_BDTR_BKF_Pos (16U)
12929#define TIM_BDTR_BKF_Msk (0xFUL << TIM_BDTR_BKF_Pos)
12930#define TIM_BDTR_BKF TIM_BDTR_BKF_Msk
12931#define TIM_BDTR_BK2F_Pos (20U)
12932#define TIM_BDTR_BK2F_Msk (0xFUL << TIM_BDTR_BK2F_Pos)
12933#define TIM_BDTR_BK2F TIM_BDTR_BK2F_Msk
12935#define TIM_BDTR_BK2E_Pos (24U)
12936#define TIM_BDTR_BK2E_Msk (0x1UL << TIM_BDTR_BK2E_Pos)
12937#define TIM_BDTR_BK2E TIM_BDTR_BK2E_Msk
12938#define TIM_BDTR_BK2P_Pos (25U)
12939#define TIM_BDTR_BK2P_Msk (0x1UL << TIM_BDTR_BK2P_Pos)
12940#define TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk
12942/******************* Bit definition for TIM_DCR register ********************/
12943#define TIM_DCR_DBA_Pos (0U)
12944#define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos)
12945#define TIM_DCR_DBA TIM_DCR_DBA_Msk
12946#define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos)
12947#define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos)
12948#define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos)
12949#define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos)
12950#define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos)
12952#define TIM_DCR_DBL_Pos (8U)
12953#define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos)
12954#define TIM_DCR_DBL TIM_DCR_DBL_Msk
12955#define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos)
12956#define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos)
12957#define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos)
12958#define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos)
12959#define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos)
12961/******************* Bit definition for TIM_DMAR register *******************/
12962#define TIM_DMAR_DMAB_Pos (0U)
12963#define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos)
12964#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk
12966/******************* Bit definition for TIM1_OR1 register *******************/
12967#define TIM1_OR1_ETR_ADC1_RMP_Pos (0U)
12968#define TIM1_OR1_ETR_ADC1_RMP_Msk (0x3UL << TIM1_OR1_ETR_ADC1_RMP_Pos)
12969#define TIM1_OR1_ETR_ADC1_RMP TIM1_OR1_ETR_ADC1_RMP_Msk
12970#define TIM1_OR1_ETR_ADC1_RMP_0 (0x1UL << TIM1_OR1_ETR_ADC1_RMP_Pos)
12971#define TIM1_OR1_ETR_ADC1_RMP_1 (0x2UL << TIM1_OR1_ETR_ADC1_RMP_Pos)
12973#define TIM1_OR1_TI1_RMP_Pos (4U)
12974#define TIM1_OR1_TI1_RMP_Msk (0x1UL << TIM1_OR1_TI1_RMP_Pos)
12975#define TIM1_OR1_TI1_RMP TIM1_OR1_TI1_RMP_Msk
12977/******************* Bit definition for TIM1_OR2 register *******************/
12978#define TIM1_OR2_BKINE_Pos (0U)
12979#define TIM1_OR2_BKINE_Msk (0x1UL << TIM1_OR2_BKINE_Pos)
12980#define TIM1_OR2_BKINE TIM1_OR2_BKINE_Msk
12981#define TIM1_OR2_BKCMP1E_Pos (1U)
12982#define TIM1_OR2_BKCMP1E_Msk (0x1UL << TIM1_OR2_BKCMP1E_Pos)
12983#define TIM1_OR2_BKCMP1E TIM1_OR2_BKCMP1E_Msk
12984#define TIM1_OR2_BKCMP2E_Pos (2U)
12985#define TIM1_OR2_BKCMP2E_Msk (0x1UL << TIM1_OR2_BKCMP2E_Pos)
12986#define TIM1_OR2_BKCMP2E TIM1_OR2_BKCMP2E_Msk
12987#define TIM1_OR2_BKINP_Pos (9U)
12988#define TIM1_OR2_BKINP_Msk (0x1UL << TIM1_OR2_BKINP_Pos)
12989#define TIM1_OR2_BKINP TIM1_OR2_BKINP_Msk
12990#define TIM1_OR2_BKCMP1P_Pos (10U)
12991#define TIM1_OR2_BKCMP1P_Msk (0x1UL << TIM1_OR2_BKCMP1P_Pos)
12992#define TIM1_OR2_BKCMP1P TIM1_OR2_BKCMP1P_Msk
12993#define TIM1_OR2_BKCMP2P_Pos (11U)
12994#define TIM1_OR2_BKCMP2P_Msk (0x1UL << TIM1_OR2_BKCMP2P_Pos)
12995#define TIM1_OR2_BKCMP2P TIM1_OR2_BKCMP2P_Msk
12997#define TIM1_OR2_ETRSEL_Pos (14U)
12998#define TIM1_OR2_ETRSEL_Msk (0x7UL << TIM1_OR2_ETRSEL_Pos)
12999#define TIM1_OR2_ETRSEL TIM1_OR2_ETRSEL_Msk
13000#define TIM1_OR2_ETRSEL_0 (0x1UL << TIM1_OR2_ETRSEL_Pos)
13001#define TIM1_OR2_ETRSEL_1 (0x2UL << TIM1_OR2_ETRSEL_Pos)
13002#define TIM1_OR2_ETRSEL_2 (0x4UL << TIM1_OR2_ETRSEL_Pos)
13004/******************* Bit definition for TIM1_OR3 register *******************/
13005#define TIM1_OR3_BK2INE_Pos (0U)
13006#define TIM1_OR3_BK2INE_Msk (0x1UL << TIM1_OR3_BK2INE_Pos)
13007#define TIM1_OR3_BK2INE TIM1_OR3_BK2INE_Msk
13008#define TIM1_OR3_BK2CMP1E_Pos (1U)
13009#define TIM1_OR3_BK2CMP1E_Msk (0x1UL << TIM1_OR3_BK2CMP1E_Pos)
13010#define TIM1_OR3_BK2CMP1E TIM1_OR3_BK2CMP1E_Msk
13011#define TIM1_OR3_BK2CMP2E_Pos (2U)
13012#define TIM1_OR3_BK2CMP2E_Msk (0x1UL << TIM1_OR3_BK2CMP2E_Pos)
13013#define TIM1_OR3_BK2CMP2E TIM1_OR3_BK2CMP2E_Msk
13014#define TIM1_OR3_BK2INP_Pos (9U)
13015#define TIM1_OR3_BK2INP_Msk (0x1UL << TIM1_OR3_BK2INP_Pos)
13016#define TIM1_OR3_BK2INP TIM1_OR3_BK2INP_Msk
13017#define TIM1_OR3_BK2CMP1P_Pos (10U)
13018#define TIM1_OR3_BK2CMP1P_Msk (0x1UL << TIM1_OR3_BK2CMP1P_Pos)
13019#define TIM1_OR3_BK2CMP1P TIM1_OR3_BK2CMP1P_Msk
13020#define TIM1_OR3_BK2CMP2P_Pos (11U)
13021#define TIM1_OR3_BK2CMP2P_Msk (0x1UL << TIM1_OR3_BK2CMP2P_Pos)
13022#define TIM1_OR3_BK2CMP2P TIM1_OR3_BK2CMP2P_Msk
13025/******************* Bit definition for TIM2_OR1 register *******************/
13026#define TIM2_OR1_ITR1_RMP_Pos (0U)
13027#define TIM2_OR1_ITR1_RMP_Msk (0x1UL << TIM2_OR1_ITR1_RMP_Pos)
13028#define TIM2_OR1_ITR1_RMP TIM2_OR1_ITR1_RMP_Msk
13029#define TIM2_OR1_ETR1_RMP_Pos (1U)
13030#define TIM2_OR1_ETR1_RMP_Msk (0x1UL << TIM2_OR1_ETR1_RMP_Pos)
13031#define TIM2_OR1_ETR1_RMP TIM2_OR1_ETR1_RMP_Msk
13033#define TIM2_OR1_TI4_RMP_Pos (2U)
13034#define TIM2_OR1_TI4_RMP_Msk (0x3UL << TIM2_OR1_TI4_RMP_Pos)
13035#define TIM2_OR1_TI4_RMP TIM2_OR1_TI4_RMP_Msk
13036#define TIM2_OR1_TI4_RMP_0 (0x1UL << TIM2_OR1_TI4_RMP_Pos)
13037#define TIM2_OR1_TI4_RMP_1 (0x2UL << TIM2_OR1_TI4_RMP_Pos)
13039/******************* Bit definition for TIM2_OR2 register *******************/
13040#define TIM2_OR2_ETRSEL_Pos (14U)
13041#define TIM2_OR2_ETRSEL_Msk (0x7UL << TIM2_OR2_ETRSEL_Pos)
13042#define TIM2_OR2_ETRSEL TIM2_OR2_ETRSEL_Msk
13043#define TIM2_OR2_ETRSEL_0 (0x1UL << TIM2_OR2_ETRSEL_Pos)
13044#define TIM2_OR2_ETRSEL_1 (0x2UL << TIM2_OR2_ETRSEL_Pos)
13045#define TIM2_OR2_ETRSEL_2 (0x4UL << TIM2_OR2_ETRSEL_Pos)
13048/******************* Bit definition for TIM15_OR1 register ******************/
13049#define TIM15_OR1_TI1_RMP_Pos (0U)
13050#define TIM15_OR1_TI1_RMP_Msk (0x1UL << TIM15_OR1_TI1_RMP_Pos)
13051#define TIM15_OR1_TI1_RMP TIM15_OR1_TI1_RMP_Msk
13053#define TIM15_OR1_ENCODER_MODE_Pos (1U)
13054#define TIM15_OR1_ENCODER_MODE_Msk (0x3UL << TIM15_OR1_ENCODER_MODE_Pos)
13055#define TIM15_OR1_ENCODER_MODE TIM15_OR1_ENCODER_MODE_Msk
13056#define TIM15_OR1_ENCODER_MODE_0 (0x1UL << TIM15_OR1_ENCODER_MODE_Pos)
13057#define TIM15_OR1_ENCODER_MODE_1 (0x2UL << TIM15_OR1_ENCODER_MODE_Pos)
13059/******************* Bit definition for TIM15_OR2 register ******************/
13060#define TIM15_OR2_BKINE_Pos (0U)
13061#define TIM15_OR2_BKINE_Msk (0x1UL << TIM15_OR2_BKINE_Pos)
13062#define TIM15_OR2_BKINE TIM15_OR2_BKINE_Msk
13063#define TIM15_OR2_BKCMP1E_Pos (1U)
13064#define TIM15_OR2_BKCMP1E_Msk (0x1UL << TIM15_OR2_BKCMP1E_Pos)
13065#define TIM15_OR2_BKCMP1E TIM15_OR2_BKCMP1E_Msk
13066#define TIM15_OR2_BKCMP2E_Pos (2U)
13067#define TIM15_OR2_BKCMP2E_Msk (0x1UL << TIM15_OR2_BKCMP2E_Pos)
13068#define TIM15_OR2_BKCMP2E TIM15_OR2_BKCMP2E_Msk
13069#define TIM15_OR2_BKINP_Pos (9U)
13070#define TIM15_OR2_BKINP_Msk (0x1UL << TIM15_OR2_BKINP_Pos)
13071#define TIM15_OR2_BKINP TIM15_OR2_BKINP_Msk
13072#define TIM15_OR2_BKCMP1P_Pos (10U)
13073#define TIM15_OR2_BKCMP1P_Msk (0x1UL << TIM15_OR2_BKCMP1P_Pos)
13074#define TIM15_OR2_BKCMP1P TIM15_OR2_BKCMP1P_Msk
13075#define TIM15_OR2_BKCMP2P_Pos (11U)
13076#define TIM15_OR2_BKCMP2P_Msk (0x1UL << TIM15_OR2_BKCMP2P_Pos)
13077#define TIM15_OR2_BKCMP2P TIM15_OR2_BKCMP2P_Msk
13079/******************* Bit definition for TIM16_OR1 register ******************/
13080#define TIM16_OR1_TI1_RMP_Pos (0U)
13081#define TIM16_OR1_TI1_RMP_Msk (0x7UL << TIM16_OR1_TI1_RMP_Pos)
13082#define TIM16_OR1_TI1_RMP TIM16_OR1_TI1_RMP_Msk
13083#define TIM16_OR1_TI1_RMP_0 (0x1UL << TIM16_OR1_TI1_RMP_Pos)
13084#define TIM16_OR1_TI1_RMP_1 (0x2UL << TIM16_OR1_TI1_RMP_Pos)
13085#define TIM16_OR1_TI1_RMP_2 (0x4UL << TIM16_OR1_TI1_RMP_Pos)
13087/******************* Bit definition for TIM16_OR2 register ******************/
13088#define TIM16_OR2_BKINE_Pos (0U)
13089#define TIM16_OR2_BKINE_Msk (0x1UL << TIM16_OR2_BKINE_Pos)
13090#define TIM16_OR2_BKINE TIM16_OR2_BKINE_Msk
13091#define TIM16_OR2_BKCMP1E_Pos (1U)
13092#define TIM16_OR2_BKCMP1E_Msk (0x1UL << TIM16_OR2_BKCMP1E_Pos)
13093#define TIM16_OR2_BKCMP1E TIM16_OR2_BKCMP1E_Msk
13094#define TIM16_OR2_BKCMP2E_Pos (2U)
13095#define TIM16_OR2_BKCMP2E_Msk (0x1UL << TIM16_OR2_BKCMP2E_Pos)
13096#define TIM16_OR2_BKCMP2E TIM16_OR2_BKCMP2E_Msk
13097#define TIM16_OR2_BKINP_Pos (9U)
13098#define TIM16_OR2_BKINP_Msk (0x1UL << TIM16_OR2_BKINP_Pos)
13099#define TIM16_OR2_BKINP TIM16_OR2_BKINP_Msk
13100#define TIM16_OR2_BKCMP1P_Pos (10U)
13101#define TIM16_OR2_BKCMP1P_Msk (0x1UL << TIM16_OR2_BKCMP1P_Pos)
13102#define TIM16_OR2_BKCMP1P TIM16_OR2_BKCMP1P_Msk
13103#define TIM16_OR2_BKCMP2P_Pos (11U)
13104#define TIM16_OR2_BKCMP2P_Msk (0x1UL << TIM16_OR2_BKCMP2P_Pos)
13105#define TIM16_OR2_BKCMP2P TIM16_OR2_BKCMP2P_Msk
13108/******************************************************************************/
13109/* */
13110/* Low Power Timer (LPTIM) */
13111/* */
13112/******************************************************************************/
13113/****************** Bit definition for LPTIM_ISR register *******************/
13114#define LPTIM_ISR_CMPM_Pos (0U)
13115#define LPTIM_ISR_CMPM_Msk (0x1UL << LPTIM_ISR_CMPM_Pos)
13116#define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk
13117#define LPTIM_ISR_ARRM_Pos (1U)
13118#define LPTIM_ISR_ARRM_Msk (0x1UL << LPTIM_ISR_ARRM_Pos)
13119#define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk
13120#define LPTIM_ISR_EXTTRIG_Pos (2U)
13121#define LPTIM_ISR_EXTTRIG_Msk (0x1UL << LPTIM_ISR_EXTTRIG_Pos)
13122#define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk
13123#define LPTIM_ISR_CMPOK_Pos (3U)
13124#define LPTIM_ISR_CMPOK_Msk (0x1UL << LPTIM_ISR_CMPOK_Pos)
13125#define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk
13126#define LPTIM_ISR_ARROK_Pos (4U)
13127#define LPTIM_ISR_ARROK_Msk (0x1UL << LPTIM_ISR_ARROK_Pos)
13128#define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk
13129#define LPTIM_ISR_UP_Pos (5U)
13130#define LPTIM_ISR_UP_Msk (0x1UL << LPTIM_ISR_UP_Pos)
13131#define LPTIM_ISR_UP LPTIM_ISR_UP_Msk
13132#define LPTIM_ISR_DOWN_Pos (6U)
13133#define LPTIM_ISR_DOWN_Msk (0x1UL << LPTIM_ISR_DOWN_Pos)
13134#define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk
13136/****************** Bit definition for LPTIM_ICR register *******************/
13137#define LPTIM_ICR_CMPMCF_Pos (0U)
13138#define LPTIM_ICR_CMPMCF_Msk (0x1UL << LPTIM_ICR_CMPMCF_Pos)
13139#define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk
13140#define LPTIM_ICR_ARRMCF_Pos (1U)
13141#define LPTIM_ICR_ARRMCF_Msk (0x1UL << LPTIM_ICR_ARRMCF_Pos)
13142#define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk
13143#define LPTIM_ICR_EXTTRIGCF_Pos (2U)
13144#define LPTIM_ICR_EXTTRIGCF_Msk (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)
13145#define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk
13146#define LPTIM_ICR_CMPOKCF_Pos (3U)
13147#define LPTIM_ICR_CMPOKCF_Msk (0x1UL << LPTIM_ICR_CMPOKCF_Pos)
13148#define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk
13149#define LPTIM_ICR_ARROKCF_Pos (4U)
13150#define LPTIM_ICR_ARROKCF_Msk (0x1UL << LPTIM_ICR_ARROKCF_Pos)
13151#define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk
13152#define LPTIM_ICR_UPCF_Pos (5U)
13153#define LPTIM_ICR_UPCF_Msk (0x1UL << LPTIM_ICR_UPCF_Pos)
13154#define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk
13155#define LPTIM_ICR_DOWNCF_Pos (6U)
13156#define LPTIM_ICR_DOWNCF_Msk (0x1UL << LPTIM_ICR_DOWNCF_Pos)
13157#define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk
13159/****************** Bit definition for LPTIM_IER register ********************/
13160#define LPTIM_IER_CMPMIE_Pos (0U)
13161#define LPTIM_IER_CMPMIE_Msk (0x1UL << LPTIM_IER_CMPMIE_Pos)
13162#define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk
13163#define LPTIM_IER_ARRMIE_Pos (1U)
13164#define LPTIM_IER_ARRMIE_Msk (0x1UL << LPTIM_IER_ARRMIE_Pos)
13165#define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk
13166#define LPTIM_IER_EXTTRIGIE_Pos (2U)
13167#define LPTIM_IER_EXTTRIGIE_Msk (0x1UL << LPTIM_IER_EXTTRIGIE_Pos)
13168#define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk
13169#define LPTIM_IER_CMPOKIE_Pos (3U)
13170#define LPTIM_IER_CMPOKIE_Msk (0x1UL << LPTIM_IER_CMPOKIE_Pos)
13171#define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk
13172#define LPTIM_IER_ARROKIE_Pos (4U)
13173#define LPTIM_IER_ARROKIE_Msk (0x1UL << LPTIM_IER_ARROKIE_Pos)
13174#define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk
13175#define LPTIM_IER_UPIE_Pos (5U)
13176#define LPTIM_IER_UPIE_Msk (0x1UL << LPTIM_IER_UPIE_Pos)
13177#define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk
13178#define LPTIM_IER_DOWNIE_Pos (6U)
13179#define LPTIM_IER_DOWNIE_Msk (0x1UL << LPTIM_IER_DOWNIE_Pos)
13180#define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk
13182/****************** Bit definition for LPTIM_CFGR register *******************/
13183#define LPTIM_CFGR_CKSEL_Pos (0U)
13184#define LPTIM_CFGR_CKSEL_Msk (0x1UL << LPTIM_CFGR_CKSEL_Pos)
13185#define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk
13187#define LPTIM_CFGR_CKPOL_Pos (1U)
13188#define LPTIM_CFGR_CKPOL_Msk (0x3UL << LPTIM_CFGR_CKPOL_Pos)
13189#define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk
13190#define LPTIM_CFGR_CKPOL_0 (0x1UL << LPTIM_CFGR_CKPOL_Pos)
13191#define LPTIM_CFGR_CKPOL_1 (0x2UL << LPTIM_CFGR_CKPOL_Pos)
13193#define LPTIM_CFGR_CKFLT_Pos (3U)
13194#define LPTIM_CFGR_CKFLT_Msk (0x3UL << LPTIM_CFGR_CKFLT_Pos)
13195#define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk
13196#define LPTIM_CFGR_CKFLT_0 (0x1UL << LPTIM_CFGR_CKFLT_Pos)
13197#define LPTIM_CFGR_CKFLT_1 (0x2UL << LPTIM_CFGR_CKFLT_Pos)
13199#define LPTIM_CFGR_TRGFLT_Pos (6U)
13200#define LPTIM_CFGR_TRGFLT_Msk (0x3UL << LPTIM_CFGR_TRGFLT_Pos)
13201#define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk
13202#define LPTIM_CFGR_TRGFLT_0 (0x1UL << LPTIM_CFGR_TRGFLT_Pos)
13203#define LPTIM_CFGR_TRGFLT_1 (0x2UL << LPTIM_CFGR_TRGFLT_Pos)
13205#define LPTIM_CFGR_PRESC_Pos (9U)
13206#define LPTIM_CFGR_PRESC_Msk (0x7UL << LPTIM_CFGR_PRESC_Pos)
13207#define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk
13208#define LPTIM_CFGR_PRESC_0 (0x1UL << LPTIM_CFGR_PRESC_Pos)
13209#define LPTIM_CFGR_PRESC_1 (0x2UL << LPTIM_CFGR_PRESC_Pos)
13210#define LPTIM_CFGR_PRESC_2 (0x4UL << LPTIM_CFGR_PRESC_Pos)
13212#define LPTIM_CFGR_TRIGSEL_Pos (13U)
13213#define LPTIM_CFGR_TRIGSEL_Msk (0x7UL << LPTIM_CFGR_TRIGSEL_Pos)
13214#define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk
13215#define LPTIM_CFGR_TRIGSEL_0 (0x1UL << LPTIM_CFGR_TRIGSEL_Pos)
13216#define LPTIM_CFGR_TRIGSEL_1 (0x2UL << LPTIM_CFGR_TRIGSEL_Pos)
13217#define LPTIM_CFGR_TRIGSEL_2 (0x4UL << LPTIM_CFGR_TRIGSEL_Pos)
13219#define LPTIM_CFGR_TRIGEN_Pos (17U)
13220#define LPTIM_CFGR_TRIGEN_Msk (0x3UL << LPTIM_CFGR_TRIGEN_Pos)
13221#define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk
13222#define LPTIM_CFGR_TRIGEN_0 (0x1UL << LPTIM_CFGR_TRIGEN_Pos)
13223#define LPTIM_CFGR_TRIGEN_1 (0x2UL << LPTIM_CFGR_TRIGEN_Pos)
13225#define LPTIM_CFGR_TIMOUT_Pos (19U)
13226#define LPTIM_CFGR_TIMOUT_Msk (0x1UL << LPTIM_CFGR_TIMOUT_Pos)
13227#define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk
13228#define LPTIM_CFGR_WAVE_Pos (20U)
13229#define LPTIM_CFGR_WAVE_Msk (0x1UL << LPTIM_CFGR_WAVE_Pos)
13230#define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk
13231#define LPTIM_CFGR_WAVPOL_Pos (21U)
13232#define LPTIM_CFGR_WAVPOL_Msk (0x1UL << LPTIM_CFGR_WAVPOL_Pos)
13233#define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk
13234#define LPTIM_CFGR_PRELOAD_Pos (22U)
13235#define LPTIM_CFGR_PRELOAD_Msk (0x1UL << LPTIM_CFGR_PRELOAD_Pos)
13236#define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk
13237#define LPTIM_CFGR_COUNTMODE_Pos (23U)
13238#define LPTIM_CFGR_COUNTMODE_Msk (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)
13239#define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk
13240#define LPTIM_CFGR_ENC_Pos (24U)
13241#define LPTIM_CFGR_ENC_Msk (0x1UL << LPTIM_CFGR_ENC_Pos)
13242#define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk
13244/****************** Bit definition for LPTIM_CR register ********************/
13245#define LPTIM_CR_ENABLE_Pos (0U)
13246#define LPTIM_CR_ENABLE_Msk (0x1UL << LPTIM_CR_ENABLE_Pos)
13247#define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk
13248#define LPTIM_CR_SNGSTRT_Pos (1U)
13249#define LPTIM_CR_SNGSTRT_Msk (0x1UL << LPTIM_CR_SNGSTRT_Pos)
13250#define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk
13251#define LPTIM_CR_CNTSTRT_Pos (2U)
13252#define LPTIM_CR_CNTSTRT_Msk (0x1UL << LPTIM_CR_CNTSTRT_Pos)
13253#define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk
13255/****************** Bit definition for LPTIM_CMP register *******************/
13256#define LPTIM_CMP_CMP_Pos (0U)
13257#define LPTIM_CMP_CMP_Msk (0xFFFFUL << LPTIM_CMP_CMP_Pos)
13258#define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk
13260/****************** Bit definition for LPTIM_ARR register *******************/
13261#define LPTIM_ARR_ARR_Pos (0U)
13262#define LPTIM_ARR_ARR_Msk (0xFFFFUL << LPTIM_ARR_ARR_Pos)
13263#define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk
13265/****************** Bit definition for LPTIM_CNT register *******************/
13266#define LPTIM_CNT_CNT_Pos (0U)
13267#define LPTIM_CNT_CNT_Msk (0xFFFFUL << LPTIM_CNT_CNT_Pos)
13268#define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk
13270/****************** Bit definition for LPTIM_OR register ********************/
13271#define LPTIM_OR_OR_Pos (0U)
13272#define LPTIM_OR_OR_Msk (0x3UL << LPTIM_OR_OR_Pos)
13273#define LPTIM_OR_OR LPTIM_OR_OR_Msk
13274#define LPTIM_OR_OR_0 (0x1UL << LPTIM_OR_OR_Pos)
13275#define LPTIM_OR_OR_1 (0x2UL << LPTIM_OR_OR_Pos)
13277/******************************************************************************/
13278/* */
13279/* Analog Comparators (COMP) */
13280/* */
13281/******************************************************************************/
13282/********************** Bit definition for COMP_CSR register ****************/
13283#define COMP_CSR_EN_Pos (0U)
13284#define COMP_CSR_EN_Msk (0x1UL << COMP_CSR_EN_Pos)
13285#define COMP_CSR_EN COMP_CSR_EN_Msk
13287#define COMP_CSR_PWRMODE_Pos (2U)
13288#define COMP_CSR_PWRMODE_Msk (0x3UL << COMP_CSR_PWRMODE_Pos)
13289#define COMP_CSR_PWRMODE COMP_CSR_PWRMODE_Msk
13290#define COMP_CSR_PWRMODE_0 (0x1UL << COMP_CSR_PWRMODE_Pos)
13291#define COMP_CSR_PWRMODE_1 (0x2UL << COMP_CSR_PWRMODE_Pos)
13293#define COMP_CSR_INMSEL_Pos (4U)
13294#define COMP_CSR_INMSEL_Msk (0x7UL << COMP_CSR_INMSEL_Pos)
13295#define COMP_CSR_INMSEL COMP_CSR_INMSEL_Msk
13296#define COMP_CSR_INMSEL_0 (0x1UL << COMP_CSR_INMSEL_Pos)
13297#define COMP_CSR_INMSEL_1 (0x2UL << COMP_CSR_INMSEL_Pos)
13298#define COMP_CSR_INMSEL_2 (0x4UL << COMP_CSR_INMSEL_Pos)
13300#define COMP_CSR_INPSEL_Pos (7U)
13301#define COMP_CSR_INPSEL_Msk (0x3UL << COMP_CSR_INPSEL_Pos)
13302#define COMP_CSR_INPSEL COMP_CSR_INPSEL_Msk
13303#define COMP_CSR_INPSEL_0 (0x1UL << COMP_CSR_INPSEL_Pos)
13304#define COMP_CSR_INPSEL_1 (0x2UL << COMP_CSR_INPSEL_Pos)
13306#define COMP_CSR_WINMODE_Pos (9U)
13307#define COMP_CSR_WINMODE_Msk (0x1UL << COMP_CSR_WINMODE_Pos)
13308#define COMP_CSR_WINMODE COMP_CSR_WINMODE_Msk
13310#define COMP_CSR_POLARITY_Pos (15U)
13311#define COMP_CSR_POLARITY_Msk (0x1UL << COMP_CSR_POLARITY_Pos)
13312#define COMP_CSR_POLARITY COMP_CSR_POLARITY_Msk
13314#define COMP_CSR_HYST_Pos (16U)
13315#define COMP_CSR_HYST_Msk (0x3UL << COMP_CSR_HYST_Pos)
13316#define COMP_CSR_HYST COMP_CSR_HYST_Msk
13317#define COMP_CSR_HYST_0 (0x1UL << COMP_CSR_HYST_Pos)
13318#define COMP_CSR_HYST_1 (0x2UL << COMP_CSR_HYST_Pos)
13320#define COMP_CSR_BLANKING_Pos (18U)
13321#define COMP_CSR_BLANKING_Msk (0x7UL << COMP_CSR_BLANKING_Pos)
13322#define COMP_CSR_BLANKING COMP_CSR_BLANKING_Msk
13323#define COMP_CSR_BLANKING_0 (0x1UL << COMP_CSR_BLANKING_Pos)
13324#define COMP_CSR_BLANKING_1 (0x2UL << COMP_CSR_BLANKING_Pos)
13325#define COMP_CSR_BLANKING_2 (0x4UL << COMP_CSR_BLANKING_Pos)
13327#define COMP_CSR_BRGEN_Pos (22U)
13328#define COMP_CSR_BRGEN_Msk (0x1UL << COMP_CSR_BRGEN_Pos)
13329#define COMP_CSR_BRGEN COMP_CSR_BRGEN_Msk
13330#define COMP_CSR_SCALEN_Pos (23U)
13331#define COMP_CSR_SCALEN_Msk (0x1UL << COMP_CSR_SCALEN_Pos)
13332#define COMP_CSR_SCALEN COMP_CSR_SCALEN_Msk
13334#define COMP_CSR_INMESEL_Pos (25U)
13335#define COMP_CSR_INMESEL_Msk (0x3UL << COMP_CSR_INMESEL_Pos)
13336#define COMP_CSR_INMESEL COMP_CSR_INMESEL_Msk
13337#define COMP_CSR_INMESEL_0 (0x1UL << COMP_CSR_INMESEL_Pos)
13338#define COMP_CSR_INMESEL_1 (0x2UL << COMP_CSR_INMESEL_Pos)
13340#define COMP_CSR_VALUE_Pos (30U)
13341#define COMP_CSR_VALUE_Msk (0x1UL << COMP_CSR_VALUE_Pos)
13342#define COMP_CSR_VALUE COMP_CSR_VALUE_Msk
13344#define COMP_CSR_LOCK_Pos (31U)
13345#define COMP_CSR_LOCK_Msk (0x1UL << COMP_CSR_LOCK_Pos)
13346#define COMP_CSR_LOCK COMP_CSR_LOCK_Msk
13348/******************************************************************************/
13349/* */
13350/* Operational Amplifier (OPAMP) */
13351/* */
13352/******************************************************************************/
13353/********************* Bit definition for OPAMPx_CSR register ***************/
13354#define OPAMP_CSR_OPAMPxEN_Pos (0U)
13355#define OPAMP_CSR_OPAMPxEN_Msk (0x1UL << OPAMP_CSR_OPAMPxEN_Pos)
13356#define OPAMP_CSR_OPAMPxEN OPAMP_CSR_OPAMPxEN_Msk
13357#define OPAMP_CSR_OPALPM_Pos (1U)
13358#define OPAMP_CSR_OPALPM_Msk (0x1UL << OPAMP_CSR_OPALPM_Pos)
13359#define OPAMP_CSR_OPALPM OPAMP_CSR_OPALPM_Msk
13361#define OPAMP_CSR_OPAMODE_Pos (2U)
13362#define OPAMP_CSR_OPAMODE_Msk (0x3UL << OPAMP_CSR_OPAMODE_Pos)
13363#define OPAMP_CSR_OPAMODE OPAMP_CSR_OPAMODE_Msk
13364#define OPAMP_CSR_OPAMODE_0 (0x1UL << OPAMP_CSR_OPAMODE_Pos)
13365#define OPAMP_CSR_OPAMODE_1 (0x2UL << OPAMP_CSR_OPAMODE_Pos)
13367#define OPAMP_CSR_PGGAIN_Pos (4U)
13368#define OPAMP_CSR_PGGAIN_Msk (0x3UL << OPAMP_CSR_PGGAIN_Pos)
13369#define OPAMP_CSR_PGGAIN OPAMP_CSR_PGGAIN_Msk
13370#define OPAMP_CSR_PGGAIN_0 (0x1UL << OPAMP_CSR_PGGAIN_Pos)
13371#define OPAMP_CSR_PGGAIN_1 (0x2UL << OPAMP_CSR_PGGAIN_Pos)
13373#define OPAMP_CSR_VMSEL_Pos (8U)
13374#define OPAMP_CSR_VMSEL_Msk (0x3UL << OPAMP_CSR_VMSEL_Pos)
13375#define OPAMP_CSR_VMSEL OPAMP_CSR_VMSEL_Msk
13376#define OPAMP_CSR_VMSEL_0 (0x1UL << OPAMP_CSR_VMSEL_Pos)
13377#define OPAMP_CSR_VMSEL_1 (0x2UL << OPAMP_CSR_VMSEL_Pos)
13379#define OPAMP_CSR_VPSEL_Pos (10U)
13380#define OPAMP_CSR_VPSEL_Msk (0x1UL << OPAMP_CSR_VPSEL_Pos)
13381#define OPAMP_CSR_VPSEL OPAMP_CSR_VPSEL_Msk
13382#define OPAMP_CSR_CALON_Pos (12U)
13383#define OPAMP_CSR_CALON_Msk (0x1UL << OPAMP_CSR_CALON_Pos)
13384#define OPAMP_CSR_CALON OPAMP_CSR_CALON_Msk
13385#define OPAMP_CSR_CALSEL_Pos (13U)
13386#define OPAMP_CSR_CALSEL_Msk (0x1UL << OPAMP_CSR_CALSEL_Pos)
13387#define OPAMP_CSR_CALSEL OPAMP_CSR_CALSEL_Msk
13388#define OPAMP_CSR_USERTRIM_Pos (14U)
13389#define OPAMP_CSR_USERTRIM_Msk (0x1UL << OPAMP_CSR_USERTRIM_Pos)
13390#define OPAMP_CSR_USERTRIM OPAMP_CSR_USERTRIM_Msk
13391#define OPAMP_CSR_CALOUT_Pos (15U)
13392#define OPAMP_CSR_CALOUT_Msk (0x1UL << OPAMP_CSR_CALOUT_Pos)
13393#define OPAMP_CSR_CALOUT OPAMP_CSR_CALOUT_Msk
13395/********************* Bit definition for OPAMP1_CSR register ***************/
13396#define OPAMP1_CSR_OPAEN_Pos (0U)
13397#define OPAMP1_CSR_OPAEN_Msk (0x1UL << OPAMP1_CSR_OPAEN_Pos)
13398#define OPAMP1_CSR_OPAEN OPAMP1_CSR_OPAEN_Msk
13399#define OPAMP1_CSR_OPALPM_Pos (1U)
13400#define OPAMP1_CSR_OPALPM_Msk (0x1UL << OPAMP1_CSR_OPALPM_Pos)
13401#define OPAMP1_CSR_OPALPM OPAMP1_CSR_OPALPM_Msk
13403#define OPAMP1_CSR_OPAMODE_Pos (2U)
13404#define OPAMP1_CSR_OPAMODE_Msk (0x3UL << OPAMP1_CSR_OPAMODE_Pos)
13405#define OPAMP1_CSR_OPAMODE OPAMP1_CSR_OPAMODE_Msk
13406#define OPAMP1_CSR_OPAMODE_0 (0x1UL << OPAMP1_CSR_OPAMODE_Pos)
13407#define OPAMP1_CSR_OPAMODE_1 (0x2UL << OPAMP1_CSR_OPAMODE_Pos)
13409#define OPAMP1_CSR_PGAGAIN_Pos (4U)
13410#define OPAMP1_CSR_PGAGAIN_Msk (0x3UL << OPAMP1_CSR_PGAGAIN_Pos)
13411#define OPAMP1_CSR_PGAGAIN OPAMP1_CSR_PGAGAIN_Msk
13412#define OPAMP1_CSR_PGAGAIN_0 (0x1UL << OPAMP1_CSR_PGAGAIN_Pos)
13413#define OPAMP1_CSR_PGAGAIN_1 (0x2UL << OPAMP1_CSR_PGAGAIN_Pos)
13415#define OPAMP1_CSR_VMSEL_Pos (8U)
13416#define OPAMP1_CSR_VMSEL_Msk (0x3UL << OPAMP1_CSR_VMSEL_Pos)
13417#define OPAMP1_CSR_VMSEL OPAMP1_CSR_VMSEL_Msk
13418#define OPAMP1_CSR_VMSEL_0 (0x1UL << OPAMP1_CSR_VMSEL_Pos)
13419#define OPAMP1_CSR_VMSEL_1 (0x2UL << OPAMP1_CSR_VMSEL_Pos)
13421#define OPAMP1_CSR_VPSEL_Pos (10U)
13422#define OPAMP1_CSR_VPSEL_Msk (0x1UL << OPAMP1_CSR_VPSEL_Pos)
13423#define OPAMP1_CSR_VPSEL OPAMP1_CSR_VPSEL_Msk
13424#define OPAMP1_CSR_CALON_Pos (12U)
13425#define OPAMP1_CSR_CALON_Msk (0x1UL << OPAMP1_CSR_CALON_Pos)
13426#define OPAMP1_CSR_CALON OPAMP1_CSR_CALON_Msk
13427#define OPAMP1_CSR_CALSEL_Pos (13U)
13428#define OPAMP1_CSR_CALSEL_Msk (0x1UL << OPAMP1_CSR_CALSEL_Pos)
13429#define OPAMP1_CSR_CALSEL OPAMP1_CSR_CALSEL_Msk
13430#define OPAMP1_CSR_USERTRIM_Pos (14U)
13431#define OPAMP1_CSR_USERTRIM_Msk (0x1UL << OPAMP1_CSR_USERTRIM_Pos)
13432#define OPAMP1_CSR_USERTRIM OPAMP1_CSR_USERTRIM_Msk
13433#define OPAMP1_CSR_CALOUT_Pos (15U)
13434#define OPAMP1_CSR_CALOUT_Msk (0x1UL << OPAMP1_CSR_CALOUT_Pos)
13435#define OPAMP1_CSR_CALOUT OPAMP1_CSR_CALOUT_Msk
13437#define OPAMP1_CSR_OPARANGE_Pos (31U)
13438#define OPAMP1_CSR_OPARANGE_Msk (0x1UL << OPAMP1_CSR_OPARANGE_Pos)
13439#define OPAMP1_CSR_OPARANGE OPAMP1_CSR_OPARANGE_Msk
13441/******************* Bit definition for OPAMP_OTR register ******************/
13442#define OPAMP_OTR_TRIMOFFSETN_Pos (0U)
13443#define OPAMP_OTR_TRIMOFFSETN_Msk (0x1FUL << OPAMP_OTR_TRIMOFFSETN_Pos)
13444#define OPAMP_OTR_TRIMOFFSETN OPAMP_OTR_TRIMOFFSETN_Msk
13445#define OPAMP_OTR_TRIMOFFSETP_Pos (8U)
13446#define OPAMP_OTR_TRIMOFFSETP_Msk (0x1FUL << OPAMP_OTR_TRIMOFFSETP_Pos)
13447#define OPAMP_OTR_TRIMOFFSETP OPAMP_OTR_TRIMOFFSETP_Msk
13449/******************* Bit definition for OPAMP1_OTR register ******************/
13450#define OPAMP1_OTR_TRIMOFFSETN_Pos (0U)
13451#define OPAMP1_OTR_TRIMOFFSETN_Msk (0x1FUL << OPAMP1_OTR_TRIMOFFSETN_Pos)
13452#define OPAMP1_OTR_TRIMOFFSETN OPAMP1_OTR_TRIMOFFSETN_Msk
13453#define OPAMP1_OTR_TRIMOFFSETP_Pos (8U)
13454#define OPAMP1_OTR_TRIMOFFSETP_Msk (0x1FUL << OPAMP1_OTR_TRIMOFFSETP_Pos)
13455#define OPAMP1_OTR_TRIMOFFSETP OPAMP1_OTR_TRIMOFFSETP_Msk
13457/******************* Bit definition for OPAMP_LPOTR register ****************/
13458#define OPAMP_LPOTR_TRIMLPOFFSETN_Pos (0U)
13459#define OPAMP_LPOTR_TRIMLPOFFSETN_Msk (0x1FUL << OPAMP_LPOTR_TRIMLPOFFSETN_Pos)
13460#define OPAMP_LPOTR_TRIMLPOFFSETN OPAMP_LPOTR_TRIMLPOFFSETN_Msk
13461#define OPAMP_LPOTR_TRIMLPOFFSETP_Pos (8U)
13462#define OPAMP_LPOTR_TRIMLPOFFSETP_Msk (0x1FUL << OPAMP_LPOTR_TRIMLPOFFSETP_Pos)
13463#define OPAMP_LPOTR_TRIMLPOFFSETP OPAMP_LPOTR_TRIMLPOFFSETP_Msk
13465/******************* Bit definition for OPAMP1_LPOTR register ****************/
13466#define OPAMP1_LPOTR_TRIMLPOFFSETN_Pos (0U)
13467#define OPAMP1_LPOTR_TRIMLPOFFSETN_Msk (0x1FUL << OPAMP1_LPOTR_TRIMLPOFFSETN_Pos)
13468#define OPAMP1_LPOTR_TRIMLPOFFSETN OPAMP1_LPOTR_TRIMLPOFFSETN_Msk
13469#define OPAMP1_LPOTR_TRIMLPOFFSETP_Pos (8U)
13470#define OPAMP1_LPOTR_TRIMLPOFFSETP_Msk (0x1FUL << OPAMP1_LPOTR_TRIMLPOFFSETP_Pos)
13471#define OPAMP1_LPOTR_TRIMLPOFFSETP OPAMP1_LPOTR_TRIMLPOFFSETP_Msk
13473/******************************************************************************/
13474/* */
13475/* Touch Sensing Controller (TSC) */
13476/* */
13477/******************************************************************************/
13478/******************* Bit definition for TSC_CR register *********************/
13479#define TSC_CR_TSCE_Pos (0U)
13480#define TSC_CR_TSCE_Msk (0x1UL << TSC_CR_TSCE_Pos)
13481#define TSC_CR_TSCE TSC_CR_TSCE_Msk
13482#define TSC_CR_START_Pos (1U)
13483#define TSC_CR_START_Msk (0x1UL << TSC_CR_START_Pos)
13484#define TSC_CR_START TSC_CR_START_Msk
13485#define TSC_CR_AM_Pos (2U)
13486#define TSC_CR_AM_Msk (0x1UL << TSC_CR_AM_Pos)
13487#define TSC_CR_AM TSC_CR_AM_Msk
13488#define TSC_CR_SYNCPOL_Pos (3U)
13489#define TSC_CR_SYNCPOL_Msk (0x1UL << TSC_CR_SYNCPOL_Pos)
13490#define TSC_CR_SYNCPOL TSC_CR_SYNCPOL_Msk
13491#define TSC_CR_IODEF_Pos (4U)
13492#define TSC_CR_IODEF_Msk (0x1UL << TSC_CR_IODEF_Pos)
13493#define TSC_CR_IODEF TSC_CR_IODEF_Msk
13495#define TSC_CR_MCV_Pos (5U)
13496#define TSC_CR_MCV_Msk (0x7UL << TSC_CR_MCV_Pos)
13497#define TSC_CR_MCV TSC_CR_MCV_Msk
13498#define TSC_CR_MCV_0 (0x1UL << TSC_CR_MCV_Pos)
13499#define TSC_CR_MCV_1 (0x2UL << TSC_CR_MCV_Pos)
13500#define TSC_CR_MCV_2 (0x4UL << TSC_CR_MCV_Pos)
13502#define TSC_CR_PGPSC_Pos (12U)
13503#define TSC_CR_PGPSC_Msk (0x7UL << TSC_CR_PGPSC_Pos)
13504#define TSC_CR_PGPSC TSC_CR_PGPSC_Msk
13505#define TSC_CR_PGPSC_0 (0x1UL << TSC_CR_PGPSC_Pos)
13506#define TSC_CR_PGPSC_1 (0x2UL << TSC_CR_PGPSC_Pos)
13507#define TSC_CR_PGPSC_2 (0x4UL << TSC_CR_PGPSC_Pos)
13509#define TSC_CR_SSPSC_Pos (15U)
13510#define TSC_CR_SSPSC_Msk (0x1UL << TSC_CR_SSPSC_Pos)
13511#define TSC_CR_SSPSC TSC_CR_SSPSC_Msk
13512#define TSC_CR_SSE_Pos (16U)
13513#define TSC_CR_SSE_Msk (0x1UL << TSC_CR_SSE_Pos)
13514#define TSC_CR_SSE TSC_CR_SSE_Msk
13516#define TSC_CR_SSD_Pos (17U)
13517#define TSC_CR_SSD_Msk (0x7FUL << TSC_CR_SSD_Pos)
13518#define TSC_CR_SSD TSC_CR_SSD_Msk
13519#define TSC_CR_SSD_0 (0x01UL << TSC_CR_SSD_Pos)
13520#define TSC_CR_SSD_1 (0x02UL << TSC_CR_SSD_Pos)
13521#define TSC_CR_SSD_2 (0x04UL << TSC_CR_SSD_Pos)
13522#define TSC_CR_SSD_3 (0x08UL << TSC_CR_SSD_Pos)
13523#define TSC_CR_SSD_4 (0x10UL << TSC_CR_SSD_Pos)
13524#define TSC_CR_SSD_5 (0x20UL << TSC_CR_SSD_Pos)
13525#define TSC_CR_SSD_6 (0x40UL << TSC_CR_SSD_Pos)
13527#define TSC_CR_CTPL_Pos (24U)
13528#define TSC_CR_CTPL_Msk (0xFUL << TSC_CR_CTPL_Pos)
13529#define TSC_CR_CTPL TSC_CR_CTPL_Msk
13530#define TSC_CR_CTPL_0 (0x1UL << TSC_CR_CTPL_Pos)
13531#define TSC_CR_CTPL_1 (0x2UL << TSC_CR_CTPL_Pos)
13532#define TSC_CR_CTPL_2 (0x4UL << TSC_CR_CTPL_Pos)
13533#define TSC_CR_CTPL_3 (0x8UL << TSC_CR_CTPL_Pos)
13535#define TSC_CR_CTPH_Pos (28U)
13536#define TSC_CR_CTPH_Msk (0xFUL << TSC_CR_CTPH_Pos)
13537#define TSC_CR_CTPH TSC_CR_CTPH_Msk
13538#define TSC_CR_CTPH_0 (0x1UL << TSC_CR_CTPH_Pos)
13539#define TSC_CR_CTPH_1 (0x2UL << TSC_CR_CTPH_Pos)
13540#define TSC_CR_CTPH_2 (0x4UL << TSC_CR_CTPH_Pos)
13541#define TSC_CR_CTPH_3 (0x8UL << TSC_CR_CTPH_Pos)
13543/******************* Bit definition for TSC_IER register ********************/
13544#define TSC_IER_EOAIE_Pos (0U)
13545#define TSC_IER_EOAIE_Msk (0x1UL << TSC_IER_EOAIE_Pos)
13546#define TSC_IER_EOAIE TSC_IER_EOAIE_Msk
13547#define TSC_IER_MCEIE_Pos (1U)
13548#define TSC_IER_MCEIE_Msk (0x1UL << TSC_IER_MCEIE_Pos)
13549#define TSC_IER_MCEIE TSC_IER_MCEIE_Msk
13551/******************* Bit definition for TSC_ICR register ********************/
13552#define TSC_ICR_EOAIC_Pos (0U)
13553#define TSC_ICR_EOAIC_Msk (0x1UL << TSC_ICR_EOAIC_Pos)
13554#define TSC_ICR_EOAIC TSC_ICR_EOAIC_Msk
13555#define TSC_ICR_MCEIC_Pos (1U)
13556#define TSC_ICR_MCEIC_Msk (0x1UL << TSC_ICR_MCEIC_Pos)
13557#define TSC_ICR_MCEIC TSC_ICR_MCEIC_Msk
13559/******************* Bit definition for TSC_ISR register ********************/
13560#define TSC_ISR_EOAF_Pos (0U)
13561#define TSC_ISR_EOAF_Msk (0x1UL << TSC_ISR_EOAF_Pos)
13562#define TSC_ISR_EOAF TSC_ISR_EOAF_Msk
13563#define TSC_ISR_MCEF_Pos (1U)
13564#define TSC_ISR_MCEF_Msk (0x1UL << TSC_ISR_MCEF_Pos)
13565#define TSC_ISR_MCEF TSC_ISR_MCEF_Msk
13567/******************* Bit definition for TSC_IOHCR register ******************/
13568#define TSC_IOHCR_G1_IO1_Pos (0U)
13569#define TSC_IOHCR_G1_IO1_Msk (0x1UL << TSC_IOHCR_G1_IO1_Pos)
13570#define TSC_IOHCR_G1_IO1 TSC_IOHCR_G1_IO1_Msk
13571#define TSC_IOHCR_G1_IO2_Pos (1U)
13572#define TSC_IOHCR_G1_IO2_Msk (0x1UL << TSC_IOHCR_G1_IO2_Pos)
13573#define TSC_IOHCR_G1_IO2 TSC_IOHCR_G1_IO2_Msk
13574#define TSC_IOHCR_G1_IO3_Pos (2U)
13575#define TSC_IOHCR_G1_IO3_Msk (0x1UL << TSC_IOHCR_G1_IO3_Pos)
13576#define TSC_IOHCR_G1_IO3 TSC_IOHCR_G1_IO3_Msk
13577#define TSC_IOHCR_G1_IO4_Pos (3U)
13578#define TSC_IOHCR_G1_IO4_Msk (0x1UL << TSC_IOHCR_G1_IO4_Pos)
13579#define TSC_IOHCR_G1_IO4 TSC_IOHCR_G1_IO4_Msk
13580#define TSC_IOHCR_G2_IO1_Pos (4U)
13581#define TSC_IOHCR_G2_IO1_Msk (0x1UL << TSC_IOHCR_G2_IO1_Pos)
13582#define TSC_IOHCR_G2_IO1 TSC_IOHCR_G2_IO1_Msk
13583#define TSC_IOHCR_G2_IO2_Pos (5U)
13584#define TSC_IOHCR_G2_IO2_Msk (0x1UL << TSC_IOHCR_G2_IO2_Pos)
13585#define TSC_IOHCR_G2_IO2 TSC_IOHCR_G2_IO2_Msk
13586#define TSC_IOHCR_G2_IO3_Pos (6U)
13587#define TSC_IOHCR_G2_IO3_Msk (0x1UL << TSC_IOHCR_G2_IO3_Pos)
13588#define TSC_IOHCR_G2_IO3 TSC_IOHCR_G2_IO3_Msk
13589#define TSC_IOHCR_G2_IO4_Pos (7U)
13590#define TSC_IOHCR_G2_IO4_Msk (0x1UL << TSC_IOHCR_G2_IO4_Pos)
13591#define TSC_IOHCR_G2_IO4 TSC_IOHCR_G2_IO4_Msk
13592#define TSC_IOHCR_G3_IO1_Pos (8U)
13593#define TSC_IOHCR_G3_IO1_Msk (0x1UL << TSC_IOHCR_G3_IO1_Pos)
13594#define TSC_IOHCR_G3_IO1 TSC_IOHCR_G3_IO1_Msk
13595#define TSC_IOHCR_G3_IO2_Pos (9U)
13596#define TSC_IOHCR_G3_IO2_Msk (0x1UL << TSC_IOHCR_G3_IO2_Pos)
13597#define TSC_IOHCR_G3_IO2 TSC_IOHCR_G3_IO2_Msk
13598#define TSC_IOHCR_G3_IO3_Pos (10U)
13599#define TSC_IOHCR_G3_IO3_Msk (0x1UL << TSC_IOHCR_G3_IO3_Pos)
13600#define TSC_IOHCR_G3_IO3 TSC_IOHCR_G3_IO3_Msk
13601#define TSC_IOHCR_G3_IO4_Pos (11U)
13602#define TSC_IOHCR_G3_IO4_Msk (0x1UL << TSC_IOHCR_G3_IO4_Pos)
13603#define TSC_IOHCR_G3_IO4 TSC_IOHCR_G3_IO4_Msk
13604#define TSC_IOHCR_G4_IO1_Pos (12U)
13605#define TSC_IOHCR_G4_IO1_Msk (0x1UL << TSC_IOHCR_G4_IO1_Pos)
13606#define TSC_IOHCR_G4_IO1 TSC_IOHCR_G4_IO1_Msk
13607#define TSC_IOHCR_G4_IO2_Pos (13U)
13608#define TSC_IOHCR_G4_IO2_Msk (0x1UL << TSC_IOHCR_G4_IO2_Pos)
13609#define TSC_IOHCR_G4_IO2 TSC_IOHCR_G4_IO2_Msk
13610#define TSC_IOHCR_G4_IO3_Pos (14U)
13611#define TSC_IOHCR_G4_IO3_Msk (0x1UL << TSC_IOHCR_G4_IO3_Pos)
13612#define TSC_IOHCR_G4_IO3 TSC_IOHCR_G4_IO3_Msk
13613#define TSC_IOHCR_G4_IO4_Pos (15U)
13614#define TSC_IOHCR_G4_IO4_Msk (0x1UL << TSC_IOHCR_G4_IO4_Pos)
13615#define TSC_IOHCR_G4_IO4 TSC_IOHCR_G4_IO4_Msk
13616#define TSC_IOHCR_G5_IO1_Pos (16U)
13617#define TSC_IOHCR_G5_IO1_Msk (0x1UL << TSC_IOHCR_G5_IO1_Pos)
13618#define TSC_IOHCR_G5_IO1 TSC_IOHCR_G5_IO1_Msk
13619#define TSC_IOHCR_G5_IO2_Pos (17U)
13620#define TSC_IOHCR_G5_IO2_Msk (0x1UL << TSC_IOHCR_G5_IO2_Pos)
13621#define TSC_IOHCR_G5_IO2 TSC_IOHCR_G5_IO2_Msk
13622#define TSC_IOHCR_G5_IO3_Pos (18U)
13623#define TSC_IOHCR_G5_IO3_Msk (0x1UL << TSC_IOHCR_G5_IO3_Pos)
13624#define TSC_IOHCR_G5_IO3 TSC_IOHCR_G5_IO3_Msk
13625#define TSC_IOHCR_G5_IO4_Pos (19U)
13626#define TSC_IOHCR_G5_IO4_Msk (0x1UL << TSC_IOHCR_G5_IO4_Pos)
13627#define TSC_IOHCR_G5_IO4 TSC_IOHCR_G5_IO4_Msk
13628#define TSC_IOHCR_G6_IO1_Pos (20U)
13629#define TSC_IOHCR_G6_IO1_Msk (0x1UL << TSC_IOHCR_G6_IO1_Pos)
13630#define TSC_IOHCR_G6_IO1 TSC_IOHCR_G6_IO1_Msk
13631#define TSC_IOHCR_G6_IO2_Pos (21U)
13632#define TSC_IOHCR_G6_IO2_Msk (0x1UL << TSC_IOHCR_G6_IO2_Pos)
13633#define TSC_IOHCR_G6_IO2 TSC_IOHCR_G6_IO2_Msk
13634#define TSC_IOHCR_G6_IO3_Pos (22U)
13635#define TSC_IOHCR_G6_IO3_Msk (0x1UL << TSC_IOHCR_G6_IO3_Pos)
13636#define TSC_IOHCR_G6_IO3 TSC_IOHCR_G6_IO3_Msk
13637#define TSC_IOHCR_G6_IO4_Pos (23U)
13638#define TSC_IOHCR_G6_IO4_Msk (0x1UL << TSC_IOHCR_G6_IO4_Pos)
13639#define TSC_IOHCR_G6_IO4 TSC_IOHCR_G6_IO4_Msk
13640#define TSC_IOHCR_G7_IO1_Pos (24U)
13641#define TSC_IOHCR_G7_IO1_Msk (0x1UL << TSC_IOHCR_G7_IO1_Pos)
13642#define TSC_IOHCR_G7_IO1 TSC_IOHCR_G7_IO1_Msk
13643#define TSC_IOHCR_G7_IO2_Pos (25U)
13644#define TSC_IOHCR_G7_IO2_Msk (0x1UL << TSC_IOHCR_G7_IO2_Pos)
13645#define TSC_IOHCR_G7_IO2 TSC_IOHCR_G7_IO2_Msk
13646#define TSC_IOHCR_G7_IO3_Pos (26U)
13647#define TSC_IOHCR_G7_IO3_Msk (0x1UL << TSC_IOHCR_G7_IO3_Pos)
13648#define TSC_IOHCR_G7_IO3 TSC_IOHCR_G7_IO3_Msk
13649#define TSC_IOHCR_G7_IO4_Pos (27U)
13650#define TSC_IOHCR_G7_IO4_Msk (0x1UL << TSC_IOHCR_G7_IO4_Pos)
13651#define TSC_IOHCR_G7_IO4 TSC_IOHCR_G7_IO4_Msk
13653/******************* Bit definition for TSC_IOASCR register *****************/
13654#define TSC_IOASCR_G1_IO1_Pos (0U)
13655#define TSC_IOASCR_G1_IO1_Msk (0x1UL << TSC_IOASCR_G1_IO1_Pos)
13656#define TSC_IOASCR_G1_IO1 TSC_IOASCR_G1_IO1_Msk
13657#define TSC_IOASCR_G1_IO2_Pos (1U)
13658#define TSC_IOASCR_G1_IO2_Msk (0x1UL << TSC_IOASCR_G1_IO2_Pos)
13659#define TSC_IOASCR_G1_IO2 TSC_IOASCR_G1_IO2_Msk
13660#define TSC_IOASCR_G1_IO3_Pos (2U)
13661#define TSC_IOASCR_G1_IO3_Msk (0x1UL << TSC_IOASCR_G1_IO3_Pos)
13662#define TSC_IOASCR_G1_IO3 TSC_IOASCR_G1_IO3_Msk
13663#define TSC_IOASCR_G1_IO4_Pos (3U)
13664#define TSC_IOASCR_G1_IO4_Msk (0x1UL << TSC_IOASCR_G1_IO4_Pos)
13665#define TSC_IOASCR_G1_IO4 TSC_IOASCR_G1_IO4_Msk
13666#define TSC_IOASCR_G2_IO1_Pos (4U)
13667#define TSC_IOASCR_G2_IO1_Msk (0x1UL << TSC_IOASCR_G2_IO1_Pos)
13668#define TSC_IOASCR_G2_IO1 TSC_IOASCR_G2_IO1_Msk
13669#define TSC_IOASCR_G2_IO2_Pos (5U)
13670#define TSC_IOASCR_G2_IO2_Msk (0x1UL << TSC_IOASCR_G2_IO2_Pos)
13671#define TSC_IOASCR_G2_IO2 TSC_IOASCR_G2_IO2_Msk
13672#define TSC_IOASCR_G2_IO3_Pos (6U)
13673#define TSC_IOASCR_G2_IO3_Msk (0x1UL << TSC_IOASCR_G2_IO3_Pos)
13674#define TSC_IOASCR_G2_IO3 TSC_IOASCR_G2_IO3_Msk
13675#define TSC_IOASCR_G2_IO4_Pos (7U)
13676#define TSC_IOASCR_G2_IO4_Msk (0x1UL << TSC_IOASCR_G2_IO4_Pos)
13677#define TSC_IOASCR_G2_IO4 TSC_IOASCR_G2_IO4_Msk
13678#define TSC_IOASCR_G3_IO1_Pos (8U)
13679#define TSC_IOASCR_G3_IO1_Msk (0x1UL << TSC_IOASCR_G3_IO1_Pos)
13680#define TSC_IOASCR_G3_IO1 TSC_IOASCR_G3_IO1_Msk
13681#define TSC_IOASCR_G3_IO2_Pos (9U)
13682#define TSC_IOASCR_G3_IO2_Msk (0x1UL << TSC_IOASCR_G3_IO2_Pos)
13683#define TSC_IOASCR_G3_IO2 TSC_IOASCR_G3_IO2_Msk
13684#define TSC_IOASCR_G3_IO3_Pos (10U)
13685#define TSC_IOASCR_G3_IO3_Msk (0x1UL << TSC_IOASCR_G3_IO3_Pos)
13686#define TSC_IOASCR_G3_IO3 TSC_IOASCR_G3_IO3_Msk
13687#define TSC_IOASCR_G3_IO4_Pos (11U)
13688#define TSC_IOASCR_G3_IO4_Msk (0x1UL << TSC_IOASCR_G3_IO4_Pos)
13689#define TSC_IOASCR_G3_IO4 TSC_IOASCR_G3_IO4_Msk
13690#define TSC_IOASCR_G4_IO1_Pos (12U)
13691#define TSC_IOASCR_G4_IO1_Msk (0x1UL << TSC_IOASCR_G4_IO1_Pos)
13692#define TSC_IOASCR_G4_IO1 TSC_IOASCR_G4_IO1_Msk
13693#define TSC_IOASCR_G4_IO2_Pos (13U)
13694#define TSC_IOASCR_G4_IO2_Msk (0x1UL << TSC_IOASCR_G4_IO2_Pos)
13695#define TSC_IOASCR_G4_IO2 TSC_IOASCR_G4_IO2_Msk
13696#define TSC_IOASCR_G4_IO3_Pos (14U)
13697#define TSC_IOASCR_G4_IO3_Msk (0x1UL << TSC_IOASCR_G4_IO3_Pos)
13698#define TSC_IOASCR_G4_IO3 TSC_IOASCR_G4_IO3_Msk
13699#define TSC_IOASCR_G4_IO4_Pos (15U)
13700#define TSC_IOASCR_G4_IO4_Msk (0x1UL << TSC_IOASCR_G4_IO4_Pos)
13701#define TSC_IOASCR_G4_IO4 TSC_IOASCR_G4_IO4_Msk
13702#define TSC_IOASCR_G5_IO1_Pos (16U)
13703#define TSC_IOASCR_G5_IO1_Msk (0x1UL << TSC_IOASCR_G5_IO1_Pos)
13704#define TSC_IOASCR_G5_IO1 TSC_IOASCR_G5_IO1_Msk
13705#define TSC_IOASCR_G5_IO2_Pos (17U)
13706#define TSC_IOASCR_G5_IO2_Msk (0x1UL << TSC_IOASCR_G5_IO2_Pos)
13707#define TSC_IOASCR_G5_IO2 TSC_IOASCR_G5_IO2_Msk
13708#define TSC_IOASCR_G5_IO3_Pos (18U)
13709#define TSC_IOASCR_G5_IO3_Msk (0x1UL << TSC_IOASCR_G5_IO3_Pos)
13710#define TSC_IOASCR_G5_IO3 TSC_IOASCR_G5_IO3_Msk
13711#define TSC_IOASCR_G5_IO4_Pos (19U)
13712#define TSC_IOASCR_G5_IO4_Msk (0x1UL << TSC_IOASCR_G5_IO4_Pos)
13713#define TSC_IOASCR_G5_IO4 TSC_IOASCR_G5_IO4_Msk
13714#define TSC_IOASCR_G6_IO1_Pos (20U)
13715#define TSC_IOASCR_G6_IO1_Msk (0x1UL << TSC_IOASCR_G6_IO1_Pos)
13716#define TSC_IOASCR_G6_IO1 TSC_IOASCR_G6_IO1_Msk
13717#define TSC_IOASCR_G6_IO2_Pos (21U)
13718#define TSC_IOASCR_G6_IO2_Msk (0x1UL << TSC_IOASCR_G6_IO2_Pos)
13719#define TSC_IOASCR_G6_IO2 TSC_IOASCR_G6_IO2_Msk
13720#define TSC_IOASCR_G6_IO3_Pos (22U)
13721#define TSC_IOASCR_G6_IO3_Msk (0x1UL << TSC_IOASCR_G6_IO3_Pos)
13722#define TSC_IOASCR_G6_IO3 TSC_IOASCR_G6_IO3_Msk
13723#define TSC_IOASCR_G6_IO4_Pos (23U)
13724#define TSC_IOASCR_G6_IO4_Msk (0x1UL << TSC_IOASCR_G6_IO4_Pos)
13725#define TSC_IOASCR_G6_IO4 TSC_IOASCR_G6_IO4_Msk
13726#define TSC_IOASCR_G7_IO1_Pos (24U)
13727#define TSC_IOASCR_G7_IO1_Msk (0x1UL << TSC_IOASCR_G7_IO1_Pos)
13728#define TSC_IOASCR_G7_IO1 TSC_IOASCR_G7_IO1_Msk
13729#define TSC_IOASCR_G7_IO2_Pos (25U)
13730#define TSC_IOASCR_G7_IO2_Msk (0x1UL << TSC_IOASCR_G7_IO2_Pos)
13731#define TSC_IOASCR_G7_IO2 TSC_IOASCR_G7_IO2_Msk
13732#define TSC_IOASCR_G7_IO3_Pos (26U)
13733#define TSC_IOASCR_G7_IO3_Msk (0x1UL << TSC_IOASCR_G7_IO3_Pos)
13734#define TSC_IOASCR_G7_IO3 TSC_IOASCR_G7_IO3_Msk
13735#define TSC_IOASCR_G7_IO4_Pos (27U)
13736#define TSC_IOASCR_G7_IO4_Msk (0x1UL << TSC_IOASCR_G7_IO4_Pos)
13737#define TSC_IOASCR_G7_IO4 TSC_IOASCR_G7_IO4_Msk
13739/******************* Bit definition for TSC_IOSCR register ******************/
13740#define TSC_IOSCR_G1_IO1_Pos (0U)
13741#define TSC_IOSCR_G1_IO1_Msk (0x1UL << TSC_IOSCR_G1_IO1_Pos)
13742#define TSC_IOSCR_G1_IO1 TSC_IOSCR_G1_IO1_Msk
13743#define TSC_IOSCR_G1_IO2_Pos (1U)
13744#define TSC_IOSCR_G1_IO2_Msk (0x1UL << TSC_IOSCR_G1_IO2_Pos)
13745#define TSC_IOSCR_G1_IO2 TSC_IOSCR_G1_IO2_Msk
13746#define TSC_IOSCR_G1_IO3_Pos (2U)
13747#define TSC_IOSCR_G1_IO3_Msk (0x1UL << TSC_IOSCR_G1_IO3_Pos)
13748#define TSC_IOSCR_G1_IO3 TSC_IOSCR_G1_IO3_Msk
13749#define TSC_IOSCR_G1_IO4_Pos (3U)
13750#define TSC_IOSCR_G1_IO4_Msk (0x1UL << TSC_IOSCR_G1_IO4_Pos)
13751#define TSC_IOSCR_G1_IO4 TSC_IOSCR_G1_IO4_Msk
13752#define TSC_IOSCR_G2_IO1_Pos (4U)
13753#define TSC_IOSCR_G2_IO1_Msk (0x1UL << TSC_IOSCR_G2_IO1_Pos)
13754#define TSC_IOSCR_G2_IO1 TSC_IOSCR_G2_IO1_Msk
13755#define TSC_IOSCR_G2_IO2_Pos (5U)
13756#define TSC_IOSCR_G2_IO2_Msk (0x1UL << TSC_IOSCR_G2_IO2_Pos)
13757#define TSC_IOSCR_G2_IO2 TSC_IOSCR_G2_IO2_Msk
13758#define TSC_IOSCR_G2_IO3_Pos (6U)
13759#define TSC_IOSCR_G2_IO3_Msk (0x1UL << TSC_IOSCR_G2_IO3_Pos)
13760#define TSC_IOSCR_G2_IO3 TSC_IOSCR_G2_IO3_Msk
13761#define TSC_IOSCR_G2_IO4_Pos (7U)
13762#define TSC_IOSCR_G2_IO4_Msk (0x1UL << TSC_IOSCR_G2_IO4_Pos)
13763#define TSC_IOSCR_G2_IO4 TSC_IOSCR_G2_IO4_Msk
13764#define TSC_IOSCR_G3_IO1_Pos (8U)
13765#define TSC_IOSCR_G3_IO1_Msk (0x1UL << TSC_IOSCR_G3_IO1_Pos)
13766#define TSC_IOSCR_G3_IO1 TSC_IOSCR_G3_IO1_Msk
13767#define TSC_IOSCR_G3_IO2_Pos (9U)
13768#define TSC_IOSCR_G3_IO2_Msk (0x1UL << TSC_IOSCR_G3_IO2_Pos)
13769#define TSC_IOSCR_G3_IO2 TSC_IOSCR_G3_IO2_Msk
13770#define TSC_IOSCR_G3_IO3_Pos (10U)
13771#define TSC_IOSCR_G3_IO3_Msk (0x1UL << TSC_IOSCR_G3_IO3_Pos)
13772#define TSC_IOSCR_G3_IO3 TSC_IOSCR_G3_IO3_Msk
13773#define TSC_IOSCR_G3_IO4_Pos (11U)
13774#define TSC_IOSCR_G3_IO4_Msk (0x1UL << TSC_IOSCR_G3_IO4_Pos)
13775#define TSC_IOSCR_G3_IO4 TSC_IOSCR_G3_IO4_Msk
13776#define TSC_IOSCR_G4_IO1_Pos (12U)
13777#define TSC_IOSCR_G4_IO1_Msk (0x1UL << TSC_IOSCR_G4_IO1_Pos)
13778#define TSC_IOSCR_G4_IO1 TSC_IOSCR_G4_IO1_Msk
13779#define TSC_IOSCR_G4_IO2_Pos (13U)
13780#define TSC_IOSCR_G4_IO2_Msk (0x1UL << TSC_IOSCR_G4_IO2_Pos)
13781#define TSC_IOSCR_G4_IO2 TSC_IOSCR_G4_IO2_Msk
13782#define TSC_IOSCR_G4_IO3_Pos (14U)
13783#define TSC_IOSCR_G4_IO3_Msk (0x1UL << TSC_IOSCR_G4_IO3_Pos)
13784#define TSC_IOSCR_G4_IO3 TSC_IOSCR_G4_IO3_Msk
13785#define TSC_IOSCR_G4_IO4_Pos (15U)
13786#define TSC_IOSCR_G4_IO4_Msk (0x1UL << TSC_IOSCR_G4_IO4_Pos)
13787#define TSC_IOSCR_G4_IO4 TSC_IOSCR_G4_IO4_Msk
13788#define TSC_IOSCR_G5_IO1_Pos (16U)
13789#define TSC_IOSCR_G5_IO1_Msk (0x1UL << TSC_IOSCR_G5_IO1_Pos)
13790#define TSC_IOSCR_G5_IO1 TSC_IOSCR_G5_IO1_Msk
13791#define TSC_IOSCR_G5_IO2_Pos (17U)
13792#define TSC_IOSCR_G5_IO2_Msk (0x1UL << TSC_IOSCR_G5_IO2_Pos)
13793#define TSC_IOSCR_G5_IO2 TSC_IOSCR_G5_IO2_Msk
13794#define TSC_IOSCR_G5_IO3_Pos (18U)
13795#define TSC_IOSCR_G5_IO3_Msk (0x1UL << TSC_IOSCR_G5_IO3_Pos)
13796#define TSC_IOSCR_G5_IO3 TSC_IOSCR_G5_IO3_Msk
13797#define TSC_IOSCR_G5_IO4_Pos (19U)
13798#define TSC_IOSCR_G5_IO4_Msk (0x1UL << TSC_IOSCR_G5_IO4_Pos)
13799#define TSC_IOSCR_G5_IO4 TSC_IOSCR_G5_IO4_Msk
13800#define TSC_IOSCR_G6_IO1_Pos (20U)
13801#define TSC_IOSCR_G6_IO1_Msk (0x1UL << TSC_IOSCR_G6_IO1_Pos)
13802#define TSC_IOSCR_G6_IO1 TSC_IOSCR_G6_IO1_Msk
13803#define TSC_IOSCR_G6_IO2_Pos (21U)
13804#define TSC_IOSCR_G6_IO2_Msk (0x1UL << TSC_IOSCR_G6_IO2_Pos)
13805#define TSC_IOSCR_G6_IO2 TSC_IOSCR_G6_IO2_Msk
13806#define TSC_IOSCR_G6_IO3_Pos (22U)
13807#define TSC_IOSCR_G6_IO3_Msk (0x1UL << TSC_IOSCR_G6_IO3_Pos)
13808#define TSC_IOSCR_G6_IO3 TSC_IOSCR_G6_IO3_Msk
13809#define TSC_IOSCR_G6_IO4_Pos (23U)
13810#define TSC_IOSCR_G6_IO4_Msk (0x1UL << TSC_IOSCR_G6_IO4_Pos)
13811#define TSC_IOSCR_G6_IO4 TSC_IOSCR_G6_IO4_Msk
13812#define TSC_IOSCR_G7_IO1_Pos (24U)
13813#define TSC_IOSCR_G7_IO1_Msk (0x1UL << TSC_IOSCR_G7_IO1_Pos)
13814#define TSC_IOSCR_G7_IO1 TSC_IOSCR_G7_IO1_Msk
13815#define TSC_IOSCR_G7_IO2_Pos (25U)
13816#define TSC_IOSCR_G7_IO2_Msk (0x1UL << TSC_IOSCR_G7_IO2_Pos)
13817#define TSC_IOSCR_G7_IO2 TSC_IOSCR_G7_IO2_Msk
13818#define TSC_IOSCR_G7_IO3_Pos (26U)
13819#define TSC_IOSCR_G7_IO3_Msk (0x1UL << TSC_IOSCR_G7_IO3_Pos)
13820#define TSC_IOSCR_G7_IO3 TSC_IOSCR_G7_IO3_Msk
13821#define TSC_IOSCR_G7_IO4_Pos (27U)
13822#define TSC_IOSCR_G7_IO4_Msk (0x1UL << TSC_IOSCR_G7_IO4_Pos)
13823#define TSC_IOSCR_G7_IO4 TSC_IOSCR_G7_IO4_Msk
13825/******************* Bit definition for TSC_IOCCR register ******************/
13826#define TSC_IOCCR_G1_IO1_Pos (0U)
13827#define TSC_IOCCR_G1_IO1_Msk (0x1UL << TSC_IOCCR_G1_IO1_Pos)
13828#define TSC_IOCCR_G1_IO1 TSC_IOCCR_G1_IO1_Msk
13829#define TSC_IOCCR_G1_IO2_Pos (1U)
13830#define TSC_IOCCR_G1_IO2_Msk (0x1UL << TSC_IOCCR_G1_IO2_Pos)
13831#define TSC_IOCCR_G1_IO2 TSC_IOCCR_G1_IO2_Msk
13832#define TSC_IOCCR_G1_IO3_Pos (2U)
13833#define TSC_IOCCR_G1_IO3_Msk (0x1UL << TSC_IOCCR_G1_IO3_Pos)
13834#define TSC_IOCCR_G1_IO3 TSC_IOCCR_G1_IO3_Msk
13835#define TSC_IOCCR_G1_IO4_Pos (3U)
13836#define TSC_IOCCR_G1_IO4_Msk (0x1UL << TSC_IOCCR_G1_IO4_Pos)
13837#define TSC_IOCCR_G1_IO4 TSC_IOCCR_G1_IO4_Msk
13838#define TSC_IOCCR_G2_IO1_Pos (4U)
13839#define TSC_IOCCR_G2_IO1_Msk (0x1UL << TSC_IOCCR_G2_IO1_Pos)
13840#define TSC_IOCCR_G2_IO1 TSC_IOCCR_G2_IO1_Msk
13841#define TSC_IOCCR_G2_IO2_Pos (5U)
13842#define TSC_IOCCR_G2_IO2_Msk (0x1UL << TSC_IOCCR_G2_IO2_Pos)
13843#define TSC_IOCCR_G2_IO2 TSC_IOCCR_G2_IO2_Msk
13844#define TSC_IOCCR_G2_IO3_Pos (6U)
13845#define TSC_IOCCR_G2_IO3_Msk (0x1UL << TSC_IOCCR_G2_IO3_Pos)
13846#define TSC_IOCCR_G2_IO3 TSC_IOCCR_G2_IO3_Msk
13847#define TSC_IOCCR_G2_IO4_Pos (7U)
13848#define TSC_IOCCR_G2_IO4_Msk (0x1UL << TSC_IOCCR_G2_IO4_Pos)
13849#define TSC_IOCCR_G2_IO4 TSC_IOCCR_G2_IO4_Msk
13850#define TSC_IOCCR_G3_IO1_Pos (8U)
13851#define TSC_IOCCR_G3_IO1_Msk (0x1UL << TSC_IOCCR_G3_IO1_Pos)
13852#define TSC_IOCCR_G3_IO1 TSC_IOCCR_G3_IO1_Msk
13853#define TSC_IOCCR_G3_IO2_Pos (9U)
13854#define TSC_IOCCR_G3_IO2_Msk (0x1UL << TSC_IOCCR_G3_IO2_Pos)
13855#define TSC_IOCCR_G3_IO2 TSC_IOCCR_G3_IO2_Msk
13856#define TSC_IOCCR_G3_IO3_Pos (10U)
13857#define TSC_IOCCR_G3_IO3_Msk (0x1UL << TSC_IOCCR_G3_IO3_Pos)
13858#define TSC_IOCCR_G3_IO3 TSC_IOCCR_G3_IO3_Msk
13859#define TSC_IOCCR_G3_IO4_Pos (11U)
13860#define TSC_IOCCR_G3_IO4_Msk (0x1UL << TSC_IOCCR_G3_IO4_Pos)
13861#define TSC_IOCCR_G3_IO4 TSC_IOCCR_G3_IO4_Msk
13862#define TSC_IOCCR_G4_IO1_Pos (12U)
13863#define TSC_IOCCR_G4_IO1_Msk (0x1UL << TSC_IOCCR_G4_IO1_Pos)
13864#define TSC_IOCCR_G4_IO1 TSC_IOCCR_G4_IO1_Msk
13865#define TSC_IOCCR_G4_IO2_Pos (13U)
13866#define TSC_IOCCR_G4_IO2_Msk (0x1UL << TSC_IOCCR_G4_IO2_Pos)
13867#define TSC_IOCCR_G4_IO2 TSC_IOCCR_G4_IO2_Msk
13868#define TSC_IOCCR_G4_IO3_Pos (14U)
13869#define TSC_IOCCR_G4_IO3_Msk (0x1UL << TSC_IOCCR_G4_IO3_Pos)
13870#define TSC_IOCCR_G4_IO3 TSC_IOCCR_G4_IO3_Msk
13871#define TSC_IOCCR_G4_IO4_Pos (15U)
13872#define TSC_IOCCR_G4_IO4_Msk (0x1UL << TSC_IOCCR_G4_IO4_Pos)
13873#define TSC_IOCCR_G4_IO4 TSC_IOCCR_G4_IO4_Msk
13874#define TSC_IOCCR_G5_IO1_Pos (16U)
13875#define TSC_IOCCR_G5_IO1_Msk (0x1UL << TSC_IOCCR_G5_IO1_Pos)
13876#define TSC_IOCCR_G5_IO1 TSC_IOCCR_G5_IO1_Msk
13877#define TSC_IOCCR_G5_IO2_Pos (17U)
13878#define TSC_IOCCR_G5_IO2_Msk (0x1UL << TSC_IOCCR_G5_IO2_Pos)
13879#define TSC_IOCCR_G5_IO2 TSC_IOCCR_G5_IO2_Msk
13880#define TSC_IOCCR_G5_IO3_Pos (18U)
13881#define TSC_IOCCR_G5_IO3_Msk (0x1UL << TSC_IOCCR_G5_IO3_Pos)
13882#define TSC_IOCCR_G5_IO3 TSC_IOCCR_G5_IO3_Msk
13883#define TSC_IOCCR_G5_IO4_Pos (19U)
13884#define TSC_IOCCR_G5_IO4_Msk (0x1UL << TSC_IOCCR_G5_IO4_Pos)
13885#define TSC_IOCCR_G5_IO4 TSC_IOCCR_G5_IO4_Msk
13886#define TSC_IOCCR_G6_IO1_Pos (20U)
13887#define TSC_IOCCR_G6_IO1_Msk (0x1UL << TSC_IOCCR_G6_IO1_Pos)
13888#define TSC_IOCCR_G6_IO1 TSC_IOCCR_G6_IO1_Msk
13889#define TSC_IOCCR_G6_IO2_Pos (21U)
13890#define TSC_IOCCR_G6_IO2_Msk (0x1UL << TSC_IOCCR_G6_IO2_Pos)
13891#define TSC_IOCCR_G6_IO2 TSC_IOCCR_G6_IO2_Msk
13892#define TSC_IOCCR_G6_IO3_Pos (22U)
13893#define TSC_IOCCR_G6_IO3_Msk (0x1UL << TSC_IOCCR_G6_IO3_Pos)
13894#define TSC_IOCCR_G6_IO3 TSC_IOCCR_G6_IO3_Msk
13895#define TSC_IOCCR_G6_IO4_Pos (23U)
13896#define TSC_IOCCR_G6_IO4_Msk (0x1UL << TSC_IOCCR_G6_IO4_Pos)
13897#define TSC_IOCCR_G6_IO4 TSC_IOCCR_G6_IO4_Msk
13898#define TSC_IOCCR_G7_IO1_Pos (24U)
13899#define TSC_IOCCR_G7_IO1_Msk (0x1UL << TSC_IOCCR_G7_IO1_Pos)
13900#define TSC_IOCCR_G7_IO1 TSC_IOCCR_G7_IO1_Msk
13901#define TSC_IOCCR_G7_IO2_Pos (25U)
13902#define TSC_IOCCR_G7_IO2_Msk (0x1UL << TSC_IOCCR_G7_IO2_Pos)
13903#define TSC_IOCCR_G7_IO2 TSC_IOCCR_G7_IO2_Msk
13904#define TSC_IOCCR_G7_IO3_Pos (26U)
13905#define TSC_IOCCR_G7_IO3_Msk (0x1UL << TSC_IOCCR_G7_IO3_Pos)
13906#define TSC_IOCCR_G7_IO3 TSC_IOCCR_G7_IO3_Msk
13907#define TSC_IOCCR_G7_IO4_Pos (27U)
13908#define TSC_IOCCR_G7_IO4_Msk (0x1UL << TSC_IOCCR_G7_IO4_Pos)
13909#define TSC_IOCCR_G7_IO4 TSC_IOCCR_G7_IO4_Msk
13911/******************* Bit definition for TSC_IOGCSR register *****************/
13912#define TSC_IOGCSR_G1E_Pos (0U)
13913#define TSC_IOGCSR_G1E_Msk (0x1UL << TSC_IOGCSR_G1E_Pos)
13914#define TSC_IOGCSR_G1E TSC_IOGCSR_G1E_Msk
13915#define TSC_IOGCSR_G2E_Pos (1U)
13916#define TSC_IOGCSR_G2E_Msk (0x1UL << TSC_IOGCSR_G2E_Pos)
13917#define TSC_IOGCSR_G2E TSC_IOGCSR_G2E_Msk
13918#define TSC_IOGCSR_G3E_Pos (2U)
13919#define TSC_IOGCSR_G3E_Msk (0x1UL << TSC_IOGCSR_G3E_Pos)
13920#define TSC_IOGCSR_G3E TSC_IOGCSR_G3E_Msk
13921#define TSC_IOGCSR_G4E_Pos (3U)
13922#define TSC_IOGCSR_G4E_Msk (0x1UL << TSC_IOGCSR_G4E_Pos)
13923#define TSC_IOGCSR_G4E TSC_IOGCSR_G4E_Msk
13924#define TSC_IOGCSR_G5E_Pos (4U)
13925#define TSC_IOGCSR_G5E_Msk (0x1UL << TSC_IOGCSR_G5E_Pos)
13926#define TSC_IOGCSR_G5E TSC_IOGCSR_G5E_Msk
13927#define TSC_IOGCSR_G6E_Pos (5U)
13928#define TSC_IOGCSR_G6E_Msk (0x1UL << TSC_IOGCSR_G6E_Pos)
13929#define TSC_IOGCSR_G6E TSC_IOGCSR_G6E_Msk
13930#define TSC_IOGCSR_G7E_Pos (6U)
13931#define TSC_IOGCSR_G7E_Msk (0x1UL << TSC_IOGCSR_G7E_Pos)
13932#define TSC_IOGCSR_G7E TSC_IOGCSR_G7E_Msk
13933#define TSC_IOGCSR_G1S_Pos (16U)
13934#define TSC_IOGCSR_G1S_Msk (0x1UL << TSC_IOGCSR_G1S_Pos)
13935#define TSC_IOGCSR_G1S TSC_IOGCSR_G1S_Msk
13936#define TSC_IOGCSR_G2S_Pos (17U)
13937#define TSC_IOGCSR_G2S_Msk (0x1UL << TSC_IOGCSR_G2S_Pos)
13938#define TSC_IOGCSR_G2S TSC_IOGCSR_G2S_Msk
13939#define TSC_IOGCSR_G3S_Pos (18U)
13940#define TSC_IOGCSR_G3S_Msk (0x1UL << TSC_IOGCSR_G3S_Pos)
13941#define TSC_IOGCSR_G3S TSC_IOGCSR_G3S_Msk
13942#define TSC_IOGCSR_G4S_Pos (19U)
13943#define TSC_IOGCSR_G4S_Msk (0x1UL << TSC_IOGCSR_G4S_Pos)
13944#define TSC_IOGCSR_G4S TSC_IOGCSR_G4S_Msk
13945#define TSC_IOGCSR_G5S_Pos (20U)
13946#define TSC_IOGCSR_G5S_Msk (0x1UL << TSC_IOGCSR_G5S_Pos)
13947#define TSC_IOGCSR_G5S TSC_IOGCSR_G5S_Msk
13948#define TSC_IOGCSR_G6S_Pos (21U)
13949#define TSC_IOGCSR_G6S_Msk (0x1UL << TSC_IOGCSR_G6S_Pos)
13950#define TSC_IOGCSR_G6S TSC_IOGCSR_G6S_Msk
13951#define TSC_IOGCSR_G7S_Pos (22U)
13952#define TSC_IOGCSR_G7S_Msk (0x1UL << TSC_IOGCSR_G7S_Pos)
13953#define TSC_IOGCSR_G7S TSC_IOGCSR_G7S_Msk
13955/******************* Bit definition for TSC_IOGXCR register *****************/
13956#define TSC_IOGXCR_CNT_Pos (0U)
13957#define TSC_IOGXCR_CNT_Msk (0x3FFFUL << TSC_IOGXCR_CNT_Pos)
13958#define TSC_IOGXCR_CNT TSC_IOGXCR_CNT_Msk
13960/******************************************************************************/
13961/* */
13962/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
13963/* */
13964/******************************************************************************/
13965
13966/*
13967* @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)
13968*/
13969#define USART_TCBGT_SUPPORT
13970
13971/****************** Bit definition for USART_CR1 register *******************/
13972#define USART_CR1_UE_Pos (0U)
13973#define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos)
13974#define USART_CR1_UE USART_CR1_UE_Msk
13975#define USART_CR1_UESM_Pos (1U)
13976#define USART_CR1_UESM_Msk (0x1UL << USART_CR1_UESM_Pos)
13977#define USART_CR1_UESM USART_CR1_UESM_Msk
13978#define USART_CR1_RE_Pos (2U)
13979#define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos)
13980#define USART_CR1_RE USART_CR1_RE_Msk
13981#define USART_CR1_TE_Pos (3U)
13982#define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos)
13983#define USART_CR1_TE USART_CR1_TE_Msk
13984#define USART_CR1_IDLEIE_Pos (4U)
13985#define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos)
13986#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk
13987#define USART_CR1_RXNEIE_Pos (5U)
13988#define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos)
13989#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk
13990#define USART_CR1_TCIE_Pos (6U)
13991#define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos)
13992#define USART_CR1_TCIE USART_CR1_TCIE_Msk
13993#define USART_CR1_TXEIE_Pos (7U)
13994#define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos)
13995#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk
13996#define USART_CR1_PEIE_Pos (8U)
13997#define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos)
13998#define USART_CR1_PEIE USART_CR1_PEIE_Msk
13999#define USART_CR1_PS_Pos (9U)
14000#define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos)
14001#define USART_CR1_PS USART_CR1_PS_Msk
14002#define USART_CR1_PCE_Pos (10U)
14003#define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos)
14004#define USART_CR1_PCE USART_CR1_PCE_Msk
14005#define USART_CR1_WAKE_Pos (11U)
14006#define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos)
14007#define USART_CR1_WAKE USART_CR1_WAKE_Msk
14008#define USART_CR1_M_Pos (12U)
14009#define USART_CR1_M_Msk (0x10001UL << USART_CR1_M_Pos)
14010#define USART_CR1_M USART_CR1_M_Msk
14011#define USART_CR1_M0_Pos (12U)
14012#define USART_CR1_M0_Msk (0x1UL << USART_CR1_M0_Pos)
14013#define USART_CR1_M0 USART_CR1_M0_Msk
14014#define USART_CR1_MME_Pos (13U)
14015#define USART_CR1_MME_Msk (0x1UL << USART_CR1_MME_Pos)
14016#define USART_CR1_MME USART_CR1_MME_Msk
14017#define USART_CR1_CMIE_Pos (14U)
14018#define USART_CR1_CMIE_Msk (0x1UL << USART_CR1_CMIE_Pos)
14019#define USART_CR1_CMIE USART_CR1_CMIE_Msk
14020#define USART_CR1_OVER8_Pos (15U)
14021#define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos)
14022#define USART_CR1_OVER8 USART_CR1_OVER8_Msk
14023#define USART_CR1_DEDT_Pos (16U)
14024#define USART_CR1_DEDT_Msk (0x1FUL << USART_CR1_DEDT_Pos)
14025#define USART_CR1_DEDT USART_CR1_DEDT_Msk
14026#define USART_CR1_DEDT_0 (0x01UL << USART_CR1_DEDT_Pos)
14027#define USART_CR1_DEDT_1 (0x02UL << USART_CR1_DEDT_Pos)
14028#define USART_CR1_DEDT_2 (0x04UL << USART_CR1_DEDT_Pos)
14029#define USART_CR1_DEDT_3 (0x08UL << USART_CR1_DEDT_Pos)
14030#define USART_CR1_DEDT_4 (0x10UL << USART_CR1_DEDT_Pos)
14031#define USART_CR1_DEAT_Pos (21U)
14032#define USART_CR1_DEAT_Msk (0x1FUL << USART_CR1_DEAT_Pos)
14033#define USART_CR1_DEAT USART_CR1_DEAT_Msk
14034#define USART_CR1_DEAT_0 (0x01UL << USART_CR1_DEAT_Pos)
14035#define USART_CR1_DEAT_1 (0x02UL << USART_CR1_DEAT_Pos)
14036#define USART_CR1_DEAT_2 (0x04UL << USART_CR1_DEAT_Pos)
14037#define USART_CR1_DEAT_3 (0x08UL << USART_CR1_DEAT_Pos)
14038#define USART_CR1_DEAT_4 (0x10UL << USART_CR1_DEAT_Pos)
14039#define USART_CR1_RTOIE_Pos (26U)
14040#define USART_CR1_RTOIE_Msk (0x1UL << USART_CR1_RTOIE_Pos)
14041#define USART_CR1_RTOIE USART_CR1_RTOIE_Msk
14042#define USART_CR1_EOBIE_Pos (27U)
14043#define USART_CR1_EOBIE_Msk (0x1UL << USART_CR1_EOBIE_Pos)
14044#define USART_CR1_EOBIE USART_CR1_EOBIE_Msk
14045#define USART_CR1_M1_Pos (28U)
14046#define USART_CR1_M1_Msk (0x1UL << USART_CR1_M1_Pos)
14047#define USART_CR1_M1 USART_CR1_M1_Msk
14049/****************** Bit definition for USART_CR2 register *******************/
14050#define USART_CR2_ADDM7_Pos (4U)
14051#define USART_CR2_ADDM7_Msk (0x1UL << USART_CR2_ADDM7_Pos)
14052#define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk
14053#define USART_CR2_LBDL_Pos (5U)
14054#define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos)
14055#define USART_CR2_LBDL USART_CR2_LBDL_Msk
14056#define USART_CR2_LBDIE_Pos (6U)
14057#define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos)
14058#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk
14059#define USART_CR2_LBCL_Pos (8U)
14060#define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos)
14061#define USART_CR2_LBCL USART_CR2_LBCL_Msk
14062#define USART_CR2_CPHA_Pos (9U)
14063#define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos)
14064#define USART_CR2_CPHA USART_CR2_CPHA_Msk
14065#define USART_CR2_CPOL_Pos (10U)
14066#define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos)
14067#define USART_CR2_CPOL USART_CR2_CPOL_Msk
14068#define USART_CR2_CLKEN_Pos (11U)
14069#define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos)
14070#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk
14071#define USART_CR2_STOP_Pos (12U)
14072#define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos)
14073#define USART_CR2_STOP USART_CR2_STOP_Msk
14074#define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos)
14075#define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos)
14076#define USART_CR2_LINEN_Pos (14U)
14077#define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos)
14078#define USART_CR2_LINEN USART_CR2_LINEN_Msk
14079#define USART_CR2_SWAP_Pos (15U)
14080#define USART_CR2_SWAP_Msk (0x1UL << USART_CR2_SWAP_Pos)
14081#define USART_CR2_SWAP USART_CR2_SWAP_Msk
14082#define USART_CR2_RXINV_Pos (16U)
14083#define USART_CR2_RXINV_Msk (0x1UL << USART_CR2_RXINV_Pos)
14084#define USART_CR2_RXINV USART_CR2_RXINV_Msk
14085#define USART_CR2_TXINV_Pos (17U)
14086#define USART_CR2_TXINV_Msk (0x1UL << USART_CR2_TXINV_Pos)
14087#define USART_CR2_TXINV USART_CR2_TXINV_Msk
14088#define USART_CR2_DATAINV_Pos (18U)
14089#define USART_CR2_DATAINV_Msk (0x1UL << USART_CR2_DATAINV_Pos)
14090#define USART_CR2_DATAINV USART_CR2_DATAINV_Msk
14091#define USART_CR2_MSBFIRST_Pos (19U)
14092#define USART_CR2_MSBFIRST_Msk (0x1UL << USART_CR2_MSBFIRST_Pos)
14093#define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk
14094#define USART_CR2_ABREN_Pos (20U)
14095#define USART_CR2_ABREN_Msk (0x1UL << USART_CR2_ABREN_Pos)
14096#define USART_CR2_ABREN USART_CR2_ABREN_Msk
14097#define USART_CR2_ABRMODE_Pos (21U)
14098#define USART_CR2_ABRMODE_Msk (0x3UL << USART_CR2_ABRMODE_Pos)
14099#define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk
14100#define USART_CR2_ABRMODE_0 (0x1UL << USART_CR2_ABRMODE_Pos)
14101#define USART_CR2_ABRMODE_1 (0x2UL << USART_CR2_ABRMODE_Pos)
14102#define USART_CR2_RTOEN_Pos (23U)
14103#define USART_CR2_RTOEN_Msk (0x1UL << USART_CR2_RTOEN_Pos)
14104#define USART_CR2_RTOEN USART_CR2_RTOEN_Msk
14105#define USART_CR2_ADD_Pos (24U)
14106#define USART_CR2_ADD_Msk (0xFFUL << USART_CR2_ADD_Pos)
14107#define USART_CR2_ADD USART_CR2_ADD_Msk
14109/****************** Bit definition for USART_CR3 register *******************/
14110#define USART_CR3_EIE_Pos (0U)
14111#define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos)
14112#define USART_CR3_EIE USART_CR3_EIE_Msk
14113#define USART_CR3_IREN_Pos (1U)
14114#define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos)
14115#define USART_CR3_IREN USART_CR3_IREN_Msk
14116#define USART_CR3_IRLP_Pos (2U)
14117#define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos)
14118#define USART_CR3_IRLP USART_CR3_IRLP_Msk
14119#define USART_CR3_HDSEL_Pos (3U)
14120#define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos)
14121#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk
14122#define USART_CR3_NACK_Pos (4U)
14123#define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos)
14124#define USART_CR3_NACK USART_CR3_NACK_Msk
14125#define USART_CR3_SCEN_Pos (5U)
14126#define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos)
14127#define USART_CR3_SCEN USART_CR3_SCEN_Msk
14128#define USART_CR3_DMAR_Pos (6U)
14129#define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos)
14130#define USART_CR3_DMAR USART_CR3_DMAR_Msk
14131#define USART_CR3_DMAT_Pos (7U)
14132#define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos)
14133#define USART_CR3_DMAT USART_CR3_DMAT_Msk
14134#define USART_CR3_RTSE_Pos (8U)
14135#define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos)
14136#define USART_CR3_RTSE USART_CR3_RTSE_Msk
14137#define USART_CR3_CTSE_Pos (9U)
14138#define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos)
14139#define USART_CR3_CTSE USART_CR3_CTSE_Msk
14140#define USART_CR3_CTSIE_Pos (10U)
14141#define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos)
14142#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk
14143#define USART_CR3_ONEBIT_Pos (11U)
14144#define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos)
14145#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk
14146#define USART_CR3_OVRDIS_Pos (12U)
14147#define USART_CR3_OVRDIS_Msk (0x1UL << USART_CR3_OVRDIS_Pos)
14148#define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk
14149#define USART_CR3_DDRE_Pos (13U)
14150#define USART_CR3_DDRE_Msk (0x1UL << USART_CR3_DDRE_Pos)
14151#define USART_CR3_DDRE USART_CR3_DDRE_Msk
14152#define USART_CR3_DEM_Pos (14U)
14153#define USART_CR3_DEM_Msk (0x1UL << USART_CR3_DEM_Pos)
14154#define USART_CR3_DEM USART_CR3_DEM_Msk
14155#define USART_CR3_DEP_Pos (15U)
14156#define USART_CR3_DEP_Msk (0x1UL << USART_CR3_DEP_Pos)
14157#define USART_CR3_DEP USART_CR3_DEP_Msk
14158#define USART_CR3_SCARCNT_Pos (17U)
14159#define USART_CR3_SCARCNT_Msk (0x7UL << USART_CR3_SCARCNT_Pos)
14160#define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk
14161#define USART_CR3_SCARCNT_0 (0x1UL << USART_CR3_SCARCNT_Pos)
14162#define USART_CR3_SCARCNT_1 (0x2UL << USART_CR3_SCARCNT_Pos)
14163#define USART_CR3_SCARCNT_2 (0x4UL << USART_CR3_SCARCNT_Pos)
14164#define USART_CR3_WUS_Pos (20U)
14165#define USART_CR3_WUS_Msk (0x3UL << USART_CR3_WUS_Pos)
14166#define USART_CR3_WUS USART_CR3_WUS_Msk
14167#define USART_CR3_WUS_0 (0x1UL << USART_CR3_WUS_Pos)
14168#define USART_CR3_WUS_1 (0x2UL << USART_CR3_WUS_Pos)
14169#define USART_CR3_WUFIE_Pos (22U)
14170#define USART_CR3_WUFIE_Msk (0x1UL << USART_CR3_WUFIE_Pos)
14171#define USART_CR3_WUFIE USART_CR3_WUFIE_Msk
14172#define USART_CR3_UCESM_Pos (23U)
14173#define USART_CR3_UCESM_Msk (0x1UL << USART_CR3_UCESM_Pos)
14174#define USART_CR3_UCESM USART_CR3_UCESM_Msk
14175#define USART_CR3_TCBGTIE_Pos (24U)
14176#define USART_CR3_TCBGTIE_Msk (0x1UL << USART_CR3_TCBGTIE_Pos)
14177#define USART_CR3_TCBGTIE USART_CR3_TCBGTIE_Msk
14179/****************** Bit definition for USART_BRR register *******************/
14180#define USART_BRR_DIV_FRACTION_Pos (0U)
14181#define USART_BRR_DIV_FRACTION_Msk (0xFUL << USART_BRR_DIV_FRACTION_Pos)
14182#define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk
14183#define USART_BRR_DIV_MANTISSA_Pos (4U)
14184#define USART_BRR_DIV_MANTISSA_Msk (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos)
14185#define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk
14187/****************** Bit definition for USART_GTPR register ******************/
14188#define USART_GTPR_PSC_Pos (0U)
14189#define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos)
14190#define USART_GTPR_PSC USART_GTPR_PSC_Msk
14191#define USART_GTPR_GT_Pos (8U)
14192#define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos)
14193#define USART_GTPR_GT USART_GTPR_GT_Msk
14195/******************* Bit definition for USART_RTOR register *****************/
14196#define USART_RTOR_RTO_Pos (0U)
14197#define USART_RTOR_RTO_Msk (0xFFFFFFUL << USART_RTOR_RTO_Pos)
14198#define USART_RTOR_RTO USART_RTOR_RTO_Msk
14199#define USART_RTOR_BLEN_Pos (24U)
14200#define USART_RTOR_BLEN_Msk (0xFFUL << USART_RTOR_BLEN_Pos)
14201#define USART_RTOR_BLEN USART_RTOR_BLEN_Msk
14203/******************* Bit definition for USART_RQR register ******************/
14204#define USART_RQR_ABRRQ_Pos (0U)
14205#define USART_RQR_ABRRQ_Msk (0x1UL << USART_RQR_ABRRQ_Pos)
14206#define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk
14207#define USART_RQR_SBKRQ_Pos (1U)
14208#define USART_RQR_SBKRQ_Msk (0x1UL << USART_RQR_SBKRQ_Pos)
14209#define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk
14210#define USART_RQR_MMRQ_Pos (2U)
14211#define USART_RQR_MMRQ_Msk (0x1UL << USART_RQR_MMRQ_Pos)
14212#define USART_RQR_MMRQ USART_RQR_MMRQ_Msk
14213#define USART_RQR_RXFRQ_Pos (3U)
14214#define USART_RQR_RXFRQ_Msk (0x1UL << USART_RQR_RXFRQ_Pos)
14215#define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk
14216#define USART_RQR_TXFRQ_Pos (4U)
14217#define USART_RQR_TXFRQ_Msk (0x1UL << USART_RQR_TXFRQ_Pos)
14218#define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk
14220/******************* Bit definition for USART_ISR register ******************/
14221#define USART_ISR_PE_Pos (0U)
14222#define USART_ISR_PE_Msk (0x1UL << USART_ISR_PE_Pos)
14223#define USART_ISR_PE USART_ISR_PE_Msk
14224#define USART_ISR_FE_Pos (1U)
14225#define USART_ISR_FE_Msk (0x1UL << USART_ISR_FE_Pos)
14226#define USART_ISR_FE USART_ISR_FE_Msk
14227#define USART_ISR_NE_Pos (2U)
14228#define USART_ISR_NE_Msk (0x1UL << USART_ISR_NE_Pos)
14229#define USART_ISR_NE USART_ISR_NE_Msk
14230#define USART_ISR_ORE_Pos (3U)
14231#define USART_ISR_ORE_Msk (0x1UL << USART_ISR_ORE_Pos)
14232#define USART_ISR_ORE USART_ISR_ORE_Msk
14233#define USART_ISR_IDLE_Pos (4U)
14234#define USART_ISR_IDLE_Msk (0x1UL << USART_ISR_IDLE_Pos)
14235#define USART_ISR_IDLE USART_ISR_IDLE_Msk
14236#define USART_ISR_RXNE_Pos (5U)
14237#define USART_ISR_RXNE_Msk (0x1UL << USART_ISR_RXNE_Pos)
14238#define USART_ISR_RXNE USART_ISR_RXNE_Msk
14239#define USART_ISR_TC_Pos (6U)
14240#define USART_ISR_TC_Msk (0x1UL << USART_ISR_TC_Pos)
14241#define USART_ISR_TC USART_ISR_TC_Msk
14242#define USART_ISR_TXE_Pos (7U)
14243#define USART_ISR_TXE_Msk (0x1UL << USART_ISR_TXE_Pos)
14244#define USART_ISR_TXE USART_ISR_TXE_Msk
14245#define USART_ISR_LBDF_Pos (8U)
14246#define USART_ISR_LBDF_Msk (0x1UL << USART_ISR_LBDF_Pos)
14247#define USART_ISR_LBDF USART_ISR_LBDF_Msk
14248#define USART_ISR_CTSIF_Pos (9U)
14249#define USART_ISR_CTSIF_Msk (0x1UL << USART_ISR_CTSIF_Pos)
14250#define USART_ISR_CTSIF USART_ISR_CTSIF_Msk
14251#define USART_ISR_CTS_Pos (10U)
14252#define USART_ISR_CTS_Msk (0x1UL << USART_ISR_CTS_Pos)
14253#define USART_ISR_CTS USART_ISR_CTS_Msk
14254#define USART_ISR_RTOF_Pos (11U)
14255#define USART_ISR_RTOF_Msk (0x1UL << USART_ISR_RTOF_Pos)
14256#define USART_ISR_RTOF USART_ISR_RTOF_Msk
14257#define USART_ISR_EOBF_Pos (12U)
14258#define USART_ISR_EOBF_Msk (0x1UL << USART_ISR_EOBF_Pos)
14259#define USART_ISR_EOBF USART_ISR_EOBF_Msk
14260#define USART_ISR_ABRE_Pos (14U)
14261#define USART_ISR_ABRE_Msk (0x1UL << USART_ISR_ABRE_Pos)
14262#define USART_ISR_ABRE USART_ISR_ABRE_Msk
14263#define USART_ISR_ABRF_Pos (15U)
14264#define USART_ISR_ABRF_Msk (0x1UL << USART_ISR_ABRF_Pos)
14265#define USART_ISR_ABRF USART_ISR_ABRF_Msk
14266#define USART_ISR_BUSY_Pos (16U)
14267#define USART_ISR_BUSY_Msk (0x1UL << USART_ISR_BUSY_Pos)
14268#define USART_ISR_BUSY USART_ISR_BUSY_Msk
14269#define USART_ISR_CMF_Pos (17U)
14270#define USART_ISR_CMF_Msk (0x1UL << USART_ISR_CMF_Pos)
14271#define USART_ISR_CMF USART_ISR_CMF_Msk
14272#define USART_ISR_SBKF_Pos (18U)
14273#define USART_ISR_SBKF_Msk (0x1UL << USART_ISR_SBKF_Pos)
14274#define USART_ISR_SBKF USART_ISR_SBKF_Msk
14275#define USART_ISR_RWU_Pos (19U)
14276#define USART_ISR_RWU_Msk (0x1UL << USART_ISR_RWU_Pos)
14277#define USART_ISR_RWU USART_ISR_RWU_Msk
14278#define USART_ISR_WUF_Pos (20U)
14279#define USART_ISR_WUF_Msk (0x1UL << USART_ISR_WUF_Pos)
14280#define USART_ISR_WUF USART_ISR_WUF_Msk
14281#define USART_ISR_TEACK_Pos (21U)
14282#define USART_ISR_TEACK_Msk (0x1UL << USART_ISR_TEACK_Pos)
14283#define USART_ISR_TEACK USART_ISR_TEACK_Msk
14284#define USART_ISR_REACK_Pos (22U)
14285#define USART_ISR_REACK_Msk (0x1UL << USART_ISR_REACK_Pos)
14286#define USART_ISR_REACK USART_ISR_REACK_Msk
14287#define USART_ISR_TCBGT_Pos (25U)
14288#define USART_ISR_TCBGT_Msk (0x1UL << USART_ISR_TCBGT_Pos)
14289#define USART_ISR_TCBGT USART_ISR_TCBGT_Msk
14291/******************* Bit definition for USART_ICR register ******************/
14292#define USART_ICR_PECF_Pos (0U)
14293#define USART_ICR_PECF_Msk (0x1UL << USART_ICR_PECF_Pos)
14294#define USART_ICR_PECF USART_ICR_PECF_Msk
14295#define USART_ICR_FECF_Pos (1U)
14296#define USART_ICR_FECF_Msk (0x1UL << USART_ICR_FECF_Pos)
14297#define USART_ICR_FECF USART_ICR_FECF_Msk
14298#define USART_ICR_NECF_Pos (2U)
14299#define USART_ICR_NECF_Msk (0x1UL << USART_ICR_NECF_Pos)
14300#define USART_ICR_NECF USART_ICR_NECF_Msk
14301#define USART_ICR_ORECF_Pos (3U)
14302#define USART_ICR_ORECF_Msk (0x1UL << USART_ICR_ORECF_Pos)
14303#define USART_ICR_ORECF USART_ICR_ORECF_Msk
14304#define USART_ICR_IDLECF_Pos (4U)
14305#define USART_ICR_IDLECF_Msk (0x1UL << USART_ICR_IDLECF_Pos)
14306#define USART_ICR_IDLECF USART_ICR_IDLECF_Msk
14307#define USART_ICR_TCCF_Pos (6U)
14308#define USART_ICR_TCCF_Msk (0x1UL << USART_ICR_TCCF_Pos)
14309#define USART_ICR_TCCF USART_ICR_TCCF_Msk
14310#define USART_ICR_TCBGTCF_Pos (7U)
14311#define USART_ICR_TCBGTCF_Msk (0x1UL << USART_ICR_TCBGTCF_Pos)
14312#define USART_ICR_TCBGTCF USART_ICR_TCBGTCF_Msk
14313#define USART_ICR_LBDCF_Pos (8U)
14314#define USART_ICR_LBDCF_Msk (0x1UL << USART_ICR_LBDCF_Pos)
14315#define USART_ICR_LBDCF USART_ICR_LBDCF_Msk
14316#define USART_ICR_CTSCF_Pos (9U)
14317#define USART_ICR_CTSCF_Msk (0x1UL << USART_ICR_CTSCF_Pos)
14318#define USART_ICR_CTSCF USART_ICR_CTSCF_Msk
14319#define USART_ICR_RTOCF_Pos (11U)
14320#define USART_ICR_RTOCF_Msk (0x1UL << USART_ICR_RTOCF_Pos)
14321#define USART_ICR_RTOCF USART_ICR_RTOCF_Msk
14322#define USART_ICR_EOBCF_Pos (12U)
14323#define USART_ICR_EOBCF_Msk (0x1UL << USART_ICR_EOBCF_Pos)
14324#define USART_ICR_EOBCF USART_ICR_EOBCF_Msk
14325#define USART_ICR_CMCF_Pos (17U)
14326#define USART_ICR_CMCF_Msk (0x1UL << USART_ICR_CMCF_Pos)
14327#define USART_ICR_CMCF USART_ICR_CMCF_Msk
14328#define USART_ICR_WUCF_Pos (20U)
14329#define USART_ICR_WUCF_Msk (0x1UL << USART_ICR_WUCF_Pos)
14330#define USART_ICR_WUCF USART_ICR_WUCF_Msk
14332/* Legacy defines */
14333#define USART_ICR_NCF_Pos USART_ICR_NECF_Pos
14334#define USART_ICR_NCF_Msk USART_ICR_NECF_Msk
14335#define USART_ICR_NCF USART_ICR_NECF
14336
14337/******************* Bit definition for USART_RDR register ******************/
14338#define USART_RDR_RDR_Pos (0U)
14339#define USART_RDR_RDR_Msk (0x1FFUL << USART_RDR_RDR_Pos)
14340#define USART_RDR_RDR USART_RDR_RDR_Msk
14342/******************* Bit definition for USART_TDR register ******************/
14343#define USART_TDR_TDR_Pos (0U)
14344#define USART_TDR_TDR_Msk (0x1FFUL << USART_TDR_TDR_Pos)
14345#define USART_TDR_TDR USART_TDR_TDR_Msk
14347/******************************************************************************/
14348/* */
14349/* Single Wire Protocol Master Interface (SWPMI) */
14350/* */
14351/******************************************************************************/
14352
14353/******************* Bit definition for SWPMI_CR register ********************/
14354#define SWPMI_CR_RXDMA_Pos (0U)
14355#define SWPMI_CR_RXDMA_Msk (0x1UL << SWPMI_CR_RXDMA_Pos)
14356#define SWPMI_CR_RXDMA SWPMI_CR_RXDMA_Msk
14357#define SWPMI_CR_TXDMA_Pos (1U)
14358#define SWPMI_CR_TXDMA_Msk (0x1UL << SWPMI_CR_TXDMA_Pos)
14359#define SWPMI_CR_TXDMA SWPMI_CR_TXDMA_Msk
14360#define SWPMI_CR_RXMODE_Pos (2U)
14361#define SWPMI_CR_RXMODE_Msk (0x1UL << SWPMI_CR_RXMODE_Pos)
14362#define SWPMI_CR_RXMODE SWPMI_CR_RXMODE_Msk
14363#define SWPMI_CR_TXMODE_Pos (3U)
14364#define SWPMI_CR_TXMODE_Msk (0x1UL << SWPMI_CR_TXMODE_Pos)
14365#define SWPMI_CR_TXMODE SWPMI_CR_TXMODE_Msk
14366#define SWPMI_CR_LPBK_Pos (4U)
14367#define SWPMI_CR_LPBK_Msk (0x1UL << SWPMI_CR_LPBK_Pos)
14368#define SWPMI_CR_LPBK SWPMI_CR_LPBK_Msk
14369#define SWPMI_CR_SWPACT_Pos (5U)
14370#define SWPMI_CR_SWPACT_Msk (0x1UL << SWPMI_CR_SWPACT_Pos)
14371#define SWPMI_CR_SWPACT SWPMI_CR_SWPACT_Msk
14372#define SWPMI_CR_DEACT_Pos (10U)
14373#define SWPMI_CR_DEACT_Msk (0x1UL << SWPMI_CR_DEACT_Pos)
14374#define SWPMI_CR_DEACT SWPMI_CR_DEACT_Msk
14376/******************* Bit definition for SWPMI_BRR register ********************/
14377#define SWPMI_BRR_BR_Pos (0U)
14378#define SWPMI_BRR_BR_Msk (0x3FUL << SWPMI_BRR_BR_Pos)
14379#define SWPMI_BRR_BR SWPMI_BRR_BR_Msk
14381/******************* Bit definition for SWPMI_ISR register ********************/
14382#define SWPMI_ISR_RXBFF_Pos (0U)
14383#define SWPMI_ISR_RXBFF_Msk (0x1UL << SWPMI_ISR_RXBFF_Pos)
14384#define SWPMI_ISR_RXBFF SWPMI_ISR_RXBFF_Msk
14385#define SWPMI_ISR_TXBEF_Pos (1U)
14386#define SWPMI_ISR_TXBEF_Msk (0x1UL << SWPMI_ISR_TXBEF_Pos)
14387#define SWPMI_ISR_TXBEF SWPMI_ISR_TXBEF_Msk
14388#define SWPMI_ISR_RXBERF_Pos (2U)
14389#define SWPMI_ISR_RXBERF_Msk (0x1UL << SWPMI_ISR_RXBERF_Pos)
14390#define SWPMI_ISR_RXBERF SWPMI_ISR_RXBERF_Msk
14391#define SWPMI_ISR_RXOVRF_Pos (3U)
14392#define SWPMI_ISR_RXOVRF_Msk (0x1UL << SWPMI_ISR_RXOVRF_Pos)
14393#define SWPMI_ISR_RXOVRF SWPMI_ISR_RXOVRF_Msk
14394#define SWPMI_ISR_TXUNRF_Pos (4U)
14395#define SWPMI_ISR_TXUNRF_Msk (0x1UL << SWPMI_ISR_TXUNRF_Pos)
14396#define SWPMI_ISR_TXUNRF SWPMI_ISR_TXUNRF_Msk
14397#define SWPMI_ISR_RXNE_Pos (5U)
14398#define SWPMI_ISR_RXNE_Msk (0x1UL << SWPMI_ISR_RXNE_Pos)
14399#define SWPMI_ISR_RXNE SWPMI_ISR_RXNE_Msk
14400#define SWPMI_ISR_TXE_Pos (6U)
14401#define SWPMI_ISR_TXE_Msk (0x1UL << SWPMI_ISR_TXE_Pos)
14402#define SWPMI_ISR_TXE SWPMI_ISR_TXE_Msk
14403#define SWPMI_ISR_TCF_Pos (7U)
14404#define SWPMI_ISR_TCF_Msk (0x1UL << SWPMI_ISR_TCF_Pos)
14405#define SWPMI_ISR_TCF SWPMI_ISR_TCF_Msk
14406#define SWPMI_ISR_SRF_Pos (8U)
14407#define SWPMI_ISR_SRF_Msk (0x1UL << SWPMI_ISR_SRF_Pos)
14408#define SWPMI_ISR_SRF SWPMI_ISR_SRF_Msk
14409#define SWPMI_ISR_SUSP_Pos (9U)
14410#define SWPMI_ISR_SUSP_Msk (0x1UL << SWPMI_ISR_SUSP_Pos)
14411#define SWPMI_ISR_SUSP SWPMI_ISR_SUSP_Msk
14412#define SWPMI_ISR_DEACTF_Pos (10U)
14413#define SWPMI_ISR_DEACTF_Msk (0x1UL << SWPMI_ISR_DEACTF_Pos)
14414#define SWPMI_ISR_DEACTF SWPMI_ISR_DEACTF_Msk
14416/******************* Bit definition for SWPMI_ICR register ********************/
14417#define SWPMI_ICR_CRXBFF_Pos (0U)
14418#define SWPMI_ICR_CRXBFF_Msk (0x1UL << SWPMI_ICR_CRXBFF_Pos)
14419#define SWPMI_ICR_CRXBFF SWPMI_ICR_CRXBFF_Msk
14420#define SWPMI_ICR_CTXBEF_Pos (1U)
14421#define SWPMI_ICR_CTXBEF_Msk (0x1UL << SWPMI_ICR_CTXBEF_Pos)
14422#define SWPMI_ICR_CTXBEF SWPMI_ICR_CTXBEF_Msk
14423#define SWPMI_ICR_CRXBERF_Pos (2U)
14424#define SWPMI_ICR_CRXBERF_Msk (0x1UL << SWPMI_ICR_CRXBERF_Pos)
14425#define SWPMI_ICR_CRXBERF SWPMI_ICR_CRXBERF_Msk
14426#define SWPMI_ICR_CRXOVRF_Pos (3U)
14427#define SWPMI_ICR_CRXOVRF_Msk (0x1UL << SWPMI_ICR_CRXOVRF_Pos)
14428#define SWPMI_ICR_CRXOVRF SWPMI_ICR_CRXOVRF_Msk
14429#define SWPMI_ICR_CTXUNRF_Pos (4U)
14430#define SWPMI_ICR_CTXUNRF_Msk (0x1UL << SWPMI_ICR_CTXUNRF_Pos)
14431#define SWPMI_ICR_CTXUNRF SWPMI_ICR_CTXUNRF_Msk
14432#define SWPMI_ICR_CTCF_Pos (7U)
14433#define SWPMI_ICR_CTCF_Msk (0x1UL << SWPMI_ICR_CTCF_Pos)
14434#define SWPMI_ICR_CTCF SWPMI_ICR_CTCF_Msk
14435#define SWPMI_ICR_CSRF_Pos (8U)
14436#define SWPMI_ICR_CSRF_Msk (0x1UL << SWPMI_ICR_CSRF_Pos)
14437#define SWPMI_ICR_CSRF SWPMI_ICR_CSRF_Msk
14439/******************* Bit definition for SWPMI_IER register ********************/
14440#define SWPMI_IER_SRIE_Pos (8U)
14441#define SWPMI_IER_SRIE_Msk (0x1UL << SWPMI_IER_SRIE_Pos)
14442#define SWPMI_IER_SRIE SWPMI_IER_SRIE_Msk
14443#define SWPMI_IER_TCIE_Pos (7U)
14444#define SWPMI_IER_TCIE_Msk (0x1UL << SWPMI_IER_TCIE_Pos)
14445#define SWPMI_IER_TCIE SWPMI_IER_TCIE_Msk
14446#define SWPMI_IER_TIE_Pos (6U)
14447#define SWPMI_IER_TIE_Msk (0x1UL << SWPMI_IER_TIE_Pos)
14448#define SWPMI_IER_TIE SWPMI_IER_TIE_Msk
14449#define SWPMI_IER_RIE_Pos (5U)
14450#define SWPMI_IER_RIE_Msk (0x1UL << SWPMI_IER_RIE_Pos)
14451#define SWPMI_IER_RIE SWPMI_IER_RIE_Msk
14452#define SWPMI_IER_TXUNRIE_Pos (4U)
14453#define SWPMI_IER_TXUNRIE_Msk (0x1UL << SWPMI_IER_TXUNRIE_Pos)
14454#define SWPMI_IER_TXUNRIE SWPMI_IER_TXUNRIE_Msk
14455#define SWPMI_IER_RXOVRIE_Pos (3U)
14456#define SWPMI_IER_RXOVRIE_Msk (0x1UL << SWPMI_IER_RXOVRIE_Pos)
14457#define SWPMI_IER_RXOVRIE SWPMI_IER_RXOVRIE_Msk
14458#define SWPMI_IER_RXBERIE_Pos (2U)
14459#define SWPMI_IER_RXBERIE_Msk (0x1UL << SWPMI_IER_RXBERIE_Pos)
14460#define SWPMI_IER_RXBERIE SWPMI_IER_RXBERIE_Msk
14461#define SWPMI_IER_TXBEIE_Pos (1U)
14462#define SWPMI_IER_TXBEIE_Msk (0x1UL << SWPMI_IER_TXBEIE_Pos)
14463#define SWPMI_IER_TXBEIE SWPMI_IER_TXBEIE_Msk
14464#define SWPMI_IER_RXBFIE_Pos (0U)
14465#define SWPMI_IER_RXBFIE_Msk (0x1UL << SWPMI_IER_RXBFIE_Pos)
14466#define SWPMI_IER_RXBFIE SWPMI_IER_RXBFIE_Msk
14468/******************* Bit definition for SWPMI_RFL register ********************/
14469#define SWPMI_RFL_RFL_Pos (0U)
14470#define SWPMI_RFL_RFL_Msk (0x1FUL << SWPMI_RFL_RFL_Pos)
14471#define SWPMI_RFL_RFL SWPMI_RFL_RFL_Msk
14472#define SWPMI_RFL_RFL_0_1_Pos (0U)
14473#define SWPMI_RFL_RFL_0_1_Msk (0x3UL << SWPMI_RFL_RFL_0_1_Pos)
14474#define SWPMI_RFL_RFL_0_1 SWPMI_RFL_RFL_0_1_Msk
14476/******************* Bit definition for SWPMI_TDR register ********************/
14477#define SWPMI_TDR_TD_Pos (0U)
14478#define SWPMI_TDR_TD_Msk (0xFFFFFFFFUL << SWPMI_TDR_TD_Pos)
14479#define SWPMI_TDR_TD SWPMI_TDR_TD_Msk
14481/******************* Bit definition for SWPMI_RDR register ********************/
14482#define SWPMI_RDR_RD_Pos (0U)
14483#define SWPMI_RDR_RD_Msk (0xFFFFFFFFUL << SWPMI_RDR_RD_Pos)
14484#define SWPMI_RDR_RD SWPMI_RDR_RD_Msk
14486/******************* Bit definition for SWPMI_OR register ********************/
14487#define SWPMI_OR_TBYP_Pos (0U)
14488#define SWPMI_OR_TBYP_Msk (0x1UL << SWPMI_OR_TBYP_Pos)
14489#define SWPMI_OR_TBYP SWPMI_OR_TBYP_Msk
14490#define SWPMI_OR_CLASS_Pos (1U)
14491#define SWPMI_OR_CLASS_Msk (0x1UL << SWPMI_OR_CLASS_Pos)
14492#define SWPMI_OR_CLASS SWPMI_OR_CLASS_Msk
14494/******************************************************************************/
14495/* */
14496/* VREFBUF */
14497/* */
14498/******************************************************************************/
14499/******************* Bit definition for VREFBUF_CSR register ****************/
14500#define VREFBUF_CSR_ENVR_Pos (0U)
14501#define VREFBUF_CSR_ENVR_Msk (0x1UL << VREFBUF_CSR_ENVR_Pos)
14502#define VREFBUF_CSR_ENVR VREFBUF_CSR_ENVR_Msk
14503#define VREFBUF_CSR_HIZ_Pos (1U)
14504#define VREFBUF_CSR_HIZ_Msk (0x1UL << VREFBUF_CSR_HIZ_Pos)
14505#define VREFBUF_CSR_HIZ VREFBUF_CSR_HIZ_Msk
14506#define VREFBUF_CSR_VRS_Pos (2U)
14507#define VREFBUF_CSR_VRS_Msk (0x1UL << VREFBUF_CSR_VRS_Pos)
14508#define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk
14509#define VREFBUF_CSR_VRR_Pos (3U)
14510#define VREFBUF_CSR_VRR_Msk (0x1UL << VREFBUF_CSR_VRR_Pos)
14511#define VREFBUF_CSR_VRR VREFBUF_CSR_VRR_Msk
14513/******************* Bit definition for VREFBUF_CCR register ******************/
14514#define VREFBUF_CCR_TRIM_Pos (0U)
14515#define VREFBUF_CCR_TRIM_Msk (0x3FUL << VREFBUF_CCR_TRIM_Pos)
14516#define VREFBUF_CCR_TRIM VREFBUF_CCR_TRIM_Msk
14518/******************************************************************************/
14519/* */
14520/* Window WATCHDOG */
14521/* */
14522/******************************************************************************/
14523/******************* Bit definition for WWDG_CR register ********************/
14524#define WWDG_CR_T_Pos (0U)
14525#define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos)
14526#define WWDG_CR_T WWDG_CR_T_Msk
14527#define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos)
14528#define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos)
14529#define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos)
14530#define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos)
14531#define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos)
14532#define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos)
14533#define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos)
14535#define WWDG_CR_WDGA_Pos (7U)
14536#define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos)
14537#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk
14539/******************* Bit definition for WWDG_CFR register *******************/
14540#define WWDG_CFR_W_Pos (0U)
14541#define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos)
14542#define WWDG_CFR_W WWDG_CFR_W_Msk
14543#define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos)
14544#define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos)
14545#define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos)
14546#define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos)
14547#define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos)
14548#define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos)
14549#define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos)
14551#define WWDG_CFR_WDGTB_Pos (7U)
14552#define WWDG_CFR_WDGTB_Msk (0x3UL << WWDG_CFR_WDGTB_Pos)
14553#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk
14554#define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos)
14555#define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos)
14557#define WWDG_CFR_EWI_Pos (9U)
14558#define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos)
14559#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk
14561/******************* Bit definition for WWDG_SR register ********************/
14562#define WWDG_SR_EWIF_Pos (0U)
14563#define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos)
14564#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk
14567/******************************************************************************/
14568/* */
14569/* Debug MCU */
14570/* */
14571/******************************************************************************/
14572/******************** Bit definition for DBGMCU_IDCODE register *************/
14573#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
14574#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos)
14575#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
14576#define DBGMCU_IDCODE_REV_ID_Pos (16U)
14577#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos)
14578#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
14579
14580/******************** Bit definition for DBGMCU_CR register *****************/
14581#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
14582#define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos)
14583#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
14584#define DBGMCU_CR_DBG_STOP_Pos (1U)
14585#define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos)
14586#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
14587#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
14588#define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos)
14589#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
14590#define DBGMCU_CR_TRACE_IOEN_Pos (5U)
14591#define DBGMCU_CR_TRACE_IOEN_Msk (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos)
14592#define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
14593
14594#define DBGMCU_CR_TRACE_MODE_Pos (6U)
14595#define DBGMCU_CR_TRACE_MODE_Msk (0x3UL << DBGMCU_CR_TRACE_MODE_Pos)
14596#define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
14597#define DBGMCU_CR_TRACE_MODE_0 (0x1UL << DBGMCU_CR_TRACE_MODE_Pos)
14598#define DBGMCU_CR_TRACE_MODE_1 (0x2UL << DBGMCU_CR_TRACE_MODE_Pos)
14600/******************** Bit definition for DBGMCU_APB1FZR1 register ***********/
14601#define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos (0U)
14602#define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos)
14603#define DBGMCU_APB1FZR1_DBG_TIM2_STOP DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk
14604#define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos (4U)
14605#define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos)
14606#define DBGMCU_APB1FZR1_DBG_TIM6_STOP DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk
14607#define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos (5U)
14608#define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos)
14609#define DBGMCU_APB1FZR1_DBG_TIM7_STOP DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk
14610#define DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos (10U)
14611#define DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos)
14612#define DBGMCU_APB1FZR1_DBG_RTC_STOP DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk
14613#define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos (11U)
14614#define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos)
14615#define DBGMCU_APB1FZR1_DBG_WWDG_STOP DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk
14616#define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos (12U)
14617#define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos)
14618#define DBGMCU_APB1FZR1_DBG_IWDG_STOP DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk
14619#define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos (21U)
14620#define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos)
14621#define DBGMCU_APB1FZR1_DBG_I2C1_STOP DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk
14622#define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos (22U)
14623#define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos)
14624#define DBGMCU_APB1FZR1_DBG_I2C2_STOP DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk
14625#define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos (23U)
14626#define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos)
14627#define DBGMCU_APB1FZR1_DBG_I2C3_STOP DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk
14628#define DBGMCU_APB1FZR1_DBG_CAN_STOP_Pos (25U)
14629#define DBGMCU_APB1FZR1_DBG_CAN_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_CAN_STOP_Pos)
14630#define DBGMCU_APB1FZR1_DBG_CAN_STOP DBGMCU_APB1FZR1_DBG_CAN_STOP_Msk
14631#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos (31U)
14632#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos)
14633#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk
14634
14635/******************** Bit definition for DBGMCU_APB1FZR2 register **********/
14636#define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Pos (5U)
14637#define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Msk (0x1UL << DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Pos)
14638#define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Msk
14639
14640/******************** Bit definition for DBGMCU_APB2FZ register ************/
14641#define DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos (11U)
14642#define DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos)
14643#define DBGMCU_APB2FZ_DBG_TIM1_STOP DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk
14644#define DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos (16U)
14645#define DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos)
14646#define DBGMCU_APB2FZ_DBG_TIM15_STOP DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk
14647#define DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos (17U)
14648#define DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos)
14649#define DBGMCU_APB2FZ_DBG_TIM16_STOP DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk
14650
14651
14664/******************************* ADC Instances ********************************/
14665#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
14666
14667#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
14668
14669/******************************** CAN Instances ******************************/
14670#define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN1)
14671
14672/******************************** COMP Instances ******************************/
14673#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
14674 ((INSTANCE) == COMP2))
14675
14676#define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
14677
14678/******************** COMP Instances with window mode capability **************/
14679#define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2)
14680
14681/******************************* CRC Instances ********************************/
14682#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
14683
14684/******************************* DAC Instances ********************************/
14685#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
14686
14687/******************************** DMA Instances *******************************/
14688#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
14689 ((INSTANCE) == DMA1_Channel2) || \
14690 ((INSTANCE) == DMA1_Channel3) || \
14691 ((INSTANCE) == DMA1_Channel4) || \
14692 ((INSTANCE) == DMA1_Channel5) || \
14693 ((INSTANCE) == DMA1_Channel6) || \
14694 ((INSTANCE) == DMA1_Channel7) || \
14695 ((INSTANCE) == DMA2_Channel1) || \
14696 ((INSTANCE) == DMA2_Channel2) || \
14697 ((INSTANCE) == DMA2_Channel3) || \
14698 ((INSTANCE) == DMA2_Channel4) || \
14699 ((INSTANCE) == DMA2_Channel5) || \
14700 ((INSTANCE) == DMA2_Channel6) || \
14701 ((INSTANCE) == DMA2_Channel7))
14702
14703/******************************* GPIO Instances *******************************/
14704#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
14705 ((INSTANCE) == GPIOB) || \
14706 ((INSTANCE) == GPIOC) || \
14707 ((INSTANCE) == GPIOD) || \
14708 ((INSTANCE) == GPIOE) || \
14709 ((INSTANCE) == GPIOH))
14710
14711/******************************* GPIO AF Instances ****************************/
14712/* On L4, all GPIO Bank support AF */
14713#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
14714
14715/**************************** GPIO Lock Instances *****************************/
14716/* On L4, all GPIO Bank support the Lock mechanism */
14717#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
14718
14719/******************************** I2C Instances *******************************/
14720#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
14721 ((INSTANCE) == I2C2) || \
14722 ((INSTANCE) == I2C3))
14723
14724/****************** I2C Instances : wakeup capability from stop modes *********/
14725#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
14726
14727/****************************** OPAMP Instances *******************************/
14728#define IS_OPAMP_ALL_INSTANCE(INSTANCE) ((INSTANCE) == OPAMP1)
14729
14730#define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP1_COMMON)
14731
14732/******************************* QSPI Instances *******************************/
14733#define IS_QSPI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == QUADSPI)
14734
14735/******************************* RNG Instances ********************************/
14736#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
14737
14738/****************************** RTC Instances *********************************/
14739#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
14740
14741/******************************** SAI Instances *******************************/
14742#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A) || \
14743 ((INSTANCE) == SAI1_Block_B))
14744
14745/****************************** SDMMC Instances *******************************/
14746#define IS_SDMMC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDMMC1)
14747
14748/****************************** SMBUS Instances *******************************/
14749#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
14750 ((INSTANCE) == I2C2) || \
14751 ((INSTANCE) == I2C3))
14752
14753/******************************** SPI Instances *******************************/
14754#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
14755 ((INSTANCE) == SPI2) || \
14756 ((INSTANCE) == SPI3))
14757
14758/******************************** SWPMI Instances *****************************/
14759#define IS_SWPMI_INSTANCE(INSTANCE) ((INSTANCE) == SWPMI1)
14760
14761/****************** LPTIM Instances : All supported instances *****************/
14762#define IS_LPTIM_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1) || \
14763 ((INSTANCE) == LPTIM2))
14764
14765/****************** LPTIM Instances : supporting the encoder mode *************/
14766#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
14767
14768/****************** TIM Instances : All supported instances *******************/
14769#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14770 ((INSTANCE) == TIM2) || \
14771 ((INSTANCE) == TIM6) || \
14772 ((INSTANCE) == TIM7) || \
14773 ((INSTANCE) == TIM15) || \
14774 ((INSTANCE) == TIM16))
14775
14776/****************** TIM Instances : supporting 32 bits counter ****************/
14777#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
14778
14779/****************** TIM Instances : supporting the break function *************/
14780#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14781 ((INSTANCE) == TIM15) || \
14782 ((INSTANCE) == TIM16))
14783
14784/************** TIM Instances : supporting Break source selection *************/
14785#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14786 ((INSTANCE) == TIM15) || \
14787 ((INSTANCE) == TIM16))
14788
14789/****************** TIM Instances : supporting 2 break inputs *****************/
14790#define IS_TIM_BKIN2_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
14791
14792/************* TIM Instances : at least 1 capture/compare channel *************/
14793#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14794 ((INSTANCE) == TIM2) || \
14795 ((INSTANCE) == TIM15) || \
14796 ((INSTANCE) == TIM16))
14797
14798/************ TIM Instances : at least 2 capture/compare channels *************/
14799#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14800 ((INSTANCE) == TIM2) || \
14801 ((INSTANCE) == TIM15))
14802
14803/************ TIM Instances : at least 3 capture/compare channels *************/
14804#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14805 ((INSTANCE) == TIM2))
14806
14807/************ TIM Instances : at least 4 capture/compare channels *************/
14808#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14809 ((INSTANCE) == TIM2))
14810
14811/****************** TIM Instances : at least 5 capture/compare channels *******/
14812#define IS_TIM_CC5_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
14813
14814/****************** TIM Instances : at least 6 capture/compare channels *******/
14815#define IS_TIM_CC6_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
14816
14817/************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/
14818#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14819 ((INSTANCE) == TIM15) || \
14820 ((INSTANCE) == TIM16))
14821
14822/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/
14823#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14824 ((INSTANCE) == TIM2) || \
14825 ((INSTANCE) == TIM6) || \
14826 ((INSTANCE) == TIM7) || \
14827 ((INSTANCE) == TIM15) || \
14828 ((INSTANCE) == TIM16))
14829
14830/************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/
14831#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14832 ((INSTANCE) == TIM2) || \
14833 ((INSTANCE) == TIM15) || \
14834 ((INSTANCE) == TIM16))
14835
14836/******************** TIM Instances : DMA burst feature ***********************/
14837#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14838 ((INSTANCE) == TIM2) || \
14839 ((INSTANCE) == TIM15) || \
14840 ((INSTANCE) == TIM16))
14841
14842/******************* TIM Instances : output(s) available **********************/
14843#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
14844 ((((INSTANCE) == TIM1) && \
14845 (((CHANNEL) == TIM_CHANNEL_1) || \
14846 ((CHANNEL) == TIM_CHANNEL_2) || \
14847 ((CHANNEL) == TIM_CHANNEL_3) || \
14848 ((CHANNEL) == TIM_CHANNEL_4) || \
14849 ((CHANNEL) == TIM_CHANNEL_5) || \
14850 ((CHANNEL) == TIM_CHANNEL_6))) \
14851 || \
14852 (((INSTANCE) == TIM2) && \
14853 (((CHANNEL) == TIM_CHANNEL_1) || \
14854 ((CHANNEL) == TIM_CHANNEL_2) || \
14855 ((CHANNEL) == TIM_CHANNEL_3) || \
14856 ((CHANNEL) == TIM_CHANNEL_4))) \
14857 || \
14858 (((INSTANCE) == TIM15) && \
14859 (((CHANNEL) == TIM_CHANNEL_1) || \
14860 ((CHANNEL) == TIM_CHANNEL_2))) \
14861 || \
14862 (((INSTANCE) == TIM16) && \
14863 (((CHANNEL) == TIM_CHANNEL_1))))
14864
14865/****************** TIM Instances : supporting complementary output(s) ********/
14866#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
14867 ((((INSTANCE) == TIM1) && \
14868 (((CHANNEL) == TIM_CHANNEL_1) || \
14869 ((CHANNEL) == TIM_CHANNEL_2) || \
14870 ((CHANNEL) == TIM_CHANNEL_3))) \
14871 || \
14872 (((INSTANCE) == TIM15) && \
14873 ((CHANNEL) == TIM_CHANNEL_1)) \
14874 || \
14875 (((INSTANCE) == TIM16) && \
14876 ((CHANNEL) == TIM_CHANNEL_1)))
14877
14878/****************** TIM Instances : supporting clock division *****************/
14879#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14880 ((INSTANCE) == TIM2) || \
14881 ((INSTANCE) == TIM15) || \
14882 ((INSTANCE) == TIM16))
14883
14884/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
14885#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14886 ((INSTANCE) == TIM2) || \
14887 ((INSTANCE) == TIM15))
14888
14889/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
14890#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14891 ((INSTANCE) == TIM2))
14892
14893/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
14894#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14895 ((INSTANCE) == TIM2) || \
14896 ((INSTANCE) == TIM15))
14897
14898/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
14899#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14900 ((INSTANCE) == TIM2) || \
14901 ((INSTANCE) == TIM15))
14902
14903/****************** TIM Instances : supporting combined 3-phase PWM mode ******/
14904#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
14905
14906/****************** TIM Instances : supporting commutation event generation ***/
14907#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14908 ((INSTANCE) == TIM15) || \
14909 ((INSTANCE) == TIM16))
14910
14911/****************** TIM Instances : supporting counting mode selection ********/
14912#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14913 ((INSTANCE) == TIM2))
14914
14915/****************** TIM Instances : supporting encoder interface **************/
14916#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14917 ((INSTANCE) == TIM2))
14918
14919/****************** TIM Instances : supporting Hall sensor interface **********/
14920#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14921 ((INSTANCE) == TIM2))
14922
14923/**************** TIM Instances : external trigger input available ************/
14924#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14925 ((INSTANCE) == TIM2))
14926
14927/************* TIM Instances : supporting ETR source selection ***************/
14928#define IS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14929 ((INSTANCE) == TIM2))
14930
14931/****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/
14932#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14933 ((INSTANCE) == TIM2) || \
14934 ((INSTANCE) == TIM6) || \
14935 ((INSTANCE) == TIM7) || \
14936 ((INSTANCE) == TIM15))
14937
14938/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
14939#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14940 ((INSTANCE) == TIM2) || \
14941 ((INSTANCE) == TIM15))
14942
14943/****************** TIM Instances : supporting OCxREF clear *******************/
14944#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14945 ((INSTANCE) == TIM2))
14946
14947/****************** TIM Instances : remapping capability **********************/
14948#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14949 ((INSTANCE) == TIM2) || \
14950 ((INSTANCE) == TIM15) || \
14951 ((INSTANCE) == TIM16))
14952
14953/****************** TIM Instances : supporting repetition counter *************/
14954#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14955 ((INSTANCE) == TIM15) || \
14956 ((INSTANCE) == TIM16))
14957
14958/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
14959#define IS_TIM_TRGO2_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
14960
14961/******************* TIM Instances : Timer input XOR function *****************/
14962#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14963 ((INSTANCE) == TIM2) || \
14964 ((INSTANCE) == TIM15))
14965
14966/****************** TIM Instances : Advanced timer instances *******************/
14967#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
14968
14969/****************************** TSC Instances *********************************/
14970#define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
14971
14972/******************** USART Instances : Synchronous mode **********************/
14973#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
14974 ((INSTANCE) == USART2) || \
14975 ((INSTANCE) == USART3))
14976
14977/******************** UART Instances : Asynchronous mode **********************/
14978#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
14979 ((INSTANCE) == USART2) || \
14980 ((INSTANCE) == USART3))
14981
14982/****************** UART Instances : Auto Baud Rate detection ****************/
14983#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
14984 ((INSTANCE) == USART2) || \
14985 ((INSTANCE) == USART3))
14986
14987/****************** UART Instances : Driver Enable *****************/
14988#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
14989 ((INSTANCE) == USART2) || \
14990 ((INSTANCE) == USART3) || \
14991 ((INSTANCE) == LPUART1))
14992
14993/******************** UART Instances : Half-Duplex mode **********************/
14994#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
14995 ((INSTANCE) == USART2) || \
14996 ((INSTANCE) == USART3) || \
14997 ((INSTANCE) == LPUART1))
14998
14999/****************** UART Instances : Hardware Flow control ********************/
15000#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15001 ((INSTANCE) == USART2) || \
15002 ((INSTANCE) == USART3) || \
15003 ((INSTANCE) == LPUART1))
15004
15005/******************** UART Instances : LIN mode **********************/
15006#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15007 ((INSTANCE) == USART2) || \
15008 ((INSTANCE) == USART3))
15009
15010/******************** UART Instances : Wake-up from Stop mode **********************/
15011#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15012 ((INSTANCE) == USART2) || \
15013 ((INSTANCE) == USART3) || \
15014 ((INSTANCE) == LPUART1))
15015
15016/*********************** UART Instances : IRDA mode ***************************/
15017#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15018 ((INSTANCE) == USART2) || \
15019 ((INSTANCE) == USART3))
15020
15021/********************* USART Instances : Smard card mode ***********************/
15022#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15023 ((INSTANCE) == USART2) || \
15024 ((INSTANCE) == USART3))
15025
15026/******************** LPUART Instance *****************************************/
15027#define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)
15028
15029/****************************** IWDG Instances ********************************/
15030#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
15031
15032/****************************** WWDG Instances ********************************/
15033#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
15034
15040/******************************************************************************/
15041/* For a painless codes migration between the STM32L4xx device product */
15042/* lines, the aliases defined below are put in place to overcome the */
15043/* differences in the interrupt handlers and IRQn definitions. */
15044/* No need to update developed interrupt code when moving across */
15045/* product lines within the same STM32L4 Family */
15046/******************************************************************************/
15047
15048/* Aliases for __IRQn */
15049#define TIM6_IRQn TIM6_DAC_IRQn
15050#define ADC1_2_IRQn ADC1_IRQn
15051#define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_IRQn
15052#define HASH_RNG_IRQn RNG_IRQn
15053#define HASH_CRS_IRQn CRS_IRQn
15054
15055/* Aliases for __IRQHandler */
15056#define TIM6_IRQHandler TIM6_DAC_IRQHandler
15057#define ADC1_2_IRQHandler ADC1_IRQHandler
15058#define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_IRQHandler
15059#define HASH_RNG_IRQHandler RNG_IRQHandler
15060#define HASH_CRS_IRQHandler CRS_IRQHandler
15061
15062#ifdef __cplusplus
15063}
15064#endif /* __cplusplus */
15065
15066#endif /* __STM32L431xx_H */
15067
__IO
#define __IO
Definition core_armv81mml.h:277
__I
#define __I
Definition core_armv81mml.h:274
core_cm4.h
CMSIS Cortex-M4 Core Peripheral Access Layer Header File
IRQn_Type
IRQn_Type
STM32L4XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition stm32l431xx.h:66
CRS_IRQn
@ CRS_IRQn
Definition stm32l431xx.h:141
PendSV_IRQn
@ PendSV_IRQn
Definition stm32l431xx.h:75
EXTI2_IRQn
@ EXTI2_IRQn
Definition stm32l431xx.h:86
DMA2_Channel4_IRQn
@ DMA2_Channel4_IRQn
Definition stm32l431xx.h:125
CAN1_SCE_IRQn
@ CAN1_SCE_IRQn
Definition stm32l431xx.h:100
RTC_WKUP_IRQn
@ RTC_WKUP_IRQn
Definition stm32l431xx.h:81
DMA1_Channel2_IRQn
@ DMA1_Channel2_IRQn
Definition stm32l431xx.h:90
I2C1_ER_IRQn
@ I2C1_ER_IRQn
Definition stm32l431xx.h:108
I2C2_EV_IRQn
@ I2C2_EV_IRQn
Definition stm32l431xx.h:109
MemoryManagement_IRQn
@ MemoryManagement_IRQn
Definition stm32l431xx.h:70
ADC1_IRQn
@ ADC1_IRQn
Definition stm32l431xx.h:96
SAI1_IRQn
@ SAI1_IRQn
Definition stm32l431xx.h:136
TIM2_IRQn
@ TIM2_IRQn
Definition stm32l431xx.h:106
DMA1_Channel1_IRQn
@ DMA1_Channel1_IRQn
Definition stm32l431xx.h:89
DMA1_Channel3_IRQn
@ DMA1_Channel3_IRQn
Definition stm32l431xx.h:91
USART2_IRQn
@ USART2_IRQn
Definition stm32l431xx.h:114
DMA2_Channel7_IRQn
@ DMA2_Channel7_IRQn
Definition stm32l431xx.h:131
SVCall_IRQn
@ SVCall_IRQn
Definition stm32l431xx.h:73
SPI3_IRQn
@ SPI3_IRQn
Definition stm32l431xx.h:119
SPI2_IRQn
@ SPI2_IRQn
Definition stm32l431xx.h:112
TIM7_IRQn
@ TIM7_IRQn
Definition stm32l431xx.h:121
RCC_IRQn
@ RCC_IRQn
Definition stm32l431xx.h:83
LPTIM2_IRQn
@ LPTIM2_IRQn
Definition stm32l431xx.h:129
TIM6_DAC_IRQn
@ TIM6_DAC_IRQn
Definition stm32l431xx.h:120
I2C2_ER_IRQn
@ I2C2_ER_IRQn
Definition stm32l431xx.h:110
QUADSPI_IRQn
@ QUADSPI_IRQn
Definition stm32l431xx.h:133
DMA1_Channel7_IRQn
@ DMA1_Channel7_IRQn
Definition stm32l431xx.h:95
UsageFault_IRQn
@ UsageFault_IRQn
Definition stm32l431xx.h:72
SysTick_IRQn
@ SysTick_IRQn
Definition stm32l431xx.h:76
I2C3_ER_IRQn
@ I2C3_ER_IRQn
Definition stm32l431xx.h:135
I2C3_EV_IRQn
@ I2C3_EV_IRQn
Definition stm32l431xx.h:134
BusFault_IRQn
@ BusFault_IRQn
Definition stm32l431xx.h:71
DMA2_Channel6_IRQn
@ DMA2_Channel6_IRQn
Definition stm32l431xx.h:130
TIM1_BRK_TIM15_IRQn
@ TIM1_BRK_TIM15_IRQn
Definition stm32l431xx.h:102
DebugMonitor_IRQn
@ DebugMonitor_IRQn
Definition stm32l431xx.h:74
RNG_IRQn
@ RNG_IRQn
Definition stm32l431xx.h:139
FLASH_IRQn
@ FLASH_IRQn
Definition stm32l431xx.h:82
SWPMI1_IRQn
@ SWPMI1_IRQn
Definition stm32l431xx.h:137
WWDG_IRQn
@ WWDG_IRQn
Definition stm32l431xx.h:78
I2C1_EV_IRQn
@ I2C1_EV_IRQn
Definition stm32l431xx.h:107
CAN1_TX_IRQn
@ CAN1_TX_IRQn
Definition stm32l431xx.h:97
SDMMC1_IRQn
@ SDMMC1_IRQn
Definition stm32l431xx.h:118
EXTI15_10_IRQn
@ EXTI15_10_IRQn
Definition stm32l431xx.h:116
EXTI9_5_IRQn
@ EXTI9_5_IRQn
Definition stm32l431xx.h:101
LPTIM1_IRQn
@ LPTIM1_IRQn
Definition stm32l431xx.h:128
FPU_IRQn
@ FPU_IRQn
Definition stm32l431xx.h:140
DMA1_Channel6_IRQn
@ DMA1_Channel6_IRQn
Definition stm32l431xx.h:94
SPI1_IRQn
@ SPI1_IRQn
Definition stm32l431xx.h:111
HardFault_IRQn
@ HardFault_IRQn
Definition stm32l431xx.h:69
EXTI0_IRQn
@ EXTI0_IRQn
Definition stm32l431xx.h:84
CAN1_RX0_IRQn
@ CAN1_RX0_IRQn
Definition stm32l431xx.h:98
EXTI4_IRQn
@ EXTI4_IRQn
Definition stm32l431xx.h:88
DMA2_Channel1_IRQn
@ DMA2_Channel1_IRQn
Definition stm32l431xx.h:122
DMA1_Channel5_IRQn
@ DMA1_Channel5_IRQn
Definition stm32l431xx.h:93
TAMP_STAMP_IRQn
@ TAMP_STAMP_IRQn
Definition stm32l431xx.h:80
DMA2_Channel5_IRQn
@ DMA2_Channel5_IRQn
Definition stm32l431xx.h:126
TIM1_TRG_COM_IRQn
@ TIM1_TRG_COM_IRQn
Definition stm32l431xx.h:104
DMA2_Channel2_IRQn
@ DMA2_Channel2_IRQn
Definition stm32l431xx.h:123
TIM1_UP_TIM16_IRQn
@ TIM1_UP_TIM16_IRQn
Definition stm32l431xx.h:103
USART1_IRQn
@ USART1_IRQn
Definition stm32l431xx.h:113
COMP_IRQn
@ COMP_IRQn
Definition stm32l431xx.h:127
DMA2_Channel3_IRQn
@ DMA2_Channel3_IRQn
Definition stm32l431xx.h:124
EXTI3_IRQn
@ EXTI3_IRQn
Definition stm32l431xx.h:87
NonMaskableInt_IRQn
@ NonMaskableInt_IRQn
Definition stm32l431xx.h:68
PVD_PVM_IRQn
@ PVD_PVM_IRQn
Definition stm32l431xx.h:79
DMA1_Channel4_IRQn
@ DMA1_Channel4_IRQn
Definition stm32l431xx.h:92
EXTI1_IRQn
@ EXTI1_IRQn
Definition stm32l431xx.h:85
TIM1_CC_IRQn
@ TIM1_CC_IRQn
Definition stm32l431xx.h:105
LPUART1_IRQn
@ LPUART1_IRQn
Definition stm32l431xx.h:132
CAN1_RX1_IRQn
@ CAN1_RX1_IRQn
Definition stm32l431xx.h:99
USART3_IRQn
@ USART3_IRQn
Definition stm32l431xx.h:115
TSC_IRQn
@ TSC_IRQn
Definition stm32l431xx.h:138
RTC_Alarm_IRQn
@ RTC_Alarm_IRQn
Definition stm32l431xx.h:117
ADC_Common_TypeDef
Definition stm32l431xx.h:203
ADC_Common_TypeDef::RESERVED2
uint32_t RESERVED2
Definition stm32l431xx.h:205
ADC_Common_TypeDef::CCR
__IO uint32_t CCR
Definition stm32l431xx.h:206
ADC_Common_TypeDef::RESERVED1
uint32_t RESERVED1
Definition stm32l431xx.h:204
ADC_Common_TypeDef::RESERVED3
uint32_t RESERVED3
Definition stm32l431xx.h:207
ADC_TypeDef
Analog to Digital Converter
Definition stm32l431xx.h:161
ADC_TypeDef::JDR1
__IO uint32_t JDR1
Definition stm32l431xx.h:188
ADC_TypeDef::CFGR
__IO uint32_t CFGR
Definition stm32l431xx.h:165
ADC_TypeDef::TR2
__IO uint32_t TR2
Definition stm32l431xx.h:171
ADC_TypeDef::SQR1
__IO uint32_t SQR1
Definition stm32l431xx.h:174
ADC_TypeDef::JDR3
__IO uint32_t JDR3
Definition stm32l431xx.h:190
ADC_TypeDef::DR
__IO uint32_t DR
Definition stm32l431xx.h:178
ADC_TypeDef::OFR1
__IO uint32_t OFR1
Definition stm32l431xx.h:183
ADC_TypeDef::RESERVED2
uint32_t RESERVED2
Definition stm32l431xx.h:173
ADC_TypeDef::IER
__IO uint32_t IER
Definition stm32l431xx.h:163
ADC_TypeDef::OFR3
__IO uint32_t OFR3
Definition stm32l431xx.h:185
ADC_TypeDef::SMPR2
__IO uint32_t SMPR2
Definition stm32l431xx.h:168
ADC_TypeDef::JSQR
__IO uint32_t JSQR
Definition stm32l431xx.h:181
ADC_TypeDef::OFR2
__IO uint32_t OFR2
Definition stm32l431xx.h:184
ADC_TypeDef::TR1
__IO uint32_t TR1
Definition stm32l431xx.h:170
ADC_TypeDef::JDR4
__IO uint32_t JDR4
Definition stm32l431xx.h:191
ADC_TypeDef::SQR4
__IO uint32_t SQR4
Definition stm32l431xx.h:177
ADC_TypeDef::SQR3
__IO uint32_t SQR3
Definition stm32l431xx.h:176
ADC_TypeDef::SQR2
__IO uint32_t SQR2
Definition stm32l431xx.h:175
ADC_TypeDef::AWD3CR
__IO uint32_t AWD3CR
Definition stm32l431xx.h:194
ADC_TypeDef::ISR
__IO uint32_t ISR
Definition stm32l431xx.h:162
ADC_TypeDef::CR
__IO uint32_t CR
Definition stm32l431xx.h:164
ADC_TypeDef::CALFACT
__IO uint32_t CALFACT
Definition stm32l431xx.h:198
ADC_TypeDef::RESERVED4
uint32_t RESERVED4
Definition stm32l431xx.h:180
ADC_TypeDef::RESERVED1
uint32_t RESERVED1
Definition stm32l431xx.h:169
ADC_TypeDef::CFGR2
__IO uint32_t CFGR2
Definition stm32l431xx.h:166
ADC_TypeDef::RESERVED9
uint32_t RESERVED9
Definition stm32l431xx.h:196
ADC_TypeDef::DIFSEL
__IO uint32_t DIFSEL
Definition stm32l431xx.h:197
ADC_TypeDef::JDR2
__IO uint32_t JDR2
Definition stm32l431xx.h:189
ADC_TypeDef::AWD2CR
__IO uint32_t AWD2CR
Definition stm32l431xx.h:193
ADC_TypeDef::RESERVED3
uint32_t RESERVED3
Definition stm32l431xx.h:179
ADC_TypeDef::TR3
__IO uint32_t TR3
Definition stm32l431xx.h:172
ADC_TypeDef::RESERVED8
uint32_t RESERVED8
Definition stm32l431xx.h:195
ADC_TypeDef::SMPR1
__IO uint32_t SMPR1
Definition stm32l431xx.h:167
ADC_TypeDef::OFR4
__IO uint32_t OFR4
Definition stm32l431xx.h:186
CAN_FIFOMailBox_TypeDef
Controller Area Network FIFOMailBox
Definition stm32l431xx.h:228
CAN_FIFOMailBox_TypeDef::RIR
__IO uint32_t RIR
Definition stm32l431xx.h:229
CAN_FIFOMailBox_TypeDef::RDHR
__IO uint32_t RDHR
Definition stm32l431xx.h:232
CAN_FIFOMailBox_TypeDef::RDTR
__IO uint32_t RDTR
Definition stm32l431xx.h:230
CAN_FIFOMailBox_TypeDef::RDLR
__IO uint32_t RDLR
Definition stm32l431xx.h:231
CAN_FilterRegister_TypeDef
Controller Area Network FilterRegister
Definition stm32l431xx.h:240
CAN_FilterRegister_TypeDef::FR2
__IO uint32_t FR2
Definition stm32l431xx.h:242
CAN_FilterRegister_TypeDef::FR1
__IO uint32_t FR1
Definition stm32l431xx.h:241
CAN_TxMailBox_TypeDef
Controller Area Network TxMailBox
Definition stm32l431xx.h:216
CAN_TxMailBox_TypeDef::TIR
__IO uint32_t TIR
Definition stm32l431xx.h:217
CAN_TxMailBox_TypeDef::TDHR
__IO uint32_t TDHR
Definition stm32l431xx.h:220
CAN_TxMailBox_TypeDef::TDLR
__IO uint32_t TDLR
Definition stm32l431xx.h:219
CAN_TxMailBox_TypeDef::TDTR
__IO uint32_t TDTR
Definition stm32l431xx.h:218
CAN_TypeDef
Controller Area Network
Definition stm32l431xx.h:250
CAN_TypeDef::RF1R
__IO uint32_t RF1R
Definition stm32l431xx.h:255
CAN_TypeDef::FMR
__IO uint32_t FMR
Definition stm32l431xx.h:263
CAN_TypeDef::MCR
__IO uint32_t MCR
Definition stm32l431xx.h:251
CAN_TypeDef::ESR
__IO uint32_t ESR
Definition stm32l431xx.h:257
CAN_TypeDef::RESERVED2
uint32_t RESERVED2
Definition stm32l431xx.h:265
CAN_TypeDef::BTR
__IO uint32_t BTR
Definition stm32l431xx.h:258
CAN_TypeDef::IER
__IO uint32_t IER
Definition stm32l431xx.h:256
CAN_TypeDef::TSR
__IO uint32_t TSR
Definition stm32l431xx.h:253
CAN_TypeDef::FM1R
__IO uint32_t FM1R
Definition stm32l431xx.h:264
CAN_TypeDef::FS1R
__IO uint32_t FS1R
Definition stm32l431xx.h:266
CAN_TypeDef::FA1R
__IO uint32_t FA1R
Definition stm32l431xx.h:270
CAN_TypeDef::RESERVED4
uint32_t RESERVED4
Definition stm32l431xx.h:269
CAN_TypeDef::RF0R
__IO uint32_t RF0R
Definition stm32l431xx.h:254
CAN_TypeDef::MSR
__IO uint32_t MSR
Definition stm32l431xx.h:252
CAN_TypeDef::FFA1R
__IO uint32_t FFA1R
Definition stm32l431xx.h:268
CAN_TypeDef::RESERVED3
uint32_t RESERVED3
Definition stm32l431xx.h:267
COMP_Common_TypeDef
Definition stm32l431xx.h:286
COMP_Common_TypeDef::CSR
__IO uint32_t CSR
Definition stm32l431xx.h:287
COMP_TypeDef
Comparator
Definition stm32l431xx.h:281
COMP_TypeDef::CSR
__IO uint32_t CSR
Definition stm32l431xx.h:282
CRC_TypeDef
CRC calculation unit
Definition stm32l431xx.h:295
CRC_TypeDef::DR
__IO uint32_t DR
Definition stm32l431xx.h:296
CRC_TypeDef::RESERVED2
uint32_t RESERVED2
Definition stm32l431xx.h:301
CRC_TypeDef::IDR
__IO uint8_t IDR
Definition stm32l431xx.h:297
CRC_TypeDef::RESERVED1
uint16_t RESERVED1
Definition stm32l431xx.h:299
CRC_TypeDef::POL
__IO uint32_t POL
Definition stm32l431xx.h:303
CRC_TypeDef::RESERVED0
uint8_t RESERVED0
Definition stm32l431xx.h:298
CRC_TypeDef::CR
__IO uint32_t CR
Definition stm32l431xx.h:300
CRC_TypeDef::INIT
__IO uint32_t INIT
Definition stm32l431xx.h:302
CRS_TypeDef
Clock Recovery System
Definition stm32l431xx.h:310
CRS_TypeDef::ICR
__IO uint32_t ICR
Definition stm32l431xx.h:314
CRS_TypeDef::CFGR
__IO uint32_t CFGR
Definition stm32l431xx.h:312
CRS_TypeDef::ISR
__IO uint32_t ISR
Definition stm32l431xx.h:313
CRS_TypeDef::CR
__IO uint32_t CR
Definition stm32l431xx.h:311
DAC_TypeDef
Digital to Analog Converter
Definition stm32l431xx.h:322
DAC_TypeDef::SHRR
__IO uint32_t SHRR
Definition stm32l431xx.h:342
DAC_TypeDef::DHR12RD
__IO uint32_t DHR12RD
Definition stm32l431xx.h:331
DAC_TypeDef::MCR
__IO uint32_t MCR
Definition stm32l431xx.h:338
DAC_TypeDef::DHR12L2
__IO uint32_t DHR12L2
Definition stm32l431xx.h:329
DAC_TypeDef::SHSR2
__IO uint32_t SHSR2
Definition stm32l431xx.h:340
DAC_TypeDef::SHSR1
__IO uint32_t SHSR1
Definition stm32l431xx.h:339
DAC_TypeDef::SHHR
__IO uint32_t SHHR
Definition stm32l431xx.h:341
DAC_TypeDef::DHR8R2
__IO uint32_t DHR8R2
Definition stm32l431xx.h:330
DAC_TypeDef::CCR
__IO uint32_t CCR
Definition stm32l431xx.h:337
DAC_TypeDef::DHR12R2
__IO uint32_t DHR12R2
Definition stm32l431xx.h:328
DAC_TypeDef::SWTRIGR
__IO uint32_t SWTRIGR
Definition stm32l431xx.h:324
DAC_TypeDef::DHR8RD
__IO uint32_t DHR8RD
Definition stm32l431xx.h:333
DAC_TypeDef::DOR1
__IO uint32_t DOR1
Definition stm32l431xx.h:334
DAC_TypeDef::CR
__IO uint32_t CR
Definition stm32l431xx.h:323
DAC_TypeDef::DOR2
__IO uint32_t DOR2
Definition stm32l431xx.h:335
DAC_TypeDef::DHR12R1
__IO uint32_t DHR12R1
Definition stm32l431xx.h:325
DAC_TypeDef::DHR12LD
__IO uint32_t DHR12LD
Definition stm32l431xx.h:332
DAC_TypeDef::DHR8R1
__IO uint32_t DHR8R1
Definition stm32l431xx.h:327
DAC_TypeDef::DHR12L1
__IO uint32_t DHR12L1
Definition stm32l431xx.h:326
DAC_TypeDef::SR
__IO uint32_t SR
Definition stm32l431xx.h:336
DBGMCU_TypeDef
Debug MCU
Definition stm32l431xx.h:351
DBGMCU_TypeDef::IDCODE
__IO uint32_t IDCODE
Definition stm32l431xx.h:352
DBGMCU_TypeDef::APB1FZR1
__IO uint32_t APB1FZR1
Definition stm32l431xx.h:354
DBGMCU_TypeDef::APB2FZ
__IO uint32_t APB2FZ
Definition stm32l431xx.h:356
DBGMCU_TypeDef::CR
__IO uint32_t CR
Definition stm32l431xx.h:353
DBGMCU_TypeDef::APB1FZR2
__IO uint32_t APB1FZR2
Definition stm32l431xx.h:355
DMA_Channel_TypeDef
DMA Controller
Definition stm32l431xx.h:365
DMA_Channel_TypeDef::CPAR
__IO uint32_t CPAR
Definition stm32l431xx.h:368
DMA_Channel_TypeDef::CCR
__IO uint32_t CCR
Definition stm32l431xx.h:366
DMA_Channel_TypeDef::CNDTR
__IO uint32_t CNDTR
Definition stm32l431xx.h:367
DMA_Channel_TypeDef::CMAR
__IO uint32_t CMAR
Definition stm32l431xx.h:369
DMA_Request_TypeDef
Definition stm32l431xx.h:379
DMA_Request_TypeDef::CSELR
__IO uint32_t CSELR
Definition stm32l431xx.h:380
DMA_TypeDef
Definition stm32l431xx.h:373
DMA_TypeDef::ISR
__IO uint32_t ISR
Definition stm32l431xx.h:374
DMA_TypeDef::IFCR
__IO uint32_t IFCR
Definition stm32l431xx.h:375
EXTI_TypeDef
External Interrupt/Event Controller
Definition stm32l431xx.h:392
EXTI_TypeDef::RTSR2
__IO uint32_t RTSR2
Definition stm32l431xx.h:403
EXTI_TypeDef::SWIER2
__IO uint32_t SWIER2
Definition stm32l431xx.h:405
EXTI_TypeDef::SWIER1
__IO uint32_t SWIER1
Definition stm32l431xx.h:397
EXTI_TypeDef::EMR2
__IO uint32_t EMR2
Definition stm32l431xx.h:402
EXTI_TypeDef::EMR1
__IO uint32_t EMR1
Definition stm32l431xx.h:394
EXTI_TypeDef::PR1
__IO uint32_t PR1
Definition stm32l431xx.h:398
EXTI_TypeDef::RESERVED2
uint32_t RESERVED2
Definition stm32l431xx.h:400
EXTI_TypeDef::FTSR2
__IO uint32_t FTSR2
Definition stm32l431xx.h:404
EXTI_TypeDef::IMR2
__IO uint32_t IMR2
Definition stm32l431xx.h:401
EXTI_TypeDef::IMR1
__IO uint32_t IMR1
Definition stm32l431xx.h:393
EXTI_TypeDef::RTSR1
__IO uint32_t RTSR1
Definition stm32l431xx.h:395
EXTI_TypeDef::RESERVED1
uint32_t RESERVED1
Definition stm32l431xx.h:399
EXTI_TypeDef::FTSR1
__IO uint32_t FTSR1
Definition stm32l431xx.h:396
EXTI_TypeDef::PR2
__IO uint32_t PR2
Definition stm32l431xx.h:406
FIREWALL_TypeDef
Firewall
Definition stm32l431xx.h:415
FIREWALL_TypeDef::CSL
__IO uint32_t CSL
Definition stm32l431xx.h:417
FIREWALL_TypeDef::NVDSL
__IO uint32_t NVDSL
Definition stm32l431xx.h:419
FIREWALL_TypeDef::RESERVED2
uint32_t RESERVED2
Definition stm32l431xx.h:423
FIREWALL_TypeDef::VDSL
__IO uint32_t VDSL
Definition stm32l431xx.h:421
FIREWALL_TypeDef::CR
__IO uint32_t CR
Definition stm32l431xx.h:424
FIREWALL_TypeDef::RESERVED1
uint32_t RESERVED1
Definition stm32l431xx.h:422
FIREWALL_TypeDef::NVDSSA
__IO uint32_t NVDSSA
Definition stm32l431xx.h:418
FIREWALL_TypeDef::VDSSA
__IO uint32_t VDSSA
Definition stm32l431xx.h:420
FIREWALL_TypeDef::CSSA
__IO uint32_t CSSA
Definition stm32l431xx.h:416
FLASH_TypeDef
FLASH Registers
Definition stm32l431xx.h:433
FLASH_TypeDef::OPTR
__IO uint32_t OPTR
Definition stm32l431xx.h:442
FLASH_TypeDef::RESERVED1
__IO uint32_t RESERVED1
Definition stm32l431xx.h:441
FLASH_TypeDef::WRP1AR
__IO uint32_t WRP1AR
Definition stm32l431xx.h:445
FLASH_TypeDef::WRP1BR
__IO uint32_t WRP1BR
Definition stm32l431xx.h:446
FLASH_TypeDef::KEYR
__IO uint32_t KEYR
Definition stm32l431xx.h:436
FLASH_TypeDef::ACR
__IO uint32_t ACR
Definition stm32l431xx.h:434
FLASH_TypeDef::PCROP1SR
__IO uint32_t PCROP1SR
Definition stm32l431xx.h:443
FLASH_TypeDef::PCROP1ER
__IO uint32_t PCROP1ER
Definition stm32l431xx.h:444
FLASH_TypeDef::PDKEYR
__IO uint32_t PDKEYR
Definition stm32l431xx.h:435
FLASH_TypeDef::CR
__IO uint32_t CR
Definition stm32l431xx.h:439
FLASH_TypeDef::ECCR
__IO uint32_t ECCR
Definition stm32l431xx.h:440
FLASH_TypeDef::SR
__IO uint32_t SR
Definition stm32l431xx.h:438
FLASH_TypeDef::OPTKEYR
__IO uint32_t OPTKEYR
Definition stm32l431xx.h:437
GPIO_TypeDef
General Purpose I/O
Definition stm32l431xx.h:456
GPIO_TypeDef::BRR
__IO uint32_t BRR
Definition stm32l431xx.h:466
GPIO_TypeDef::LCKR
__IO uint32_t LCKR
Definition stm32l431xx.h:464
GPIO_TypeDef::MODER
__IO uint32_t MODER
Definition stm32l431xx.h:457
GPIO_TypeDef::OSPEEDR
__IO uint32_t OSPEEDR
Definition stm32l431xx.h:459
GPIO_TypeDef::IDR
__IO uint32_t IDR
Definition stm32l431xx.h:461
GPIO_TypeDef::OTYPER
__IO uint32_t OTYPER
Definition stm32l431xx.h:458
GPIO_TypeDef::PUPDR
__IO uint32_t PUPDR
Definition stm32l431xx.h:460
GPIO_TypeDef::ODR
__IO uint32_t ODR
Definition stm32l431xx.h:462
GPIO_TypeDef::BSRR
__IO uint32_t BSRR
Definition stm32l431xx.h:463
I2C_TypeDef
Inter-integrated Circuit Interface
Definition stm32l431xx.h:476
I2C_TypeDef::OAR1
__IO uint32_t OAR1
Definition stm32l431xx.h:479
I2C_TypeDef::ICR
__IO uint32_t ICR
Definition stm32l431xx.h:484
I2C_TypeDef::TIMINGR
__IO uint32_t TIMINGR
Definition stm32l431xx.h:481
I2C_TypeDef::TIMEOUTR
__IO uint32_t TIMEOUTR
Definition stm32l431xx.h:482
I2C_TypeDef::RXDR
__IO uint32_t RXDR
Definition stm32l431xx.h:486
I2C_TypeDef::CR1
__IO uint32_t CR1
Definition stm32l431xx.h:477
I2C_TypeDef::ISR
__IO uint32_t ISR
Definition stm32l431xx.h:483
I2C_TypeDef::OAR2
__IO uint32_t OAR2
Definition stm32l431xx.h:480
I2C_TypeDef::TXDR
__IO uint32_t TXDR
Definition stm32l431xx.h:487
I2C_TypeDef::PECR
__IO uint32_t PECR
Definition stm32l431xx.h:485
I2C_TypeDef::CR2
__IO uint32_t CR2
Definition stm32l431xx.h:478
IWDG_TypeDef
Independent WATCHDOG
Definition stm32l431xx.h:495
IWDG_TypeDef::KR
__IO uint32_t KR
Definition stm32l431xx.h:496
IWDG_TypeDef::RLR
__IO uint32_t RLR
Definition stm32l431xx.h:498
IWDG_TypeDef::WINR
__IO uint32_t WINR
Definition stm32l431xx.h:500
IWDG_TypeDef::SR
__IO uint32_t SR
Definition stm32l431xx.h:499
IWDG_TypeDef::PR
__IO uint32_t PR
Definition stm32l431xx.h:497
LPTIM_TypeDef
LPTIMER
Definition stm32l431xx.h:507
LPTIM_TypeDef::ICR
__IO uint32_t ICR
Definition stm32l431xx.h:509
LPTIM_TypeDef::CMP
__IO uint32_t CMP
Definition stm32l431xx.h:513
LPTIM_TypeDef::CFGR
__IO uint32_t CFGR
Definition stm32l431xx.h:511
LPTIM_TypeDef::CNT
__IO uint32_t CNT
Definition stm32l431xx.h:515
LPTIM_TypeDef::IER
__IO uint32_t IER
Definition stm32l431xx.h:510
LPTIM_TypeDef::OR
__IO uint32_t OR
Definition stm32l431xx.h:516
LPTIM_TypeDef::ISR
__IO uint32_t ISR
Definition stm32l431xx.h:508
LPTIM_TypeDef::CR
__IO uint32_t CR
Definition stm32l431xx.h:512
LPTIM_TypeDef::ARR
__IO uint32_t ARR
Definition stm32l431xx.h:514
OPAMP_Common_TypeDef
Definition stm32l431xx.h:531
OPAMP_Common_TypeDef::CSR
__IO uint32_t CSR
Definition stm32l431xx.h:532
OPAMP_TypeDef
Operational Amplifier (OPAMP)
Definition stm32l431xx.h:524
OPAMP_TypeDef::CSR
__IO uint32_t CSR
Definition stm32l431xx.h:525
OPAMP_TypeDef::LPOTR
__IO uint32_t LPOTR
Definition stm32l431xx.h:527
OPAMP_TypeDef::OTR
__IO uint32_t OTR
Definition stm32l431xx.h:526
PWR_TypeDef
Power Control
Definition stm32l431xx.h:540
PWR_TypeDef::PDCRD
__IO uint32_t PDCRD
Definition stm32l431xx.h:556
PWR_TypeDef::RESERVED
uint32_t RESERVED
Definition stm32l431xx.h:548
PWR_TypeDef::PDCRB
__IO uint32_t PDCRB
Definition stm32l431xx.h:552
PWR_TypeDef::PDCRA
__IO uint32_t PDCRA
Definition stm32l431xx.h:550
PWR_TypeDef::PDCRH
__IO uint32_t PDCRH
Definition stm32l431xx.h:564
PWR_TypeDef::PDCRE
__IO uint32_t PDCRE
Definition stm32l431xx.h:558
PWR_TypeDef::RESERVED2
uint32_t RESERVED2
Definition stm32l431xx.h:560
PWR_TypeDef::PUCRC
__IO uint32_t PUCRC
Definition stm32l431xx.h:553
PWR_TypeDef::SCR
__IO uint32_t SCR
Definition stm32l431xx.h:547
PWR_TypeDef::PUCRH
__IO uint32_t PUCRH
Definition stm32l431xx.h:563
PWR_TypeDef::SR2
__IO uint32_t SR2
Definition stm32l431xx.h:546
PWR_TypeDef::PDCRC
__IO uint32_t PDCRC
Definition stm32l431xx.h:554
PWR_TypeDef::PUCRD
__IO uint32_t PUCRD
Definition stm32l431xx.h:555
PWR_TypeDef::CR4
__IO uint32_t CR4
Definition stm32l431xx.h:544
PWR_TypeDef::CR1
__IO uint32_t CR1
Definition stm32l431xx.h:541
PWR_TypeDef::PUCRB
__IO uint32_t PUCRB
Definition stm32l431xx.h:551
PWR_TypeDef::PUCRE
__IO uint32_t PUCRE
Definition stm32l431xx.h:557
PWR_TypeDef::RESERVED4
uint32_t RESERVED4
Definition stm32l431xx.h:562
PWR_TypeDef::RESERVED1
uint32_t RESERVED1
Definition stm32l431xx.h:559
PWR_TypeDef::SR1
__IO uint32_t SR1
Definition stm32l431xx.h:545
PWR_TypeDef::CR3
__IO uint32_t CR3
Definition stm32l431xx.h:543
PWR_TypeDef::PUCRA
__IO uint32_t PUCRA
Definition stm32l431xx.h:549
PWR_TypeDef::RESERVED3
uint32_t RESERVED3
Definition stm32l431xx.h:561
PWR_TypeDef::CR2
__IO uint32_t CR2
Definition stm32l431xx.h:542
QUADSPI_TypeDef
QUAD Serial Peripheral Interface
Definition stm32l431xx.h:573
QUADSPI_TypeDef::AR
__IO uint32_t AR
Definition stm32l431xx.h:580
QUADSPI_TypeDef::DR
__IO uint32_t DR
Definition stm32l431xx.h:582
QUADSPI_TypeDef::ABR
__IO uint32_t ABR
Definition stm32l431xx.h:581
QUADSPI_TypeDef::FCR
__IO uint32_t FCR
Definition stm32l431xx.h:577
QUADSPI_TypeDef::CCR
__IO uint32_t CCR
Definition stm32l431xx.h:579
QUADSPI_TypeDef::DLR
__IO uint32_t DLR
Definition stm32l431xx.h:578
QUADSPI_TypeDef::PSMKR
__IO uint32_t PSMKR
Definition stm32l431xx.h:583
QUADSPI_TypeDef::PSMAR
__IO uint32_t PSMAR
Definition stm32l431xx.h:584
QUADSPI_TypeDef::PIR
__IO uint32_t PIR
Definition stm32l431xx.h:585
QUADSPI_TypeDef::CR
__IO uint32_t CR
Definition stm32l431xx.h:574
QUADSPI_TypeDef::LPTR
__IO uint32_t LPTR
Definition stm32l431xx.h:586
QUADSPI_TypeDef::DCR
__IO uint32_t DCR
Definition stm32l431xx.h:575
QUADSPI_TypeDef::SR
__IO uint32_t SR
Definition stm32l431xx.h:576
RCC_TypeDef
Reset and Clock Control
Definition stm32l431xx.h:595
RCC_TypeDef::CCIPR
__IO uint32_t CCIPR
Definition stm32l431xx.h:630
RCC_TypeDef::ICSCR
__IO uint32_t ICSCR
Definition stm32l431xx.h:597
RCC_TypeDef::APB1SMENR2
__IO uint32_t APB1SMENR2
Definition stm32l431xx.h:627
RCC_TypeDef::BDCR
__IO uint32_t BDCR
Definition stm32l431xx.h:632
RCC_TypeDef::RESERVED
uint32_t RESERVED
Definition stm32l431xx.h:601
RCC_TypeDef::CIER
__IO uint32_t CIER
Definition stm32l431xx.h:602
RCC_TypeDef::AHB1ENR
__IO uint32_t AHB1ENR
Definition stm32l431xx.h:614
RCC_TypeDef::APB1RSTR1
__IO uint32_t APB1RSTR1
Definition stm32l431xx.h:610
RCC_TypeDef::CFGR
__IO uint32_t CFGR
Definition stm32l431xx.h:598
RCC_TypeDef::AHB3RSTR
__IO uint32_t AHB3RSTR
Definition stm32l431xx.h:608
RCC_TypeDef::APB2SMENR
__IO uint32_t APB2SMENR
Definition stm32l431xx.h:628
RCC_TypeDef::AHB1RSTR
__IO uint32_t AHB1RSTR
Definition stm32l431xx.h:606
RCC_TypeDef::RESERVED2
uint32_t RESERVED2
Definition stm32l431xx.h:613
RCC_TypeDef::RESERVED6
uint32_t RESERVED6
Definition stm32l431xx.h:629
RCC_TypeDef::CICR
__IO uint32_t CICR
Definition stm32l431xx.h:604
RCC_TypeDef::AHB2ENR
__IO uint32_t AHB2ENR
Definition stm32l431xx.h:615
RCC_TypeDef::APB1RSTR2
__IO uint32_t APB1RSTR2
Definition stm32l431xx.h:611
RCC_TypeDef::RESERVED7
uint32_t RESERVED7
Definition stm32l431xx.h:631
RCC_TypeDef::AHB2RSTR
__IO uint32_t AHB2RSTR
Definition stm32l431xx.h:607
RCC_TypeDef::APB1ENR1
__IO uint32_t APB1ENR1
Definition stm32l431xx.h:618
RCC_TypeDef::CRRCR
__IO uint32_t CRRCR
Definition stm32l431xx.h:634
RCC_TypeDef::CSR
__IO uint32_t CSR
Definition stm32l431xx.h:633
RCC_TypeDef::AHB3SMENR
__IO uint32_t AHB3SMENR
Definition stm32l431xx.h:624
RCC_TypeDef::AHB2SMENR
__IO uint32_t AHB2SMENR
Definition stm32l431xx.h:623
RCC_TypeDef::APB2RSTR
__IO uint32_t APB2RSTR
Definition stm32l431xx.h:612
RCC_TypeDef::CR
__IO uint32_t CR
Definition stm32l431xx.h:596
RCC_TypeDef::RESERVED4
uint32_t RESERVED4
Definition stm32l431xx.h:621
RCC_TypeDef::RESERVED1
uint32_t RESERVED1
Definition stm32l431xx.h:609
RCC_TypeDef::APB2ENR
__IO uint32_t APB2ENR
Definition stm32l431xx.h:620
RCC_TypeDef::AHB3ENR
__IO uint32_t AHB3ENR
Definition stm32l431xx.h:616
RCC_TypeDef::AHB1SMENR
__IO uint32_t AHB1SMENR
Definition stm32l431xx.h:622
RCC_TypeDef::APB1SMENR1
__IO uint32_t APB1SMENR1
Definition stm32l431xx.h:626
RCC_TypeDef::RESERVED5
uint32_t RESERVED5
Definition stm32l431xx.h:625
RCC_TypeDef::PLLCFGR
__IO uint32_t PLLCFGR
Definition stm32l431xx.h:599
RCC_TypeDef::PLLSAI1CFGR
__IO uint32_t PLLSAI1CFGR
Definition stm32l431xx.h:600
RCC_TypeDef::RESERVED3
uint32_t RESERVED3
Definition stm32l431xx.h:617
RCC_TypeDef::CIFR
__IO uint32_t CIFR
Definition stm32l431xx.h:603
RCC_TypeDef::APB1ENR2
__IO uint32_t APB1ENR2
Definition stm32l431xx.h:619
RCC_TypeDef::RESERVED0
uint32_t RESERVED0
Definition stm32l431xx.h:605
RNG_TypeDef
RNG
Definition stm32l431xx.h:905
RNG_TypeDef::DR
__IO uint32_t DR
Definition stm32l431xx.h:908
RNG_TypeDef::CR
__IO uint32_t CR
Definition stm32l431xx.h:906
RNG_TypeDef::SR
__IO uint32_t SR
Definition stm32l431xx.h:907
RTC_TypeDef
Real-Time Clock
Definition stm32l431xx.h:642
RTC_TypeDef::TSTR
__IO uint32_t TSTR
Definition stm32l431xx.h:655
RTC_TypeDef::BKP3R
__IO uint32_t BKP3R
Definition stm32l431xx.h:666
RTC_TypeDef::TSSSR
__IO uint32_t TSSSR
Definition stm32l431xx.h:657
RTC_TypeDef::BKP20R
__IO uint32_t BKP20R
Definition stm32l431xx.h:683
RTC_TypeDef::BKP6R
__IO uint32_t BKP6R
Definition stm32l431xx.h:669
RTC_TypeDef::SHIFTR
__IO uint32_t SHIFTR
Definition stm32l431xx.h:654
RTC_TypeDef::BKP17R
__IO uint32_t BKP17R
Definition stm32l431xx.h:680
RTC_TypeDef::BKP30R
__IO uint32_t BKP30R
Definition stm32l431xx.h:693
RTC_TypeDef::BKP7R
__IO uint32_t BKP7R
Definition stm32l431xx.h:670
RTC_TypeDef::CALR
__IO uint32_t CALR
Definition stm32l431xx.h:658
RTC_TypeDef::DR
__IO uint32_t DR
Definition stm32l431xx.h:644
RTC_TypeDef::BKP0R
__IO uint32_t BKP0R
Definition stm32l431xx.h:663
RTC_TypeDef::BKP26R
__IO uint32_t BKP26R
Definition stm32l431xx.h:689
RTC_TypeDef::ALRMBR
__IO uint32_t ALRMBR
Definition stm32l431xx.h:651
RTC_TypeDef::BKP19R
__IO uint32_t BKP19R
Definition stm32l431xx.h:682
RTC_TypeDef::ALRMBSSR
__IO uint32_t ALRMBSSR
Definition stm32l431xx.h:661
RTC_TypeDef::ALRMASSR
__IO uint32_t ALRMASSR
Definition stm32l431xx.h:660
RTC_TypeDef::WPR
__IO uint32_t WPR
Definition stm32l431xx.h:652
RTC_TypeDef::TR
__IO uint32_t TR
Definition stm32l431xx.h:643
RTC_TypeDef::BKP18R
__IO uint32_t BKP18R
Definition stm32l431xx.h:681
RTC_TypeDef::BKP9R
__IO uint32_t BKP9R
Definition stm32l431xx.h:672
RTC_TypeDef::BKP29R
__IO uint32_t BKP29R
Definition stm32l431xx.h:692
RTC_TypeDef::BKP24R
__IO uint32_t BKP24R
Definition stm32l431xx.h:687
RTC_TypeDef::BKP13R
__IO uint32_t BKP13R
Definition stm32l431xx.h:676
RTC_TypeDef::BKP12R
__IO uint32_t BKP12R
Definition stm32l431xx.h:675
RTC_TypeDef::OR
__IO uint32_t OR
Definition stm32l431xx.h:662
RTC_TypeDef::BKP31R
__IO uint32_t BKP31R
Definition stm32l431xx.h:694
RTC_TypeDef::BKP25R
__IO uint32_t BKP25R
Definition stm32l431xx.h:688
RTC_TypeDef::SSR
__IO uint32_t SSR
Definition stm32l431xx.h:653
RTC_TypeDef::reserved
uint32_t reserved
Definition stm32l431xx.h:649
RTC_TypeDef::BKP23R
__IO uint32_t BKP23R
Definition stm32l431xx.h:686
RTC_TypeDef::BKP2R
__IO uint32_t BKP2R
Definition stm32l431xx.h:665
RTC_TypeDef::BKP22R
__IO uint32_t BKP22R
Definition stm32l431xx.h:685
RTC_TypeDef::BKP10R
__IO uint32_t BKP10R
Definition stm32l431xx.h:673
RTC_TypeDef::BKP4R
__IO uint32_t BKP4R
Definition stm32l431xx.h:667
RTC_TypeDef::ISR
__IO uint32_t ISR
Definition stm32l431xx.h:646
RTC_TypeDef::CR
__IO uint32_t CR
Definition stm32l431xx.h:645
RTC_TypeDef::BKP5R
__IO uint32_t BKP5R
Definition stm32l431xx.h:668
RTC_TypeDef::TAMPCR
__IO uint32_t TAMPCR
Definition stm32l431xx.h:659
RTC_TypeDef::TSDR
__IO uint32_t TSDR
Definition stm32l431xx.h:656
RTC_TypeDef::ALRMAR
__IO uint32_t ALRMAR
Definition stm32l431xx.h:650
RTC_TypeDef::BKP8R
__IO uint32_t BKP8R
Definition stm32l431xx.h:671
RTC_TypeDef::WUTR
__IO uint32_t WUTR
Definition stm32l431xx.h:648
RTC_TypeDef::BKP14R
__IO uint32_t BKP14R
Definition stm32l431xx.h:677
RTC_TypeDef::BKP11R
__IO uint32_t BKP11R
Definition stm32l431xx.h:674
RTC_TypeDef::PRER
__IO uint32_t PRER
Definition stm32l431xx.h:647
RTC_TypeDef::BKP27R
__IO uint32_t BKP27R
Definition stm32l431xx.h:690
RTC_TypeDef::BKP16R
__IO uint32_t BKP16R
Definition stm32l431xx.h:679
RTC_TypeDef::BKP21R
__IO uint32_t BKP21R
Definition stm32l431xx.h:684
RTC_TypeDef::BKP1R
__IO uint32_t BKP1R
Definition stm32l431xx.h:664
RTC_TypeDef::BKP15R
__IO uint32_t BKP15R
Definition stm32l431xx.h:678
RTC_TypeDef::BKP28R
__IO uint32_t BKP28R
Definition stm32l431xx.h:691
SAI_Block_TypeDef
Definition stm32l431xx.h:707
SAI_Block_TypeDef::DR
__IO uint32_t DR
Definition stm32l431xx.h:715
SAI_Block_TypeDef::CLRFR
__IO uint32_t CLRFR
Definition stm32l431xx.h:714
SAI_Block_TypeDef::CR1
__IO uint32_t CR1
Definition stm32l431xx.h:708
SAI_Block_TypeDef::SLOTR
__IO uint32_t SLOTR
Definition stm32l431xx.h:711
SAI_Block_TypeDef::FRCR
__IO uint32_t FRCR
Definition stm32l431xx.h:710
SAI_Block_TypeDef::IMR
__IO uint32_t IMR
Definition stm32l431xx.h:712
SAI_Block_TypeDef::SR
__IO uint32_t SR
Definition stm32l431xx.h:713
SAI_Block_TypeDef::CR2
__IO uint32_t CR2
Definition stm32l431xx.h:709
SAI_TypeDef
Serial Audio Interface
Definition stm32l431xx.h:702
SAI_TypeDef::GCR
__IO uint32_t GCR
Definition stm32l431xx.h:703
SDMMC_TypeDef
Secure digital input/output Interface
Definition stm32l431xx.h:724
SDMMC_TypeDef::ARG
__IO uint32_t ARG
Definition stm32l431xx.h:727
SDMMC_TypeDef::ICR
__IO uint32_t ICR
Definition stm32l431xx.h:739
SDMMC_TypeDef::DTIMER
__IO uint32_t DTIMER
Definition stm32l431xx.h:734
SDMMC_TypeDef::RESP3
__I uint32_t RESP3
Definition stm32l431xx.h:732
SDMMC_TypeDef::DCOUNT
__I uint32_t DCOUNT
Definition stm32l431xx.h:737
SDMMC_TypeDef::RESP2
__I uint32_t RESP2
Definition stm32l431xx.h:731
SDMMC_TypeDef::MASK
__IO uint32_t MASK
Definition stm32l431xx.h:740
SDMMC_TypeDef::DLEN
__IO uint32_t DLEN
Definition stm32l431xx.h:735
SDMMC_TypeDef::POWER
__IO uint32_t POWER
Definition stm32l431xx.h:725
SDMMC_TypeDef::FIFO
__IO uint32_t FIFO
Definition stm32l431xx.h:744
SDMMC_TypeDef::STA
__I uint32_t STA
Definition stm32l431xx.h:738
SDMMC_TypeDef::RESP1
__I uint32_t RESP1
Definition stm32l431xx.h:730
SDMMC_TypeDef::DCTRL
__IO uint32_t DCTRL
Definition stm32l431xx.h:736
SDMMC_TypeDef::CLKCR
__IO uint32_t CLKCR
Definition stm32l431xx.h:726
SDMMC_TypeDef::RESPCMD
__I uint32_t RESPCMD
Definition stm32l431xx.h:729
SDMMC_TypeDef::FIFOCNT
__I uint32_t FIFOCNT
Definition stm32l431xx.h:742
SDMMC_TypeDef::RESP4
__I uint32_t RESP4
Definition stm32l431xx.h:733
SDMMC_TypeDef::CMD
__IO uint32_t CMD
Definition stm32l431xx.h:728
SPI_TypeDef
Serial Peripheral Interface
Definition stm32l431xx.h:753
SPI_TypeDef::RXCRCR
__IO uint32_t RXCRCR
Definition stm32l431xx.h:759
SPI_TypeDef::DR
__IO uint32_t DR
Definition stm32l431xx.h:757
SPI_TypeDef::CR1
__IO uint32_t CR1
Definition stm32l431xx.h:754
SPI_TypeDef::TXCRCR
__IO uint32_t TXCRCR
Definition stm32l431xx.h:760
SPI_TypeDef::CRCPR
__IO uint32_t CRCPR
Definition stm32l431xx.h:758
SPI_TypeDef::SR
__IO uint32_t SR
Definition stm32l431xx.h:756
SPI_TypeDef::CR2
__IO uint32_t CR2
Definition stm32l431xx.h:755
SWPMI_TypeDef
Single Wire Protocol Master Interface SPWMI
Definition stm32l431xx.h:769
SWPMI_TypeDef::RFL
__IO uint32_t RFL
Definition stm32l431xx.h:776
SWPMI_TypeDef::BRR
__IO uint32_t BRR
Definition stm32l431xx.h:771
SWPMI_TypeDef::ICR
__IO uint32_t ICR
Definition stm32l431xx.h:774
SWPMI_TypeDef::TDR
__IO uint32_t TDR
Definition stm32l431xx.h:777
SWPMI_TypeDef::IER
__IO uint32_t IER
Definition stm32l431xx.h:775
SWPMI_TypeDef::OR
__IO uint32_t OR
Definition stm32l431xx.h:779
SWPMI_TypeDef::RDR
__IO uint32_t RDR
Definition stm32l431xx.h:778
SWPMI_TypeDef::ISR
__IO uint32_t ISR
Definition stm32l431xx.h:773
SWPMI_TypeDef::CR
__IO uint32_t CR
Definition stm32l431xx.h:770
SWPMI_TypeDef::RESERVED1
uint32_t RESERVED1
Definition stm32l431xx.h:772
SYSCFG_TypeDef
System configuration controller
Definition stm32l431xx.h:788
SYSCFG_TypeDef::SWPR
__IO uint32_t SWPR
Definition stm32l431xx.h:794
SYSCFG_TypeDef::CFGR1
__IO uint32_t CFGR1
Definition stm32l431xx.h:790
SYSCFG_TypeDef::SKR
__IO uint32_t SKR
Definition stm32l431xx.h:795
SYSCFG_TypeDef::MEMRMP
__IO uint32_t MEMRMP
Definition stm32l431xx.h:789
SYSCFG_TypeDef::SCSR
__IO uint32_t SCSR
Definition stm32l431xx.h:792
SYSCFG_TypeDef::CFGR2
__IO uint32_t CFGR2
Definition stm32l431xx.h:793
TIM_TypeDef
TIM
Definition stm32l431xx.h:804
TIM_TypeDef::DIER
__IO uint32_t DIER
Definition stm32l431xx.h:808
TIM_TypeDef::CCMR2
__IO uint32_t CCMR2
Definition stm32l431xx.h:812
TIM_TypeDef::CCER
__IO uint32_t CCER
Definition stm32l431xx.h:813
TIM_TypeDef::EGR
__IO uint32_t EGR
Definition stm32l431xx.h:810
TIM_TypeDef::CCR3
__IO uint32_t CCR3
Definition stm32l431xx.h:820
TIM_TypeDef::SMCR
__IO uint32_t SMCR
Definition stm32l431xx.h:807
TIM_TypeDef::CCR5
__IO uint32_t CCR5
Definition stm32l431xx.h:827
TIM_TypeDef::BDTR
__IO uint32_t BDTR
Definition stm32l431xx.h:822
TIM_TypeDef::CCR6
__IO uint32_t CCR6
Definition stm32l431xx.h:828
TIM_TypeDef::CNT
__IO uint32_t CNT
Definition stm32l431xx.h:814
TIM_TypeDef::OR2
__IO uint32_t OR2
Definition stm32l431xx.h:829
TIM_TypeDef::OR3
__IO uint32_t OR3
Definition stm32l431xx.h:830
TIM_TypeDef::CCR4
__IO uint32_t CCR4
Definition stm32l431xx.h:821
TIM_TypeDef::OR1
__IO uint32_t OR1
Definition stm32l431xx.h:825
TIM_TypeDef::PSC
__IO uint32_t PSC
Definition stm32l431xx.h:815
TIM_TypeDef::RCR
__IO uint32_t RCR
Definition stm32l431xx.h:817
TIM_TypeDef::CR1
__IO uint32_t CR1
Definition stm32l431xx.h:805
TIM_TypeDef::DMAR
__IO uint32_t DMAR
Definition stm32l431xx.h:824
TIM_TypeDef::CCR2
__IO uint32_t CCR2
Definition stm32l431xx.h:819
TIM_TypeDef::CCR1
__IO uint32_t CCR1
Definition stm32l431xx.h:818
TIM_TypeDef::CCMR1
__IO uint32_t CCMR1
Definition stm32l431xx.h:811
TIM_TypeDef::CCMR3
__IO uint32_t CCMR3
Definition stm32l431xx.h:826
TIM_TypeDef::ARR
__IO uint32_t ARR
Definition stm32l431xx.h:816
TIM_TypeDef::DCR
__IO uint32_t DCR
Definition stm32l431xx.h:823
TIM_TypeDef::SR
__IO uint32_t SR
Definition stm32l431xx.h:809
TIM_TypeDef::CR2
__IO uint32_t CR2
Definition stm32l431xx.h:806
TSC_TypeDef
Touch Sensing Controller (TSC)
Definition stm32l431xx.h:839
TSC_TypeDef::ICR
__IO uint32_t ICR
Definition stm32l431xx.h:842
TSC_TypeDef::IOHCR
__IO uint32_t IOHCR
Definition stm32l431xx.h:844
TSC_TypeDef::IOGCSR
__IO uint32_t IOGCSR
Definition stm32l431xx.h:852
TSC_TypeDef::RESERVED2
uint32_t RESERVED2
Definition stm32l431xx.h:847
TSC_TypeDef::IER
__IO uint32_t IER
Definition stm32l431xx.h:841
TSC_TypeDef::IOCCR
__IO uint32_t IOCCR
Definition stm32l431xx.h:850
TSC_TypeDef::ISR
__IO uint32_t ISR
Definition stm32l431xx.h:843
TSC_TypeDef::CR
__IO uint32_t CR
Definition stm32l431xx.h:840
TSC_TypeDef::RESERVED4
uint32_t RESERVED4
Definition stm32l431xx.h:851
TSC_TypeDef::RESERVED1
uint32_t RESERVED1
Definition stm32l431xx.h:845
TSC_TypeDef::IOASCR
__IO uint32_t IOASCR
Definition stm32l431xx.h:846
TSC_TypeDef::RESERVED3
uint32_t RESERVED3
Definition stm32l431xx.h:849
TSC_TypeDef::IOSCR
__IO uint32_t IOSCR
Definition stm32l431xx.h:848
USART_TypeDef
Universal Synchronous Asynchronous Receiver Transmitter
Definition stm32l431xx.h:861
USART_TypeDef::BRR
__IO uint32_t BRR
Definition stm32l431xx.h:865
USART_TypeDef::ICR
__IO uint32_t ICR
Definition stm32l431xx.h:872
USART_TypeDef::GTPR
__IO uint16_t GTPR
Definition stm32l431xx.h:866
USART_TypeDef::RQR
__IO uint16_t RQR
Definition stm32l431xx.h:869
USART_TypeDef::RESERVED2
uint16_t RESERVED2
Definition stm32l431xx.h:867
USART_TypeDef::RESERVED3
uint16_t RESERVED3
Definition stm32l431xx.h:870
USART_TypeDef::RESERVED4
uint16_t RESERVED4
Definition stm32l431xx.h:874
USART_TypeDef::CR1
__IO uint32_t CR1
Definition stm32l431xx.h:862
USART_TypeDef::ISR
__IO uint32_t ISR
Definition stm32l431xx.h:871
USART_TypeDef::RESERVED5
uint16_t RESERVED5
Definition stm32l431xx.h:876
USART_TypeDef::RDR
__IO uint16_t RDR
Definition stm32l431xx.h:873
USART_TypeDef::TDR
__IO uint16_t TDR
Definition stm32l431xx.h:875
USART_TypeDef::CR3
__IO uint32_t CR3
Definition stm32l431xx.h:864
USART_TypeDef::RTOR
__IO uint32_t RTOR
Definition stm32l431xx.h:868
USART_TypeDef::CR2
__IO uint32_t CR2
Definition stm32l431xx.h:863
VREFBUF_TypeDef
VREFBUF
Definition stm32l431xx.h:884
VREFBUF_TypeDef::CCR
__IO uint32_t CCR
Definition stm32l431xx.h:886
VREFBUF_TypeDef::CSR
__IO uint32_t CSR
Definition stm32l431xx.h:885
WWDG_TypeDef
Window WATCHDOG
Definition stm32l431xx.h:894
WWDG_TypeDef::CR
__IO uint32_t CR
Definition stm32l431xx.h:895
WWDG_TypeDef::CFR
__IO uint32_t CFR
Definition stm32l431xx.h:896
WWDG_TypeDef::SR
__IO uint32_t SR
Definition stm32l431xx.h:897
system_stm32l4xx.h
CMSIS Cortex-M4 Device System Source File for STM32L4xx devices.